DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed February 2, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the specification, drawings, and claims have overcome each and every objection and 35 U.S.C. § 112 rejection previously presented in the Non-Final Office Action mailed October 31, 2025, with one exception outlined below.
The objection to paragraph 49 remains because paragraph 49 of the instant specification was not amended in accordance with the objection.
Response to Arguments
Applicant’s arguments, see pages 11-12, filed February 2, 2026, with respect to the rejections of claims 1-20 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference Eschauzier et al. (Patent Number US 7,812,665 B2), hereafter referred to as Eschauzier.
Specification
The disclosure is objected to because of the following informality:
On Paragraph 49, line 3, replace “voltages” with “voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 12-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gabillard et al. (Patent Number US 6,914,479 B1), hereafter referred to as Gabillard, in view of Eschauzier
Regarding claim 1, Gabillard discloses:
An analog offset cancellation circuit (Gabillard, Fig. 2) comprising: a multi-stage amplifier (Fig. 2, see Elements 22 and 12) configured to receive first and second input voltages (Fig. 2, see INp and INn) and generate first and second output voltages (Fig. 2, see OUTp and OUTn); and a feedback loop circuit (Fig. 2, see Elements 13’ and 23) configured to generate first and second control voltages (Fig. 2, see FBp and FBn) in response to at least one DC level associated with the first and second output voltages (Col. 1, lines 41-49) and apply the first and second control voltages to the multi-stage amplifier (Fig. 2, see connection between FBp, FBn, and nodes between Elements 22 and 12) to continuously cancel a DC offset of the multi-stage amplifier following the offset cancellation operation (Col. 1, lines 41-49), but fails to disclose a comparator configured to compare the first and second output voltages; a digital to analog converter (DAC) configured to provide an offset cancellation voltage to the comparator during an offset cancellation operation for the comparator.
However, Eschauzier teaches a comparator (Eschauzier, Fig. 1, see amplifier “A”, see also Col. 2, lines 50-52) configured to compare the first and second output voltages (Fig. 1, see comparator inputs at Vin); a digital to analog converter (DAC) (Fig. 1, see “D/A”) configured to provide an offset cancellation voltage to the comparator during an offset cancellation operation for the comparator (Col. 2, lines 46-48).
Gabillard and Eschauzier are both considered to be analogous to the claimed invention because they are in the same field of improving offset cancellation circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gabillard to incorporate the teachings of Eschauzier to include the comparator circuit of Eschauzier in the circuit of Gabillard, which would have the effect of providing additional offset compensation for the circuit of Gabillard (Eschauzier, Col. 2, lines 42-45).
Regarding claim 2, Gabillard further discloses:
wherein the feedback loop circuit includes a first operational amplifier (Gabillard, Fig. 2, 16) configured to receive the first and second output voltages (Fig. 2, see connection between 16 and 12) and generate the first and second control voltages in response to the first and second output voltages (Fig. 2, see outputs of 16 and FBp and FBn).
Regarding claim 4, Gabillard further discloses:
wherein the first operational amplifier is configured to generate the first and second control voltages in response to a DC level difference between the first and second output voltages (Gabillard, Col. 1, lines 41-49).
Regarding claim 5, Gabillard further discloses:
wherein a DC level difference between the first and second control voltages, as generated by the feedback loop circuit, is the same as the DC level difference between the first and second output voltages (Gabillard, Abstract, lines 15-19).
Regarding claim 6, Gabillard further discloses:
wherein the first operational amplifier operates as a low pass filter (Gabillard, Col. 1, lines 41-47).
Regarding claim 7, Gabillard further discloses:
wherein a first amplifier of the multi-stage amplifier (Gabillard, Fig. 2, 22) is configured to receive the first and second input voltages (Fig. 2, see connection between INp, INn, and 22), generate a first voltage signal and a second voltage signal (Fig. 2, see outputs of 22), and provide the first voltage signal and the second voltage signal to a second amplifier of the multi-stage amplifier (Fig. 2, see connection between 22 and 12), and the second amplifier is configured to receive the first voltage signal and the second voltage signal (Fig. 2, see connection between 22 and 12), receive the first and second control voltages from the feedback loop circuit (Fig. 2, see connection between 12 and 23), and adjust the first voltage signal and the second voltage signal, such that DC levels of the first and second output voltages are the same (Abstract, lines 15-19).
Regarding claim 12, Gabillard discloses:
A method of operating an analog offset cancellation circuit for canceling a DC offset of a multi-stage amplifier (Gabillard, Fig. 2), the method comprising: and thereafter, performing, by operation of a feedback loop circuit (Fig. 2, see Elements 13’ and 23), a continuous canceling of the DC offset of the multi-stage amplifier (Col. 1, lines 41-49), wherein the performing of the continuous canceling of the DC offset of the multi-stage amplifier includes receiving first and second output voltages generated by the multi-stage amplifier (Fig. 2, see connection between 16 and output of multi-stage amplifier 12), generating first and second control voltages in response to the first and second output voltages (Fig. 2, see FBp and FBn), and providing the first and second control voltages to the multi-stage amplifier (Fig. 2, see connection between FBp, FBn, and nodes between Elements 22 and 12), such that DC levels of the first and second output voltages are the same (Col. 1, lines 41-49), but fails to disclose providing, by operation of a digital-to-analog converter (DAC), an offset cancellation voltage to a comparator during an offset cancellation operation of the comparator.
However, Eschauzier teaches providing, by operation of a digital-to-analog converter (DAC) (Eschauzier, Fig. 1, see “D/A”), an offset cancellation voltage to a comparator during an offset cancellation operation of the comparator (Col. 2, lines 46-48).
Gabillard and Eschauzier are both considered to be analogous to the claimed invention because they are in the same field of improving offset cancellation circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gabillard to incorporate the teachings of Eschauzier to include the comparator circuit of Eschauzier in the circuit of Gabillard, which would have the effect of providing additional offset compensation for the circuit of Gabillard (Eschauzier, Col. 2, lines 42-45).
Regarding claim 13, Gabillard further discloses:
wherein the first and second control voltages are generated further in response to a DC level difference between the first and second output voltages (Gabillard, Col. 1, lines 41-49).
Regarding claim 14, Gabillard further discloses:
wherein a DC level difference between the first and second control voltages is the same as the DC level difference between the first and second output voltages (Gabillard, Abstract, lines 15-19).
Regarding claim 15, Gabillard fails to disclose:
wherein the providing, by operation of the digital-to- analog converter (DAC), of the offset cancellation voltage to the comparator during the offset cancellation operation of the comparator includes: receiving at a controller, an offset voltage from the comparator; generating, by operation of the controller, a cancellation signal in response to the offset voltage; generating, by operation of the DAC, the offset cancellation voltage in response to the cancellation signal; and providing the offset cancellation voltage from the DAC to the comparator.
However, Eschauzier further teaches wherein the providing, by operation of the digital-to- analog converter (DAC), of the offset cancellation voltage to the comparator during the offset cancellation operation of the comparator includes: receiving at a controller, an offset voltage from the comparator (Eschauzier, Fig. 1, see connection between comparator amplifier “A” and controller formed of elements “COMP” and “SAR”); generating, by operation of the controller, a cancellation signal in response to the offset voltage (Fig. 1, see output of “SAR”); generating, by operation of the DAC, the offset cancellation voltage in response to the cancellation signal (Col. 2, lines 46-48); and providing the offset cancellation voltage from the DAC to the comparator (Col. 2, lines 46-48).
Gabillard and Eschauzier are both considered to be analogous to the claimed invention because they are in the same field of improving offset cancellation circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gabillard to incorporate the teachings of Eschauzier to include the comparator circuit of Eschauzier in the circuit of Gabillard, which would have the effect of providing additional offset compensation for the circuit of Gabillard (Eschauzier, Col. 2, lines 42-45).
Regarding claim 16, Gabillard further discloses:
wherein the feedback loop circuit comprises an operational amplifier configured to operate as a low pass filter (Gabillard, Col. 1, lines 41-47).
Regarding claim 17, Gabillard further discloses:
wherein the multi-stage amplifier includes: a first amplifier (Gabillard, Fig. 2, 22) configured to receive first and second input voltages (Fig. 2, see connection between INp, INn, and 22), and generate corresponding voltage signals in response to the first and second input voltages (Fig. 2, see outputs of 22); and a second amplifier (Fig. 2, see connection between 22 and 12) configured to receive the first and second control voltages and the corresponding voltage signals from the first amplifier (Fig. 2, see connection between 22, 12, and 23), and generate the first and second output voltages in response to the first and second control voltages and the corresponding voltage signals (Fig. 2, see outputs of 12, and inputs from 22 and 23), wherein the corresponding voltage signals are adjusted by the second amplifier such that the DC levels of the first and second output voltages are the same (Abstract, lines 15-19).
Regarding claim 18, Gabillard further discloses:
wherein the multi-stage amplifier includes: a first amplifier (Gabillard, Fig. 2, 22) configured to receive first and second input voltages (Fig. 2, see connection between 22 and INp and INn), and generate corresponding first voltage signals in response to the first and second input voltages (Fig. 22, see outputs of 22); a second amplifier (Fig. 2, see first amplifier in 12) configured to receive the first and second control voltages and the corresponding first voltage signals (Fig. 2, see connection between 22, 23, and the first amplifier in 12), adjust DC levels of the corresponding first voltage signals to be the same (Abstract, lines 15-19), and generate corresponding second voltage signals in response to the first and second control voltages and the corresponding first voltage signals (Fig. 2, see outputs of first amplifier in 12); and a third amplifier (Fig. 2, see second amplifier in 12) configured to receive the corresponding second voltage signals (Fig. 12, see connection between second amplifier in 12 and first amplifier in 12), and generate the first and second output voltages in response to the corresponding second voltage signals (Fig. 2, see outputs of second amplifier in 12).
Regarding claim 20, Gabillard further discloses:
A wired communication receiver configured to receive high-speed data (Gabillard, Fig. 2) the wired communication receiver comprising: an offset cancellation circuit configured to receive the high-speed data from a channel (Gabillard, Fig. 2), wherein the offset cancellation circuit includes: a multi-stage amplifier (Fig. 2, see Elements 22 and 12) including first and second amplifiers (Fig. 2, see Elements 22 and 12), configured to receive first and second input signals (Fig. 2, see INp and INn), and further configured to generate first and second output signals (Fig. 2, see OUTp and OUTn); and a feedback loop circuit (Fig. 2, see Elements 13’ and 23) configured to generate first and second control voltages (Fig. 2, see FBp and FBn) in response to at least one DC level associated with the first and second output signals (Col. 1, lines 41-49) and apply the first and second control voltages to the multi-stage amplifier (Fig. 2, see connection between FBp, FBn, and nodes between Elements 22 and 12) to continuously cancel a DC offset of the multi-stage amplifier following the offset cancellation operation (Col. 1, lines 41-49), but fails to disclose a comparator configured to compare the first and second output signals; a digital to analog converter (DAC) configured to provide an offset cancellation voltage to the comparator during an offset cancellation operation for the comparator.
However, Eschauzier teaches a comparator (Eschauzier, Fig. 1, see comparator amplifier “A”) configured to compare the first and second output signals (Fig. 1, see comparator inputs Vin); a digital to analog converter (DAC) (Fig. 1, see “D/A”) configured to provide an offset cancellation voltage to the comparator during an offset cancellation operation for the comparator (Col. 2, lines 46-48).
Gabillard and Eschauzier are both considered to be analogous to the claimed invention because they are in the same field of improving offset cancellation circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gabillard to incorporate the teachings of Eschauzier to include the comparator circuit of Eschauzier in the circuit of Gabillard, which would have the effect of providing additional offset compensation for the circuit of Gabillard (Eschauzier, Col. 2, lines 42-45).
Claims 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gabillard in view of Eschauzier as applied to claims 2 and 12, respectively, above, and further in view of Price et al. (Patent Number US 11,239,807 B1), as cited by applicant, hereafter referred to as Price.
Regarding claim 3, Gabillard and Eschauzier fail to disclose:
wherein the feedback loop circuit is configured to receive the first and second output voltages in response to a virtual grounding of the first operational amplifier.
However, Price teaches wherein the feedback loop circuit is configured to receive the first and second output voltages in response to a virtual grounding of the first operational amplifier (Price, Col. 7, lines 16-18).
Gabillard, Eschauzier, and Price are all considered to be analogous to the claimed invention because they are in the same field of improving offset cancellation circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gabillard to incorporate the teachings of Price to include the switch of Price in the circuit of Gabillard, which would have the effect of enabling a calibration mode for the circuit of Gabillard (Price, Col. 7, lines 16-29).
Regarding claim 19, Gabillard and Eschauzier fail to disclose:
further comprising: after the providing, by operation of the DAC, of the offset cancellation voltage to the comparator during the offset cancellation operation for the comparator, and before the performing, by operation of the feedback loop circuit, of the continuous canceling of the DC offset of the multi-stage amplifier, activating a switch between a first signal path passing the first output voltage to a first input of the comparator and a second signal path passing the second output voltage to a second input of the comparator.
However, Price teaches further comprising: after the providing, by operation of the DAC, of the offset cancellation voltage to the comparator during the offset cancellation operation for the comparator, and before the performing, by operation of the feedback loop circuit, of the continuous canceling of the DC offset of the multi-stage amplifier, activating a switch (Price, Fig. 1, 112) between a first signal path passing the first output voltage to a first input of the comparator and a second signal path passing the second output voltage to a second input of the comparator (Fig. 1, see connection between VIPP and VIPN via switch 112, see also Col. 7, lines 16-18).
Gabillard, Eschauzier, and Price are all considered to be analogous to the claimed invention because they are in the same field of improving offset cancellation circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gabillard to incorporate the teachings of Price to include the switch of Price in the circuit of Gabillard, which would have the effect of enabling a calibration mode for the circuit of Gabillard (Price, Col. 7, lines 16-29).
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Gabillard in view of Eschauzier as applied to claim 7 above, and further in view of Zhang et al. (Patent Number US 11,264,956 B2), as cited by applicant, hereafter referred to as Zhang.
Regarding claim 8, Gabillard and Eschauzier fail to disclose:
wherein the second amplifier includes a first transistor receiving the first voltage signal, a second transistor receiving the second voltage signal, a third transistor receiving the first control voltage and a fourth transistor receiving the second control voltage, as a result of receiving the first control voltage, the first voltage signal provided to the first transistor is adjusted, as a result of receiving the second control voltage, the second voltage signal provided to the second transistor is adjusted, and as a result of adjusting the first voltage signal provided to the first transistor and adjusting the second voltage signal provided to the second transistor, the DC levels of the first and second output voltages are the same.
However, Zhang teaches wherein the second amplifier includes a first transistor (Zhang, Fig. 5, Q5) receiving the first voltage signal (Fig. 5, see connection between Q5 and Inp), a second transistor (Fig. 5, Q6) receiving the second voltage signal (Fig. 5, see connection between Q6 and Inn), a third transistor (Fig. 5, Q7) receiving the first control voltage (Fig. 5, see connection between Q7 and DCinn) and a fourth transistor (Fig. 5, Q8) receiving the second control voltage (Fig. 5, see connection between Q8 and DCinp), as a result of receiving the first control voltage, the first voltage signal provided to the first transistor is adjusted (Fig. 5, see connection between Q5 and Q7, see also Col. 5, lines 26-30), as a result of receiving the second control voltage, the second voltage signal provided to the second transistor is adjusted (Fig. 5, see connection between Q6 and Q8, see also Col. 5, lines 26-30), and as a result of adjusting the first voltage signal provided to the first transistor and adjusting the second voltage signal provided to the second transistor, the DC levels of the first and second output voltages are the same (Col. 5, lines 26-30).
Gabillard, Eschauzier, and Zhang are all considered to be analogous to the claimed invention because they are in the same field of improving offset cancellation circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gabillard to incorporate the teachings of Zhang to include the amplifier of Zhang as the second amplifier of Gabillard, which would have the effect of providing an amplifier suitable for combining offset compensation signals (Zhang, Col. 5, lines 26-30).
Regarding claim 10, Gabillard further discloses:
wherein the feedback loop circuit is configured to reduce a DC level difference between the first and second control voltages (Gabillard, Abstract, lines 15-19).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gabillard in view of Eschauzier as applied to claim 1 above, and further in view of Furukawa (Patent Number US 5,642,070 A), hereafter referred to as Furukawa.
Regarding claim 11, Gabillard and Eschauzier fail to disclose:
further comprising: a signal processing circuit configured to compensate for loss in at least one of the first or second input voltages.
However, Furukawa teaches further comprising: a signal processing circuit (Furukawa, Fig. 7, 100) configured to compensate for loss in at least one of the first or second input voltages. (Col. 3, lines 1-11).
Gabillard, Eschauzier, and Furukawa are all considered to be analogous to the claimed invention because they are in the same field of improving offset cancellation circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gabillard to incorporate the teachings of Furukawa to include the signal processing circuit of Furukawa in the circuit of Gabillard, which would have the effect of increasing stability (Furukawa, Col. 3, lines 1-11).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art, when taken alone, or in combination cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the applicant.
The closest prior art is Gabillard et al. (Patent Number US 6,914,479 B1), hereafter referred to as Gabillard. Gabillard discloses a feedback control loop for offset voltage cancellation in a multi-stage amplifier, but fails to disclose the feedback control loop including “a second operational amplifier configured to receive a first common mode voltage from the first amplifier through a first connection path bypassing the first operational amplifier”, as recited by claim 9, so therefore Gabillard is not suitable for the application as claimed in claim 9.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (Patent Publication Number US 2019/0068176 A1) discloses (Fig. 2) a feedback offset cancellation loop including a comparator and a DAC.
Hoang et al. (Patent Number US 9,203,352 B1) discloses (Fig. 2) a 3-stage amplifier with an offset cancellation loop feeding into the second stage amplifier.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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