DETAILED ACTION
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
As far as amendment to claim 1, and arguments related to that amendments are concerned, there is now a new 112, indefiniteness issue related to amendment to claim 1 (see 112 rejections below). Examiner will address the arguments (mostly by adding additional explanations to the body of rejection of claim 1), but they are of secondary importance due to the presence of a new 112 issue.
As far as arguments to claim 9 (and various dependent claims) are concerned, they are all addressed below.
Applicant argues (page 6 of Remarks, middle of the page) that “while the sealant in the present application is similar to the encapsulation layer, it cannot function as a buffer material due to their inherently different physical properties”. This argument is found to be unpersuasive. The rejection of claim 1 below now includes a lot more detail as to (1) how the “opaque coatings” of Shim read on “solidified interface fillers” limitations, (2) how the definition of word “buffer” is understood in the semiconductor industry and as it applies to “opaque coatings” of Shim, and (3) how the “encapsulant” of Shim meets the definition of the term “sealant”. See rejection of claim 1, specifically the portion related to the above limitations for detailed explanations.
Applicant argues (page 6 of Remarks, middle of the page) that “claim 1 … now includes … claim 4, specifies that the sealant is formed … Therefore, amended claim 1 expressly limits the location and function of the sealant”. This argument is found to be unpersuasive. The rejection of claim 1 below now includes a lot more detail as to how both the location and function of the sealant are both explicitly taught by Shim. See rejection of claim 1, specifically the portion related to the above limitations for detailed explanations.
Applicant argues (page 6 of Remarks, near bottom of the page and on to the top of page 7) regarding the limitations of claim 9 - that are related to “first clean process” “forming an interfacial material ...”, “sawing along …” and “performing a second clean process” – that the “cited reference fails to disclose or suggest the specific combination and critical sequence of processing steps defined therein” and so on. This argument is found to be unpersuasive, because the obviousness of the steps, especially of the cited “first clean process” and “second clean process” was clearly elucidated in rejections of claims 7 & 8. To belabor the point slightly, in semiconductor industry, as is notoriously well-known that the usage of “clean process” steps is mandatory. Even general public knows that people in semiconductor industry walk around in “bunny suits” [Wingdings font/0xE0] to make sure that no speck of dirt falls anywhere. Therefore, performing “first clean process” after “sawing glass cover” is something that is obvious to even general public (never mind a POSITA). Similarly, performing “second clean process” after “sawing along the centerline …” is also something that is obvious to even general public (never mind a POSITA). The reasoning, that is clear even to a member of general public, is that “sawing” produces dust. Hence, even a member of general public would recognize that “cleaning” after “sawing” is mandatory in semiconductor industry. Hence, the Applicant’s argument is found unpersuasive.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 & 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 & 4 recite the limitation "the sealant" (line before last in both claims 1 & 4). There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2023/0122384) by Shim et al (“Shim”).
Regarding claim 1, Shim discloses in FIGs. 4a-e and related text, e.g., a method for manufacturing an image sensor module, including:
disposing a glass cover (FIG. 4a, 450) on a substrate (480);
sawing the glass cover (FIGs. 4b-c) into a plurality of glass units (two 450b’s are shown in FIG. 4c);
forming a plurality of solidified interface fillers (FIG. 4d, 462 “opaque coatings” – multiple ones are shown; later becomes FIG. 4e, 162, and even later becomes FIG. 7e, 762; they are “solidified” because they are formed of materials that start as liquids or semi-solids (see par. 56; most of materials listed there for “opaque coating” start as liquid/semi-solid; then they become “solidified”; they are also, “fillers” because they fill the recess (see par. 47)), each being between the adjacent glass units (see FIG. 4d);
sawing (see FIG. 4e) along the centerline of each solidified interface filler to form a plurality of independent electronic semi-finished products for complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS) packaging (two such products are shown); and
performing an image sensor process to obtain the image sensor module (results of such an image sensor process are shown in FIG. 7e, which shows as a finished “image sensor module”),
wherein the solidified interface fillers (FIG. 7e, 762) serve as a buffer material between the electronic semi-finished products and the sealant (see FIG. 7e; first of all, the “solidified interface fillers” 762 are present directly between “electronic semi-finished product” 750 and “sealant” 770 [Wingdings font/0xE0] hence, the limitations of “between” are met; second of all, as far as limitations of “buffer material” [Wingdings font/0xE0] no “special definition” for the term was found in Applicant’s specification – at the very least, nothing that would qualify as “special definition” in accordance with USPTO procedures; therefore, the Broadest Reasonable Interpretation, consistent with the Specification (but without reading in of additional limitations) has been used; the standard semiconductor industry definition of the term “buffer” is “an intermediate or transitional layer/material that is between two layers and that accommodates physical/chemical inconsistencies between the two layers”; in the instant case, “solidified interface fillers” 162/462/762 exist specifically, according to par. 59: “The opaque coating on the side surfaces protects side walls of the cover, reducing cracking during processing”; the quote is from embodiment of FIGs. 4a-e, which is specifically the embodiment under discussion; thus 162/462/762 is an epitome of “buffer material”, because it is an “intermediate or transitional layer between two layers (the layers were listed above) that accommodates physical/chemical inconsistencies between the two layers”; in the instant case, “physical inconsistencies” [Wingdings font/0xE0] cracking during processing is possible without it, as Shim explicitly teaches), which is applied around a periphery region of each electronic semi-finished product (see FIG. 7d; “filler” 770 is applied around opposite sides of “electronic semi-finished product” 750; hence, “around a periphery).
Shim does not explicitly state that the process is specifically “molded ball grid array (ImBGA) process”.
To elaborate briefly on the above, FIGs. 1b1-1b4, 7e and 8 all appear to show “molded ball grid array”. However, it is not explicitly stated as such.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Shim with “molded ball grid array (ImBGA) process”, in order to equip the image sensor module with a notoriously well-known and popular signal interface (ball grid array interface, specifically).
Examiner’s Note: as a matter of evidence to support Examiner’s assertion that the “ball grid array” interface is both popular and notoriously well-known, Examiner performed a quick search for “(molded) WITH (ball grid array)”. The search string is quite specific and does not look for synonyms and acronyms. Nevertheless, the result is 755 references, just in US patents and PGPUB databases (hence, popular) and per US-5,583,378, column 1, lines 30-35, such an interface was first described in US-5,241,133, dated 1993 (hence, notoriously well-known).
Regarding claim 2, Shim discloses in FIGs. 4a-e and related text, e.g., wherein each electronic semi-finished product forms an ImBGA module in the ImBGA process so that the image sensor module is obtained (by definition; one does not make functional and valuable semi-finished products to throw them away; a module is shown in FIG. 7e; hence, each of the functional and valuable semi-finished products was used to make such a module).
Regarding claim 3, Shim discloses in FIGs. 4a-e and related text, e.g., wherein each electronic semi-finished product is attached to a chip in the ImBGA process (by definition; one does not make functional and valuable semi-finished products to throw them away; a product is shown to be attached to chip in FIG. 7e; hence, each of the functional and valuable semi-finished products was used to be so attached, in a specific design application).
Regarding claim 4, Shim discloses in FIGs. 4a-e and related text, e.g., wherein, after each electronic semi-finished product (“protective cover” 750”) is attached to the chip (FIG. 7c; 750 is attached to 737), a sealing process (FIG. 7d) is further performed by applying the sealant (“encapsulant” 770) to protect each electronic semi-finished product (see par. 73: “The encapsulant covers… sides of the protective cover”).
Regarding claim 5, Shim discloses in FIGs. 4a-e and related text, e.g., wherein the chip is located on an IC board (FIG. 7d, 710), and various solder balls are further formed on an opposite surface of the IC board (FIG. 7e, “solder balls” are unmarked) after the sealing process, thereby obtaining the ImBGA module (FIG. 7e).
Regarding claim 7, Shim discloses in FIGs. 4a-e and related text, e.g., substantially the entire claim structure, as recited in above claims, but does not explicitly state “wherein a first clean process is performed prior to the step of forming the solidified interface fillers between the adjacent glass units”.
To elaborate briefly on the above, in FIG. 4c Shim teaches sawing 450 into pieces. It is notoriously well-known that after one uses a saw, one has to do some sort of cleaning in order to remove the byproducts. It is not simply notoriously well-known, it is a common sense in a host of high-tech fields and low-tech fields, from bone sawing surgery, to wood cutting carpentry. However, Shim does not explicitly state it.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Shim with “wherein a first clean process is performed prior to the step of forming the solidified interface fillers between the adjacent glass units”, in order to clean the byproducts of sawing process of FIG. 4c, before forming “solidified interface fillers (FIG. 4d, 462), and thus guarantee a properly clean semiconductor fabrication plant environment, which is notoriously well-known for its need of cleanliness (cleanliness is exemplified in general public’s mind through “bunny suits”).
Regarding claim 8, Shim discloses in FIGs. 4a-e and related text, e.g., wherein a second clean process and a debonding process are further performed after the step of sawing along the centerline of each solidified interface filler (see rejection of claim 7 above; same logic applies; it is a sawing step; fabrication plant’s cleanliness requirements, would necessitate a cleaning step of some sort).
Regarding claim 9, Shim discloses in FIGs. 4a-e and related text, e.g., a method for manufacturing an image sensor module, including:
disposing a glass cover on a substrate (see claim 1);
sawing the glass cover into a plurality of glass units (see claim 1);
performing a first clean process (see claim 7);
forming an interfacial material between the adjacent glass units (see par. 56; it teaches use of “epoxy mold compound (EMC)”; EMC reads on interfacial material);
solidifying the interfacial material to form various solidified interface fillers (see claim 1; as far as solidifying, this is what “epoxy mold compound” does);
sawing along the centerline of each solidified interface fillers (see claim 1);
performing a second clean process (see claim 8);
performing a debonding process to form a plurality of independent electronic semi-finished products for complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS) packaging (“debonding” and related limitations are inherent; the individual “semi-finished products” are used later, as was discussed above, regarding FIGs. 7a-e; hence, “debonding” happened); and
performing an image sensor molded ball grid array (ImBGA) process where each electronic semi-finished product forms an ImBGA module (see claims 1-4), thereby obtaining the image sensor module (see claim 1).
Regarding claim 10, Shim discloses in FIGs. 4a-e and related text, e.g., wherein each electronic semi-finished product is attached to the chip in the ImBGA process (see claim 2);
thereafter, the chip is arranged on an IC board (see claim 5), and a sealing process is further performed by applying a sealant on a periphery region of each electronic semi-finished product to protect each electronic semi-finished product (see claim 4); and
various solder balls are further formed on an opposite surface of the IC board subsequent to the sealing process, thereby obtaining the ImBGA module (see claim 5).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/30/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
