DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This Action is in response to communications filed 12/23/2025.
Claims 3, 17, and 22-27 have been cancelled.
Claims 1, 2, 4, 6, 8, and 10-16 have been amended.
Claims 1, 2, 4, 6, 8, and 10-16 are pending.
Claims 1, 2, 4, 6, 8, and 10-16 are rejected.
Response to Arguments
In Remarks filed on 12/23/2025, Applicant substantially argues:
On Pages 11-12, the applied references, including Ware, Yin and Gupta, fail to disclose the amended limitations of claim 1, and similarly amended claim 11, including selection of the power mode for a SRAM device based on a count associated with a chip selection signal. In particular, Applicant points to the cited references as failing to disclose a chip selection signal being provided for each chip of the SRAM device as Yin, at best, addresses accessing at a bank level and therefore does not refer to accesses individual SRAM chips. Applicant’s arguments filed have been fully considered but they are moot in view of the current rejections made in response to Applicant’s amendments. The rejections herein are revised to address Applicant’s amendments.
The applied references fail to disclose the limitations of claims 2, 4, 6, 8, 10, and 12-16 by virtue of dependency on respective independent claims 1 and 11 for the reasons identified above. Applicant’s arguments filed have been fully considered but they are moot in view of the current rejections made in response to Applicant’s amendments.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated December 23, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4, 6, 8, and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites two instances of “a time point” which lack proper distinction between the recitations as the terms refer to two different points in time and therefore should be identified separately as “a first time point” and “a second time point” respectively. Subsequent dependent claims do not resolve this issue.
Claim 10 recites “values of the first chip power control signal and the second chip power control signal are same as each other” which is unclear in view of claim 6, from which claim 10 depends, wherein the first and second SRAM chips are designated to different power modes and therefore it is unclear how the same value is transmitted to each respective chip to indicate different power modes. For purposes of the current action, the limitation is interpreted as the first and second chip power control signals as being capable of transmitting the same values.
Claim Rejections - 35 USC § 103
Claims 1-2 and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cermak et al (US 11,520,499) in view of Ware et al. (US 2017/0337965).
Regarding claim 1, Cermak discloses, in the italicized portions, a -static random access memory (SRAM) device communicating with an external device, the SRAM device comprising: a SRAM block comprising a first SRAM chip and a second SRAM chip ([Col. 8 ln. 41-43] The power output 308 can provide power to one or more RAM banks (e.g., one or more RAM banks within the system SRAM 170). [Col. 15 ln. 49-54] In an example, an SRAM may be in the retention mode, and the power for the SRAM is adjusted to the active mode. In another example, the SRAM may be in the retention mode, and a memory bank within the SRAM is adjusted to the active mode while other memory banks within the SRAM are maintained in the retention mode.); an access address decoder configured: to generate, by decoding memory access requests provided from the external device, a first chip selection signal and a second chip selection signal respectively corresponding to the first SRAM chip and the second SRAM chip; a memory power mode controller configured to: determine a first idle time elapsed from a time point where the first chip selection signal has lastly indicated that the external device has accessed to the first SRAM chip, determine a second idle time elapsed from a time point where the second chip selection signal has lastly indicated that the external device has accessed to the second SRAM chip, ([Col. 14 ln. 8-18] At step 506, a power state of the memory device at step 504 is adjusted. The arbiter 414 can trigger the power controller 408 to selectively change the first memory bank 411a of the first memory device 410-1 from a first power mode to a second power mode. Although the first memory device 410-1 is arranged in memory banks, in some implementations, there is only one memory bank, and selectively changing the first memory bank 411a from the first power mode to the second power mode is merely changing the first memory 410-1 from the first power mode to the second power mode.) control a first power mode of the first SRAM chip to be a low power mode, based on determining that the first idle time is greater than a first threshold value and control a second power mode of the second SRAM chip to be a normal mode, based on determining the second idle time is smaller than a second threshold value; ([Col. 11 ln. 11-24] The transition from standby mode to retention mode can occur due to inactivity. For example, the counter can reset when there are multiple memory operations being performed, spaced apart in time, as long as the spacing between the memory operations does not exceed the time buffer allotted by the counter. That is, the counter can reset each time a memory operation is being performed, and the counter can count up (or count down, depending on implementation) each time there is an inactivity. When the counter counts for a duration that is equal to or exceeds the time buffer, then the counter can generate the sleep signal for transitioning from standby mode to retention mode.) and a memory chip power controller configuration register configured to store setting information for controlling the first power and the second power mode, wherein the memory power mode controller is configured to determine the low power mode from among a power down mode and a retention mode ([Col. 15 ln. 31-40] At step 506, adjusting the power mode can include changing from the standby mode to the active mode, the retention mode to the active mode, the off mode to the active mode, etc. In some implementations, when the memory operation included in the memory transaction request is completed, adjusting the power mode can include changing from the active mode to the standby mode, the active mode to the retention mode, the standby mode to the retention mode, the standby mode to the off mode, the active mode to the off mode, etc.), based on the setting information. Herein Cermak discloses controlling power modes of a SRAM memory device including an active mode and plurality of low power modes wherein specific memory banks of the SRAM memory device may be controlled to different power modes simultaneously based on the utilized counters which represent the time elapsed since the previously executed memory operation to the respective memory bank. Cermak does not explicitly address that an address decoder generates selection signals to respective SRAM chips and that a configuration register is present in the power controller storing setting information to control the selection of the power mode for the SRAM chips. Regarding these aspects of the limitation, Ware discloses in Paragraphs [0076-77] “[0076] A command decoder (not shown) in CAB 415 decodes commands that arrive via port DCA[14:0] from controller component 505. Such commands are well known, so a detailed treatment is omitted. A chip-select decoder 610 is included to decode chip-select signals that accompany module commands. Normally used only to select DRAM devices for access, decoder 610 also decodes chip-select signals in this embodiment to generate device clock-enable signals. This approach supports granular clock-enable functionality that allows module 400 to leave memory devices that are not the target of an access command (e.g., a read or write command) in a low-power state. [0077] FIG. 6B depicts chip-select decoder 610 of FIG. 6A in accordance with one embodiment. A configuration register 615 stores a value indicative of the module's configuration, informing decoder 610 which data ports are active on the module in the specific configuration.” Herein Ware discloses controlling access to a memory module comprising a plurality of DRAM components, found analogous to the memory block and memory chips. The memory module includes components for decoding a command received from an external device to determine which portion of the memory module is targeted for access and, upon making the determination, is able to control which portions are memory are maintained in an access mode, or normal mode, of power consumption and for which portions to switch to and keep in a low-power mode. Specifically, Ware notes this level of activation granularity improves reducing power consumption of the memory device. While Ware discusses techniques applied in the context of DRAM chips, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the techniques may be applied to SRAM chips in the similar fashion as Ware indicates in Paragraph [0079] that “DRAM devices 600 are DDR4 SDRAM in the embodiment of FIGS. 6A and 6B, though different types of memory devices can be used.” In this manner, the techniques supplied therein are not limited to DRAM application. Cermak and Ware are analogous art because they are from the same field of endeavor of managing power consumption of memory devices.
Regarding claim 2, Cermak and Ware in combination further disclose the SRAM device of claim 1, wherein the memory power mode controller comprises a counter, which is configured to manage a first count and a second count respectively corresponding to the first idle time and the second idle time, wherein the first count is increased as time elapses and is initialized in response to the first chip selection signal being transitioned to a first level, and wherein the second count is increased as time elapses and is initialized in response to the second chip selection signal being transitioned to the first level (Cermak [Col. 11 ln. 11-24] and Ware [0076]). Herein Cermak discloses resetting the counter in regards to executing memory operations at the specified memory bank. As discussed in the rejection of claim 1, Ware discloses that signaling to each chip results in controlling the power mode of each respective chip independently.
Regarding claim 11, Cermak discloses, in the italicized portions, a static random access memory (SRAM) device comprising: a first SRAM block comprising a first plurality of SRAM chips ([Col. 8 ln. 41-43]); a memory power mode controller configured to individually control a power mode of each of the first plurality of SRAM chips ([Col. 14 ln. 8-18]); a voltage controller configured to: generate a first cell voltage control signal based on a first memory state signal which is provided from the memory power mode controller and indicates a power state of the first SRAM block, and control a first cell voltage for the first SRAM block by transmitting the first cell voltage control signal to the first SRAM block ([Col 2 ln. 49-58] In an implementation, the power controller is configured to selectively change the first memory bank from the first power mode to the second power mode by changing power supplied to the first memory bank from a first voltage level to a second voltage level. The second voltage level is greater than the first voltage level. In an implementation, the power controller is further configured to change the power supplied to the first memory bank from the second voltage level to the first voltage level after the fabric performs the memory operation.); and a memory chip power controller configuration register configured to store setting information, wherein the memory power mode controller is configured to determine the power mode of each of the first plurality of SRAM chips from among a low power mode and a normal mode, based on an idle time maintained after corresponding SRAM chip has been lastly accessed, and wherein the memory power mode controller is further configured to determine the low power mode from among a power down mode and a retention mode ([Col. 15 ln. 31-40]) based on the setting information. Herein Cermak discloses controlling power modes and generating voltage levels of a SRAM memory device including an active mode and plurality of low power modes wherein specific memory banks of the SRAM memory device may be controlled to different power modes simultaneously based on the utilized counters which represent the time elapsed since the previously executed memory operation to the respective memory bank. Cermak does not explicitly address respective SRAM chips and that a configuration register is present in the power controller storing setting information to control the selection of the power mode for the SRAM chips. Regarding these aspects of the limitation, Ware discloses in Paragraphs [0076-77] controlling access to a memory module comprising a plurality of DRAM components, found analogous to the memory block and memory chips. The memory module includes components for decoding a command received from an external device to determine which portion of the memory module is targeted for access and, upon making the determination, is able to control which portions are memory are maintained in an access mode, or normal mode, of power consumption and for which portions to switch to and keep in a low-power mode. Ware explicitly notes in Paragraph [0079] that different types of memory devices may be used and claim 11 is rejected on a similar basis as claim 1.
Regarding claim 12, Cermak and Ware in combination further disclose the SRAM device of claim 11, wherein the voltage controller is configured to generate the first cell voltage control signal indicating decrease of the first cell voltage, when the first memory state signal indicates that all SRAM chips included in the first SRAM block are set to the retention mode (Cermak [Col. 10 ln. 59-64] The counter can provide a sleep signal to the power controller 408 for deactivating the specific path based on the time to complete the memory operation. The sleep signal can include an identifier for the entire memory to be deactivated, an identifier for the memory bank to be deactivated, or both.). Cermak discloses capability of transmitting signals to indicate the entire SRAM bank to be controlled and in view of Ware wherein the individual chip select signals indicate whether a chip is activated, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that all associated chips would be set to the same lower power mode due to inactivity. The Examiner notes Cermak discloses a plurality of lower power states including standby, retention, and powered-off. The Examiner additionally notes the limitation as phrased by “when” indicates a contingent limitation which by examining procedure is therefore not required in the broadest reasonable interpretation of the claim and only the structure capable of performing the step is.
Regarding claim 13, Cermak and Ware in combination further disclose the SRAM device of claim 11, wherein the voltage controller is further configured to generate the first cell voltage control signal indicating to stop applying the first cell voltage to the first SRAM block, when the first memory state signal indicates that all SRAM chips included in the first SRAM block are set to the power down mode (Cermak [Col. 10 ln. 59-64]). Claim 13 is rejected on a similar basis as claim 12 as both Cermak and Ware disclose controlling power supply to respective portions of memory based on activity. The Examiner additionally notes the limitation as phrased by “when” indicates a contingent limitation which by examining procedure is therefore not required in the broadest reasonable interpretation of the claim and only the structure capable of performing the step is.
Regarding claim 14, Ware, Yin, Gupta, and Choi in combination further disclose the SRAM device of claim 11, further comprising a second SRAM block including a second plurality of SRAM chips, wherein the memory power mode controller is further configured to individually control a power mode of each of the second plurality of SRAM chips, and wherein the voltage controller is further configured to: generate a second cell voltage control signal based on a second memory state signal which is provided from the memory power mode controller and indicating a power state of the second SRAM block, and control a second cell voltage for the second SRAM block by transmitting the second cell voltage control signal to the second SRAM block (Cermak [Col 2 ln. 49-58]). As Cermak and Ware address a plurality of portions of memory, the techniques as cited and discussed for claim 11 by extension are applicable to these limitations involving the second SRAM block to one of ordinary skill in the art as a duplicative step achieving the same result.
Regarding claim 15, Cermak and Ware in combination further disclose the SRAM device of claim 14, wherein the voltage controller is configured to generate the second cell voltage control signal indicating decrease of the second cell voltage, when the second memory state signal indicates that all SRAM chips included in the second SRAM block are set to the retention mode (Cermak [Col. 10 ln. 59-64]). Claim 15 is rejected on a similar basis as claims 12 and 13 regarding the change in cell voltage according to the power mode. The Examiner additionally notes the limitation as phrased by “when” indicates a contingent limitation which by examining procedure is therefore not required in the broadest reasonable interpretation of the claim and only the structure capable of performing the step is.
Regarding claim 16, Cermak and Ware in combination further disclose the SRAM device of claim 14, wherein the voltage controller is further configured to generate the second cell voltage control signal indicating to stop applying the second cell voltage to the second SRAM block, when the second memory state signal indicates that all SRAM chips included in the second SRAM block are set to the power down mode (Cermak [Col. 10 ln. 59-64]). Claim 16 is rejected on a similar basis as claims 12 and 13 regarding the change in cell voltage according to the power mode. The Examiner additionally notes the limitation as phrased by “when” indicates a contingent limitation which by examining procedure is therefore not required in the broadest reasonable interpretation of the claim and only the structure capable of performing the step is.
Claims 4, 6, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cermak in view of Ware and further in view of Yin (2017/0206031).
Regarding claim 4, Cermak and Ware do not explicitly disclose the SRAM device of claim 1, wherein the memory power mode controller comprises: a first memory chip power mode controller configured to control the first power mode based on the first idle time; and a second memory chip power mode controller configured to control the second power mode based on the second idle time. Regarding this limitation, Yin discloses in Paragraph [0040] “In the illustrated embodiment, the apparatus 200 may include a plurality of memory bank power down controllers (PDCs) 220. Each PDC 220 may be configured to control the operating mode of a respective memory bank 216. More specifically, each PDC 220 may be configured to either place the respective memory bank 216 in a power down mode (e.g., deep power down mode) or to wake-up the respective memory bank 216 from a power down mode (e.g., place it back into a normal or high power consumption operational mode).” Herein Yin discloses that each respective portion of memory may have a respective controller for implementing the signals to set to portion to a particular power mode. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include multiple power mode controllers associated with corresponding portions of memory to achieve the expected result of distributed management in the system. Cermak, Ware, and Yin are analogous art because they are from the same field of endeavor of managing power consumption of memory devices.
Regarding claim 6, Cermak, Ware and Yin in combination further disclose the SRAM device of claim 4, wherein the memory power mode controller is further configured to: control the first power mode to be the low power mode by transmitting a first chip power control signal to the first SRAM chip, and control the second power mode to be the normal power mode by transmitting a second chip power control signal to the second SRAM chip (Ware [0076] and Yin [0040] and [0043]). Herein the plurality of power down controllers as disclosed by Yin may transmit signals to alter the power mode of the respective portion of memory.
Regarding claim 8, Cermak, Ware, and Yin in combination further disclose the SRAM device of claim 6, wherein the first SRAM chip is transitioned to the retention mode or the power down mode, depending on a first retention control signal generated based on the setting information (Cermak [Col. 15 ln. 31-40] and Ware [0074] and Yin [0040] and [0043]). Herein both Ware and Yin disclose power down modes for the respective portion of memory which may be switched to based on control signals. Cermak, as cited previously, also refers to the plurality of power modes.
Regarding claim 10, Cermak, Ware and Yin in combination further disclose the SRAM device of claim 6, wherein values of the first chip power control signal and the second chip power control signal are same as each other (Cermak [Col. 15 ln. 31-40] and Ware [0074] and Yin [0040] and [0043]). Herein Cermak, Ware, and Yin disclose power down modes for the respective portion of memory which may be switched to based on control signals. Each mode is represented by a different value and therefore switching to the same mode may result in the same value being transmitted whereas different modes result in different values.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kishibe (US 2011/0141838) – Paragraphs [0057-58] wherein managing power modes according to chip select signals is discussed.
Kwak et al. (US 2022/0043587) – Paragraph [0057] wherein managing power modes according to chip select signals is discussed.
Wagner et al. (US 2022/0236905) – Paragraph [0056] wherein managing SRAM chip timing parameters is discussed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER J YOON whose telephone number is (408)918-7629. The examiner can normally be reached on Monday-Friday 8am-3pm ET. The examiner’s email is alexander.yoon2@uspto.gov.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135