DETAILED ACTION
Claims 1-20 are pending.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/25/2025 has been entered.
The office acknowledges the following papers:
Claims and remarks filed on 7/25/2025.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Karm et al. (U.S. 2021/0349823), in view of Official Notice.
As per claim 1:
Karm disclosed an apparatus, comprising:
a processor core (Karm: Figure 1 element 12, paragraph 27) including circuitry configured to:
fetch a first instruction configured to cause a first memory request followed by a second instruction configured to cause a second memory request (Karm: Figure 1 elements 14-18 and 30-32, paragraphs 28-29 and 36-37)(The fetch address generation unit generates fetches to the instruction cache for instructions, including load and store instructions.);
while the second instruction is still in a pipeline of the processor core, determine that the first memory request is a candidate for combination with the second memory request (Karm: Figures 2-4 elements 50, 70, and 82, paragraphs 38-40, 49-50, 55, 58, and 61-62)(A comparison match between a committed store and a previously committed store in the write combine buffer determines that these stores are a candidate for data merging in the buffer. The processor core is pipelined. The flowchart of figure 4 is “pipelined over multiple clock cycles” (see paragraph 61).); and
responsive to the determination, send an indication, from the processor core via a bus, that the first memory request is a candidate for combination (Karm: Figures 1-2 elements 12, 50-52, paragraphs 38 and 49-50)(A comparison match between a committed store and a previously committed store in the write combine buffer determines that these stores are a candidate for data merging in the buffer. The control circuit controls allocation of entries. Karm doesn’t explicitly state that the control circuit performs the comparison. It would have been obvious to one of ordinary skill in the art that the control circuit performs the comparison and outputs control signals (i.e. indication) to indicate which entry merged data is supposed to modified. It would have been obvious to one of ordinary skill in the art that the connection between the control and memory is implemented as a bus to provide a method of transferring control signals. In addition, according to “In re Japikse” (181 F.2d 1019, 86 USPQ 70 (CCPA 1950)), shifting the location of parts doesn’t give patentability over prior art. Lastly, official notice is given that buses can be implemented to transfer data between logic elements for the advantage of such data transfers. Thus, it would have been obvious to one of ordinary skill in the art that the connection between the control and memory within the write combining buffer is a bus.); and
a transaction bundler (Karm: Figure 2 element 52, paragraph 49) configured to:
receive the first memory request, the second memory request, and the indication from the processor core (Karm: Figure 2 elements 42 and 50-52, paragraphs 38 and 49-50)(The memory buffer of the write combining buffer receives store instruction write addresses and data to be written to memory. In view of the above obviousness and official notice, the memory buffer receives control signals (i.e. indication) from the control unit to indicate a merge is to be performed between two store operations.);
determine whether the second memory request is received by the transaction bundler within a specified time period (Karm: Figures 2-4 elements 50-54, 70, and 82, paragraphs 38-40, 49-51, 58, and 62)(A comparison match between a committed store and a previously committed store in the write combine buffer determines that these stores are a candidate for data merging in the buffer. The control circuit includes a watermark number of entries within the memory that can be allocated that is fewer than the total number of memory entries. When the watermark number of entries is exceeded, the oldest entry from the memory is drained to the data cache. When the memory contains an allocated entry for a previously committed store that can be merged within the committed store, then it’s determined that the committed store has been received within a time period that is less than the time of draining the entry containing the previously committed store.).
As per claim 2:
Karm disclosed the apparatus of claim 1, wherein, to determine whether the second memory request is received by the transaction bundler within a specified time period, the transaction bundler is configured to determine that the second memory request is received within the specified time (Karm: Figures 2-4 elements 50-54, 70, and 82, paragraphs 38-40, 49-51, 58, and 62)(A comparison match between a committed store and a previously committed store in the write combine buffer determines that these stores are a candidate for data merging in the buffer. The control circuit includes a watermark number of entries within the memory that can be allocated that is fewer than the total number of memory entries. When the watermark number of entries is exceeded, the oldest entry from the memory is drained to the data cache. When the memory contains an allocated entry for a previously committed store that can be merged within the committed store, then it’s determined that the committed store has been received within a time period that is less than the time of draining the entry containing the previously committed store.), and the transaction bundler if further configured to:
based on the indication and the determination that the second memory request is received within the specified time, combine the first memory request and the second memory request into a combined memory request (Karm: Figures 1-2 elements 12, 50-52, paragraphs 38 and 49-50)(A comparison match between a committed store and a previously committed store in the write combine buffer results in merging the store data of the committed store into the entry of the previously committed store. When the memory contains an allocated entry for a previously committed store that can be merged within the committed store, then it’s determined that the committed store has been received within a time period that is less than the time of draining the entry containing the previously committed store.); and
transmit the combined memory request (Karm: Figures 1-2 elements 16 and 36, paragraphs 39)(Merged write combining buffer entries are output to the data cache.).
As per claim 3:
Karm disclosed the apparatus of claim 1, wherein, to determine whether the second memory request is received by the transaction bundler within a specified time, the transaction bundler is configured to determine that the second memory request is not received within the specified time (Karm: Figures 2-4 elements 50-54, 70, and 82, paragraphs 38-40, 49-51, 58, and 62)(A comparison match between a committed store and a previously committed store in the write combine buffer determines that these stores are a candidate for data merging in the buffer. The control circuit includes a watermark number of entries within the memory that can be allocated that is fewer than the total number of memory entries. When the watermark number of entries is exceeded, the oldest entry from the memory is drained to the data cache. When the memory contains an allocated entry for a previously committed store that cannot be merged within the committed store, then it’s determined that the committed store hasn’t been received within a time period that is less than the time of draining the entry containing the previously committed store.), and the transaction bundler is further configured to:
wait to receive the second memory request for a specified time period (Karm: Figures 2 and 4 elements 50-52 and 90-94, paragraphs 39-40, 51-54, and 63)(The write combining buffer retains a watermark number of entries for potential merging. A minimum period of time that is takes to reach a watermark number of for consecutive committed stores is reached prior to draining entries from the write combining buffer.); and
transmit the first memory request without combination with the second memory request based on determination that the second memory request is not received within the specified time (Karm: Figures 1-2 and 4 elements 16, 36, 52, 80, 88, and 94, paragraphs 38-39, 51, 54, and 63)(When a committed store is received that doesn’t match addresses of previously committed stores within the write combining buffer, an entry is allocated. The non-merged store entries are drained from the write combining buffer to the data cache upon a count value exceeding a threshold. Draining an entry without merging determined that a second memory request that was mergeable with the entry was not received in time.).
As per claim 4:
Karm disclosed the apparatus of claim 1, wherein the transaction bundler (Karm: Figure 2 element 52, paragraph 49) is further configured to:
receive the second memory request (Karm: Figure 2 elements 42 and 50-52, paragraphs 38 and 49-50)(The memory buffer of the write combining buffer receives store instruction write addresses and data to be written to memory.); and
transmit the first memory request followed by the second memory request based on determining that the first memory request and the second memory request are not combinable (Karm: Figures 1-2 and 4 elements 16, 36, 52, 80, 88, and 94, paragraphs 38-39, 51, 54, and 63)(When a committed store is received that doesn’t match addresses of previously committed stores within the write combining buffer, an entry is allocated. The non-merged store entries are drained from the write combining buffer to the data cache upon a count value exceeding a threshold.).
As per claim 5:
Karm disclosed the apparatus of claim 1, wherein the circuitry is configured to send the indication while the second instruction is still in the pipeline (Karm: Figures 2 and 4 elements 42, 50-52, 82-84, paragraphs 38, 49-50, 55, 58, and 61-62)(In view of the above obviousness and official notice, the memory buffer receives control signals (i.e. indication) from the control unit to indicate a merge is to be performed between two store operations. This occurs within the processor, which is pipelined. Additionally, the flowchart actions of figure 4 are also pipelined within the processor core.).
As per claim 6:
Karm disclosed the apparatus of claim 1, wherein the circuitry is configured to compare at least part of a first virtual address associated with the first instruction with at least part of a second virtual address associated with the second instruction for sending the indication (Karm: Figures 2-4 elements 50, 70, and 82, paragraphs 38-40, 49-50, 58, and 62)(A comparison address match between a committed store and a previously committed store in the write combine buffer determines that these stores are a candidate for data merging in the buffer. It would have been obvious to one of ordinary skill in the art that, as Karm makes no mention of address translation, the address comparisons are between virtual addresses and not physical addresses. Additionally, official notice is given that store queues and write combining buffers can store virtual addresses for the advantage of avoiding costly address translations early than necessary. Thus, it would have been obvious to one of ordinary skill in the art to implement comparing stored virtual addresses in Karm.).
As per claim 7:
Karm disclosed the apparatus of claim 1, wherein the circuitry includes a load/store execution unit (Karm: Figure 1 element 42, paragraph 34), and wherein the circuitry is configured to send the indication when the second instruction enters the load/store execution unit (Karm: Figures 1-2 elements 12, 50-52, paragraphs 38 and 49-50)(A comparison match between a committed store and a previously committed store in the write combine buffer determines that these stores are a candidate for data merging in the buffer. The control circuit controls allocation of entries. Karm doesn’t explicitly state that the control circuit performs the comparison. It would have been obvious to one of ordinary skill in the art that the load/store execution unit can also perform the comparison and outputs control signals (i.e. indication) to indicate which entry merged data is supposed to modify. In addition, according to “In re Japikse” (181 F.2d 1019, 86 USPQ 70 (CCPA 1950)), shifting the location of parts doesn’t give patentability over prior art.).
As per claim 9:
Karm disclosed the apparatus of claim 1, wherein the circuitry is configured to:
determine when a page that is addressed by the second instruction is a same page as a page that is addressed by the first instruction (Karm: Figures 2-4 elements 50, 70, and 82, paragraphs 38-40, 49-50, 58, and 62)(A comparison match between a committed store and a previously committed store in the write combine buffer determines that these stores are a candidate for data merging in the buffer when the writes are to the same cache line. Memory pages contain multiple cache lines. Thus, detecting multiple writes to the same cache line also detects multiple writes to the same memory page.); and
send the indication based on the determination (Karm: Figure 2 elements 42 and 50-52, paragraphs 38 and 49-50)(In view of the above obviousness and official notice, the memory buffer receives control signals (i.e. indication) from the control unit to indicate a merge is to be performed between two store operations.).
As per claim 10:
Claim 10 essentially recites the same limitations of claim 1. Therefore, claim 10 is rejected for the same reasons as claim 1.
As per claim 11:
The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 2. Therefore, claim 11 is rejected for the same reason(s) as claim 2.
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 3. Therefore, claim 12 is rejected for the same reason(s) as claim 3.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 4. Therefore, claim 13 is rejected for the same reason(s) as claim 4.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 5. Therefore, claim 14 is rejected for the same reason(s) as claim 5.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 6. Therefore, claim 15 is rejected for the same reason(s) as claim 6.
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 7. Therefore, claim 16 is rejected for the same reason(s) as claim 7.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 9. Therefore, claim 18 is rejected for the same reason(s) as claim 9.
As per claim 19:
Claim 19 essentially recites the same limitations of claim 1. Claim 19 additionally recites the following limitations:
executing a first and second instruction (Karm: Figure 1 element 42, paragraph 34).
As per claim 20:
Claim 20 essentially recites the same limitations of claim 2. Claim 20 additionally recites the following limitations:
receive the second memory request from the processor core (Karm: Figure 2 elements 42 and 50-52, paragraphs 38 and 49-50)(The memory buffer of the write combining buffer receives store instruction write addresses and data to be written to memory.).
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Karm et al. (U.S. 2021/0349823), in view of Lloyd et al. (U.S. 11,243,773), in view of Official Notice.
As per claim 8:
Karm disclosed the apparatus of claim 1.
Karm failed to teach wherein the circuitry is configured to: determine when a second address associated with the second instruction is adjacent to a first address associated with the first instruction; and send the indication based on the determination.
However, Lloyd combined with Karm disclosed wherein the circuitry is configured to:
determine when a second address associated with the second instruction is adjacent to a first address associated with the first instruction (Lloyd: Figure 7 elements 702-706, column 10 lines 44-65)(Karm: Figures 2-4 elements 50, 70, and 82, paragraphs 38-40, 49-50, 58, and 62)(Lloyd disclosed detecting store instructions with adjacent addresses. The combination allows for writing a merged entry in the memory buffer upon detecting store instructions with adjacent addresses.); and
send the indication based on the determination (Karm: Figure 2 elements 42 and 50-52, paragraphs 38 and 49-50)(In view of the above obviousness and official notice, the memory buffer receives control signals (i.e. indication) from the control unit to indicate a merge is to be performed between two store operations.).
The advantage of implementing checks for adjacent memory writes is that adjacent writes across cache boundary lines can be implemented for merged write operations for the advantage of increased memory throughput. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement merging adjacent writes in Karm for the above advantage.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 8. Therefore, claim 17 is rejected for the same reason(s) as claim 8.
Response to Arguments
The arguments presented by Applicant in the response, received on 7/25/2025 are not considered persuasive.
Applicant argues regarding claim 1:
“Applicant submits that Karm fails to teach the amended limitation because its determination of whether to merge memory operations occurs at a fundamentally different and later time than what is claimed. The amended claim requires the determination of combination candidacy to be made "while the second instruction is in a pipeline of the processor core", specifying a proactive determination that occurs during the active processing of an instruction. In contrast, the Write Combining (WC) Buffer (36) in Karm operates on "committed store ops" that it receives from the Load/Store Unit. Karm explicitly defines that a store operation may be considered committed "when the store is retired by the processor 12". Retirement is the final stage that occurs only after an instruction has successfully passed through the execution pipeline and its results are made permanent. Therefore, the determination of whether a store is "mergeable" in Karm happens in the WC Buffer after the instruction has already exited the execution pipeline. This reactive process is in direct contrast to the claimed invention, where the determination is made proactively while the instruction is still being processed within the pipeline. Consequently, Karm does not teach or suggest determining combination candidacy while the instruction is in a pipeline of the processor core.”
This argument is not found to be persuasive for the following reason. Karm disclosed a write combining buffer that includes a memory for combining writes to the data cache. The applicant is correct that the merging function occurs outside of the LSU and its corresponding execution pipeline stages. However, the claimed limitation of “a pipeline of the processor core” is not the same as execution pipeline stages. Karm disclosed that the flowchart of figure 4 is performed within the pipelined processor core over multiple clock cycles. Thus, Karm reads upon the newly claimed limitation.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183