DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Request for Continued Examination (RCE) on 08/28/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 7-9, 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over DeJonge et al. (US 2022/0085610), hereinafter DeJonge, in view of Chang (CN 104993811; rejection based on English translation).
Regarding claim 1, DeJonge discloses (see figures 1-12) an overcurrent protection circuit for fast switching semiconductors (figure 4C, part 460), comprising: a semiconductor switch unit (figure 4C, part 464) comprising a set of semiconductor switches connected in anti-series with respect to each other (figure 4C, part Q475a/Q475b) (paragraph [0111]; The controllable switching circuit 464 may comprise a pair of field-effect transistors (FETs) Q475a and Q475b (e.g., arranged in an anti-series configuration)); a resistor element (figure 4C, part 470) for generating a voltage signal (figure 4C, part Vsns) depending on a current through the semiconductor switch unit (figure 4C, part current Imon through 464); an amplification unit (figure 4C, part 480) configured for amplifying the voltage signal (figure 4C, part Vsns) (paragraph [0113]; The current monitoring circuit 462 may be configured to monitor (e.g., measure) the magnitude of the monitored current IMON conducted through the current monitoring circuit 462 and the controllable switching circuit 464. The amplifier 480 of the current monitoring circuit 462 may be configured to receive a sense voltage VSNS developed across the resistor 470. The amplifier 480 may output a current monitoring signal VI-MON corresponding to the magnitude of the sense voltage VSNS); a comparator unit (figure 4C, part 482) configured to compare the amplified voltage signal (figure 4C, part VI-MON) with a threshold value (figure 4C, part VI-TH1), and to generate a disable signal (figure 4C, part VI-DISBL) when an amount of the amplified voltage signal (figure 4C, part VI-MON) is greater than an amount of the threshold value (figure 4C, part VI-TH1) (paragraphs [0114]-[0118]; The timer 484 may be configured to start and run for a first time period when the output of the comparator 482 is driven high (e.g., when the magnitude of the current monitoring signal VI-MON is higher than the first voltage threshold VI-TH1, signifying that the magnitude of the monitored current IMON is above the first current threshold I.sub.TH1)… When both of the outputs of the comparator 482 and the timer 484 are driven high (e.g., signifying the magnitude of the monitored current IMON has remained above the first current threshold ITH1 for the first period of time), the logic AND gate 486 may drive its output high to control the disable signal VI-DSBL); and a device (figure 4C, part device generated by 468 and 495) configured for switching off the semiconductor switch unit (figure 4C, part off 464; through Vlatch) when the device (figure 4C, part device generated by 468 and 495) receives the disable signal (figure 4C, part VI-DSBL) (paragraphs [0126]- [128]; The latching circuit 468 may be configured to receive the disable signal VI-DSBL, which may be coupled to a negative input of the comparator 494… When the disable signal VI-DSBL is driven high (e.g., if the magnitude of the monitored current IMON has exceeded a current threshold for the respective time period), the comparator 494 may drive its output low and thus the latch signal VLATCH low… The drive circuit 472 may receive the latch signal VLATCH from the latching circuit 468 through a diode 495 and may control the drive signal VDR in accordance with the latch signal VLATCH. For example, if the latch signal VLATCH is high, the drive circuit 472 may control the drive signal VDR to render the controllable switching circuit 464 conductive. When the latch signal VLATCH is driven low, the input 473 of the drive circuit 472 may be pulled low through the diode 495 (e.g., below the turn-on voltage of the drive circuit) to cause the drive circuit 472 to control the drive signal VDR to render the controllable switching circuit 464 non-conductive).
DeJonge does not expressly disclose a switching device.
Chang teaches (see figures 1-9) a switching device (figure 4, part switching device connected and controllable with the output ocp2 from NE555) configured for switching off the semiconductor switch unit (figure 4, part off the semiconductor switch unit connected to 1mohm) when the switching device receives the disable signal (figure 4, part switching device connected and controllable with the output ocp2 from NE555; through ocp2) (paragraph [0037]; Referring to FIG. 4 , a first embodiment of the present invention is an overcurrent protection circuit for a semiconductor switch. The semiconductor switch is a semiconductor power transistor such as an IGBT or MOSFET. The semiconductor switch includes a power terminal connected to a DC power supply, a ground terminal, and a control terminal connected to a control signal. A load is also connected between the power supply and the ground. The overcurrent protection circuit includes a current sampling circuit, an overcurrent protection comparator circuit, a NE555 monostable circuit, a transistor, a drive control circuit and a drive resistor R1 connected in series. The output of the drive control circuit is used to control the on and off of the semiconductor power tube after passing through the drive resistor R1… The output of the current sampling circuit is connected to the overcurrent protection comparator circuit, wherein the overcurrent protection comparator circuit includes a comparator and an inverter. The comparator outputs an ocp1 signal, which is connected to a NE555 monostable circuit via the inverter. The NE555 monostable circuit outputs an ocp2 signal, which is output through a transistor to form an OC gate and connected to the drive control circuit).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the device of DeJonge with the switching device features as taught by Chang and obtain an overcurrent protection circuit for fast switching semiconductors, comprising: a semiconductor switch unit comprising a set of semiconductor switches connected in anti-series with respect to each other; a resistor element for generating a voltage signal depending on a current through the semiconductor switch unit; an amplification unit configured for amplifying the voltage signal; a comparator unit configured to compare the amplified voltage signal with a threshold value, and to generate a disable signal when an amount of the amplified voltage signal is greater than an amount of the threshold value; and a switching device configured for switching off the semiconductor switch unit when the switching device receives the disable signal, because it provides more efficient overcurrent protection circuit with more simple and cost effective controller (paragraph [0007]).
Regarding claim 3, DeJonge and Chang teach everything claimed as applied above (see claim 1). Further, DeJonge discloses (see figures 1-12) a blank filter unit (figure 4C, part blank filter unit generated by 484 and 486) connected between the comparator unit (figure 4C, part 482) and the device (figure 4C, part device generated by 468 and 495), for blocking (figure 4C, part blank filter unit generated by 484 and 486) the disable signal (figure 4C, part VI-DISBL) for a predefined blank time (figure 4C, part blank filter unit generated by 484 and 486; predefined blank time generated by 484) before supplying it to the device (figure 4C, part device generated by 468 and 495) (paragraphs [0117]-[0118]; The timer 484 may be configured to start and run for a first time period when the output of the comparator 482 is driven high (e.g., when the magnitude of the current monitoring signal VI-MON is higher than the first voltage threshold VI-TH1, signifying that the magnitude of the monitored current IMON is above the first current threshold ITH1). The timer 484 may continue running as long as the output of the comparator 482 is driven high (e.g., for as long as the magnitude of the monitored current IMON is above the first current threshold ITH1). While the magnitude of the monitored current IMON remains above the first current threshold ITH1, the timer 484 may be configured to drive its output low until the timer 484 reaches the expiration of the first time period… If the timer 484 reaches the expiration of the first time period while the magnitude of the monitored current IMON has remained above the first current threshold I.sub.TH1, the timer 484 may be configured to drive its output high. The logic AND gate 486 may receive the outputs of the comparator 482 and the timer 484… When both of the outputs of the comparator 482 and the timer 484 are driven high (e.g., signifying the magnitude of the monitored current IMON has remained above the first current threshold ITH1 for the first period of time), the logic AND gate 486 may drive its output high to control the disable signal VI-DSBL). However, DeJonge does not expressly disclose the switching device.
Chang teaches (see figures 1-9) a blank filter unit (figure 4, part blank filter unit generated by NE555) connected to the switching device (figure 4, part switching device connected and controllable with the output ocp2 from NE555), for blocking the disable signal for a predefined blank time (figure 4, part blank filter unit generated by NE555) before supplying it to the switching device (figure 4, part switching device connected and controllable with the output ocp2 from NE555) (paragraphs [0025] and [0026]; the NE555 monostable circuit includes a 555 time base circuit and an RC timing circuit. From the above description, it can be seen that the time keeping function of the output signal of the overcurrent protection circuit is realized by using the NE555 time base circuit and the RC timing circuit).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the device of DeJonge with the switching device features as taught by Chang and obtain a blank filter unit connected between the comparator unit and the switching device, for blocking the disable signal for a predefined blank time before supplying it to the switching device, because it provides more efficient overcurrent protection circuit with more simple and cost effective controller (paragraph [0007]).
Regarding claim 5, DeJonge and Chang teach everything claimed as applied above (see claim 1). Further, DeJonge discloses (see figures 1-12) the set of semiconductor switches (figure 4C, part Q475a/Q475b) include two semiconductor switches connected in anti-series to each other (figure 4C, part Q475a/Q475b) (paragraph [0111]; The controllable switching circuit 464 may comprise a pair of field-effect transistors (FETs) Q475a and Q475b (e.g., arranged in an anti-series configuration)).
Regarding claim 7, DeJonge and Chang teach everything claimed as applied above (see claim 1). Further, DeJonge discloses (see figures 1-12) a driver integrated circuit (figure 4C, part 472) controlled by the device (figure 4C, part device generated by 468 and 495), to switch off the semiconductor switch unit (figure 4C, part off 464; through Vlatch) when the device (figure 4C, part device generated by 468 and 495) receives the disable signal (figure 4C, part VI-DSBL) (paragraphs [0126]- [128]; The latching circuit 468 may be configured to receive the disable signal VI-DSBL, which may be coupled to a negative input of the comparator 494… When the disable signal VI-DSBL is driven high (e.g., if the magnitude of the monitored current IMON has exceeded a current threshold for the respective time period), the comparator 494 may drive its output low and thus the latch signal VLATCH low… The drive circuit 472 may receive the latch signal VLATCH from the latching circuit 468 through a diode 495 and may control the drive signal VDR in accordance with the latch signal VLATCH. For example, if the latch signal VLATCH is high, the drive circuit 472 may control the drive signal VDR to render the controllable switching circuit 464 conductive. When the latch signal VLATCH is driven low, the input 473 of the drive circuit 472 may be pulled low through the diode 495 (e.g., below the turn-on voltage of the drive circuit) to cause the drive circuit 472 to control the drive signal VDR to render the controllable switching circuit 464 non-conductive). However, DeJonge does not expressly disclose a switching device.
Chang teaches (see figures 1-9) a driver integrated circuit (figure 4, part driver circuit connected to the switching device connected and controllable with the output ocp2 from NE555) controlled by the switching device (figure 4, part switching device connected and controllable with the output ocp2 from NE555), to switch off the semiconductor switch unit (figure 4, part off the semiconductor switch unit connected to 1mohm) when the switching device (figure 4, part switching device connected and controllable with the output ocp2 from NE555) receives the disable signal (figure 4, part through ocp2) (paragraph [0037]; Referring to FIG. 4 , a first embodiment of the present invention is an overcurrent protection circuit for a semiconductor switch. The semiconductor switch is a semiconductor power transistor such as an IGBT or MOSFET. The semiconductor switch includes a power terminal connected to a DC power supply, a ground terminal, and a control terminal connected to a control signal. A load is also connected between the power supply and the ground. The overcurrent protection circuit includes a current sampling circuit, an overcurrent protection comparator circuit, a NE555 monostable circuit, a transistor, a drive control circuit and a drive resistor R1 connected in series. The output of the drive control circuit is used to control the on and off of the semiconductor power tube after passing through the drive resistor R1… The output of the current sampling circuit is connected to the overcurrent protection comparator circuit, wherein the overcurrent protection comparator circuit includes a comparator and an inverter. The comparator outputs an ocp1 signal, which is connected to a NE555 monostable circuit via the inverter. The NE555 monostable circuit outputs an ocp2 signal, which is output through a transistor to form an OC gate and connected to the drive control circuit).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the device of DeJonge with the switching device features as taught by Chang and obtain a driver integrated circuit controlled by the switching device, to switch off the semiconductor switch unit when the switching device receives the disable signal, because it provides more efficient overcurrent protection circuit with more simple and cost effective controller (paragraph [0007]).
Regarding claim 8, DeJonge and Chang teach everything claimed as applied above (see claim 1). Further, DeJonge discloses (see figures 1-12) a voltage source (figure 4C, part voltage source that generates VI-TH1) connected to the comparator unit (figure 4C, part 482), for providing a freely selectable voltage defining the threshold value (figure 4C, part VI-TH1) to the comparator unit (figure 4C, part 482) (paragraph [0114]).
Regarding claim 9, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 11, claim 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 12, DeJonge and Chang teach everything claimed as applied above (see claim 11). Further, DeJonge discloses (see figures 1-12) the predefined blank time is set (figure 4C, part blank filter unit generated by 484 and 486; predefined blank time generated by 484) (paragraphs [0117]-[0118]; The timer 484 may be configured to start and run for a first time period when the output of the comparator 482 is driven high (e.g., when the magnitude of the current monitoring signal VI-MON is higher than the first voltage threshold VI-TH1, signifying that the magnitude of the monitored current IMON is above the first current threshold ITH1). The timer 484 may continue running as long as the output of the comparator 482 is driven high (e.g., for as long as the magnitude of the monitored current IMON is above the first current threshold ITH1). While the magnitude of the monitored current IMON remains above the first current threshold ITH1, the timer 484 may be configured to drive its output low until the timer 484 reaches the expiration of the first time period… If the timer 484 reaches the expiration of the first time period while the magnitude of the monitored current IMON has remained above the first current threshold I.sub.TH1, the timer 484 may be configured to drive its output high. The logic AND gate 486 may receive the outputs of the comparator 482 and the timer 484… When both of the outputs of the comparator 482 and the timer 484 are driven high (e.g., signifying the magnitude of the monitored current IMON has remained above the first current threshold ITH1 for the first period of time), the logic AND gate 486 may drive its output high to control the disable signal VI-DSBL). However, DeJonge does not expressly disclose the predefined blank time is set to: less than 1200 ns; or less than 600 ns; or less than 300 ns; or equal or less than 150 ns.
It would have been obvious matter of design choice to one having ordinary skill in the art before the effective filling date of the claimed invention to setting the blank time (as disclosed by DeJonge) to be less than 1200 ns; or less than 600 ns; or less than 300 ns; or equal or less than 150 ns, in order to meet with more precise overcurrent detection based on the design requirements. Additional, the invention would perform equally well with the overcurrent protection circuit as taught the combination of DeJonge and Chang.
Regarding claim 13, DeJonge and Chang teach everything claimed as applied above (see claim 9). Further, DeJonge discloses (see figures 1-12) an external shunt resistor (figure 4C, part 470; external to 464) is used as the resistor element (figure 4C, part 470).
Regarding claim 15, DeJonge and Chang teach everything claimed as applied above (see claim 9). Further, DeJonge discloses (see figures 1-12) a voltage (figure 4C, part VI-TH1) is freely selected to define the threshold value (figure 4C, part VI-TH1) (paragraph [0114]).
Claims 2, 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over DeJonge et al. (US 2022/0085610), hereinafter DeJonge, in view of Chang (CN 104993811; rejection based on English translation), and further in view of Liu et al. (US 2021/0409016), hereinafter Liu.
Regarding claim 2, DeJonge and Chang teach everything claimed as applied above (see claim 1). Further, DeJonge discloses (see figures 1-12) the resistor element (figure 4C, part 470) and the comparator unit (figure 4C, part 482). However, DeJonge does not expressly disclose a filter unit connected to the resistor element and configured to filter out interfering components from the voltage signal before supplying it to the comparator unit.
Liu teaches (see figures 1-4) a filter unit (figure 2, part filter unit generated by LPF 217 and 219) connected to the resistor element (figure 2, part 201) and configured to filter out interfering components (figure 2, part filter unit generated by LPF 217 and 219) from the voltage signal before supplying it to the comparator unit (figure 2, part 227) (paragraph [0025]; resistor 219 and capacitor 217 form a low pass filter structured to further filter high frequency noise).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the filter unit of Liu to the overcurrent protection circuit of DeJonge and obtain a filter unit connected to the resistor element and configured to filter out interfering components from the voltage signal before supplying it to the comparator unit, because it provides more efficient and accurate detection with high frequency noise reduction (paragraph [0025]).
Regarding claim 6, DeJonge and Chang teach everything claimed as applied above (see claim 1). Further, DeJonge discloses (see figures 1-12) the semiconductor switch unit (figure 4C, part 464) comprises one or more power semiconductors (figure 4C, part Q475a/Q475b). However, DeJonge does not expressly disclose Wide Band Gap power semiconductors.
Liu teaches (see figures 1-4) the semiconductor switch unit (figure 1, part 117/119) comprises one or more Wide Band Gap power semiconductors (figure 1, parts 117 and 119) (paragraph [0011]; Each power switch 117, 119 may include a wide-bandgap switch, such as an E-mode gallium nitride (GaN) switch, a cascode-mode GAN switch, or a silicon carbide switch, to name but a few examples).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the semiconductor switch unit of DeJonge with the Wide Band Gap power semiconductors features as taught by Liu, because it provides more efficient semiconductor with more compact and lighter structure.
Regarding claim 10, claim 2 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim 4 are rejected under 35 U.S.C. 103 as being unpatentable over DeJonge et al. (US 2022/0085610), hereinafter DeJonge, in view of Chang (CN 104993811; rejection based on English translation), and further in view of Garrett (US 5,469,002).
Regarding claim 4, DeJonge and Chang teach everything claimed as applied above (see claim 1). Further, DeJonge discloses (see figures 1-12) the resistor element (figure 4C, part 470) is configured as a shunt resistor external (figure 4C, part 470) to the semiconductor switch unit (figure 4C, part 464); and wherein the resistor element (figure 4C, part 470) is connected a drain of one of the set of semiconductor switches (figure 4C, part drain of Q475a). However, DeJonge does not expressly disclose the resistor element is connected between an emitter of the switching device.
Chang teaches (see figures 1-9) an emitter of the switching device (figure 4, part emitter of the switching device connected and controllable with the output ocp2 from NE555).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the device of DeJonge with the switching device features as taught by Chang, because it provides more efficient overcurrent protection circuit with more simple and cost effective controller (paragraph [0007]).
Garrett teaches (see figures 1-2) the resistor element (figure 2, part resistor element generated by 50/51) is configured as a shunt resistor external (figure 2, part resistor element generated by 50/51) to the semiconductor switch unit (figure 2, part 52); and wherein the resistor element (figure 2, part resistor element generated by 50/51) is connected between an emitter of the switching device (figure 2, part emitter of 54) and a drain of one of the set of semiconductor switches (figure 2, part drain of 52).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of DeJonge and Chang with the resistor features as taught by Garrett and obtain the resistor element is configured as a shunt resistor external to the semiconductor switch unit; and wherein the resistor element is connected between an emitter of the switching device and a drain of one of the set of semiconductor switches, because it provides more efficient control with more safe operation (Abstract).
Claim 14 are rejected under 35 U.S.C. 103 as being unpatentable over DeJonge et al. (US 2022/0085610), hereinafter DeJonge, in view of Chang (CN 104993811; rejection based on English translation), and further in view of Zhang et al. (US 10,868,466), hereinafter Zhang.
Regarding claim 14, DeJonge and Chang teach everything claimed as applied above (see claim 9). Further, DeJonge discloses (see figures 1-12) the amount of the amplified voltage signal is selected (figure 4C, part amplified voltage through 480) (paragraph [0113]; The current monitoring circuit 462 may be configured to monitor (e.g., measure) the magnitude of the monitored current IMON conducted through the current monitoring circuit 462 and the controllable switching circuit 464. The amplifier 480 of the current monitoring circuit 462 may be configured to receive a sense voltage VSNS developed across the resistor 470. The amplifier 480 may output a current monitoring signal VI-MON corresponding to the magnitude of the sense voltage VSNS). However, DeJonge does not expressly disclose the amount of the amplified voltage signal is selected within a range of:1 to 1000 mV; or 50 to 500 mV; or 75 to 150 mV.
Zhang teaches (see figures 1-3) the amount of the amplified voltage signal (figure 2B, part amplified voltage signal output from 205) is selected within a range of:1 to 1000 mV; or 50 to 500 mV; or 75 to 150 mV (column 6; lines 19-26; the sense resistor voltage thus range from zero to 50 mV, the output voltage of amplifier 205 will range from zero to 1.2 V).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the amplification unit of DeJonge with the amplification features as taught by Zhang, because it provides more accurate voltage scale value in order to obtain more efficient overcurrent protection.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838