Prosecution Insights
Last updated: April 19, 2026
Application No. 18/204,077

FERROELECTRIC MEMORY ARCHITECTURE WITH GAP REGION

Final Rejection §102§103
Filed
May 31, 2023
Examiner
BERNSTEIN, ALLISON
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
84%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
719 granted / 889 resolved
+12.9% vs TC avg
Minimal +3% lift
Without
With
+3.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
15 currently pending
Career history
904
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
38.0%
-2.0% vs TC avg
§102
35.8%
-4.2% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 889 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Acknowledgment is made of applicant’s amendment, filed on 11 February 2026. The changes and remarks disclosed therein have been considered. Claims 11-28 are pending in the application. No claims are currently amended. Claims 11 and 17 are independent claims. Claims 21-28 are new. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. ►Claim(s) 11, 13 and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al. (US 2021/0376231) (hereinafter, “Yin”). Re: independent claim 11, Yin discloses in fig. 22 an apparatus, comprising: a first memory cell (101) coupled with a first access line (648) and a first plate line (192); a second memory cell (101) coupled with a second access line (648) and a second plate line (192); a first sidewall and a second sidewall between the first memory cell and the second memory cell, the first and second sidewalls (162) comprising a first dielectric material [0058] and separated by a gap region (170); and a cap (176) over the first sidewall, the second sidewall, and the gap region, the cap comprising a second dielectric material [0065]. Re: claim 13, Yin discloses in fig. 22 the apparatus of claim 11, further comprising: a transistor array (750) below the first memory cell and the second memory cell. Re: claim 15, Yin discloses in fig. 22 the apparatus of claim 11, wherein the first memory cell comprises: a ferroelectric material [0044]; a first electrode (126) configured to couple the ferroelectric material with the first access line (648); and a second electrode (158) configured to couple the ferroelectric material with the first plate line (192). Re: claim 16, Yin discloses in fig. 22 the apparatus of claim 11, wherein: the first access line (648) comprises a first digit line [0036]; and the second access line (648) comprises a second digit line [0036]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. ►Claims 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al. (US 2021/0376231) (hereinafter, “Yin”) in view of Jones Jr. (US 5,373,463). Re: claim 12, Yin discloses in fig. 22 the apparatus of claim 11. Yin does not expressly disclose a third memory cell coupled with a third access line and the first plate line; and a word line coupled with the first memory cell and the third memory cell. Jones Jr. discloses in fig. 3 a first memory cell (86) coupled with a first access line (BL0) and a first plate line (DLS0); a third memory cell (87) coupled with a third access line (BL1) and the first plate line (DLS0); and a word line (WL0) coupled with the first memory cell and the third memory cell. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a third memory cell as claimed for the purpose of reducing energy consumption as exemplified by Jones Jr. (abstract). Re: claim 14, Yin discloses in fig. 22 the apparatus of claim 13. Yin does not disclose expressly wherein the transistor array comprises: a first transistor configured to couple the first access line with a sense amplifier; and a second transistor configured to couple the second access line with the sense amplifier. Jones Jr. discloses in fig. 3 a transistor array comprising: a first transistor (86) configured to couple a first access line (BL0) with a sense amplifier (64); and a second transistor (87) configured to couple a second access line (BL1) with the sense amplifier (64). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple the first transistor and the second transistor to a sense amplifier for the purpose of operating the memory cell as exemplified by Jones Jr. ►Claims 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones Jr. (US 5,373,463) in view of Yin et al. (US 2021/0376231) (hereinafter, “Yin”). Re: independent claim 17, Jones Jr. discloses in fig. 4 an apparatus, comprising: a first pair of memory cells (102 coupled to WL1N, DLS12) configured to store a single logic state and comprising a first memory cell (104, 105) and a second memory cell (106, 107); a second pair of memory cells (102 coupled to WL11, DLS11) configured to store a single logic state and comprising a third memory cell (104, 105) and a fourth memory cell (106, 107). Jones Jr. does not disclose a first sidewall and a second sidewall between the first pair of memory cells and the second pair of memory cells, the first and second sidewalls comprising a first dielectric material and separated by a gap region; and a cap over the first sidewall, the second sidewall, and the gap region, the cap comprising a second dielectric material. Yin discloses in fig. 22 a first sidewall and a second sidewall between a first memory cell (101) and a second memory cell (101), the first and second sidewalls (162) comprising a first dielectric material [0058] and separated by a gap region (170); and a cap (176) over the first sidewall, the second sidewall, and the gap region, the cap comprising a second dielectric material [0065]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a gap region between first and second sidewalls as claimed for the purpose of insulating adjacent memory cells as exemplified by Yin. Re: claim 18, Jones Jr. in view of Yin discloses the apparatus of claim 17, further comprising: a first access line (Jones Jr.: BL10; Yin: 648) coupled with the first memory cell of the first pair of memory cells; and a second access line (Jones Jr.: BL10*; Yin: 648) coupled with the second memory cell of the first pair of memory cells. Re: claim 19, Jones Jr. in view of Yin discloses the apparatus of claim 17, further comprising: a first plate line (Jones Jr.: DLS12) coupled with the first pair of memory cells; and a second plate line (Jones Jr.: DLS11) coupled with the second pair of memory cells. Re: claim 20, Jones Jr. in view of Yin discloses the apparatus of claim 17, further comprising: a transistor array (Yin: 750) below the first pair of memory cells and the second pair of memory cells. ►Claims 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al. (US 2021/0376231) (hereinafter, “Yin”) in view of Jung (US 2017/0170237). Re: claim 21, Yin discloses the apparatus of claim 11. Yin does not disclose wherein the gap region comprises a void between the first sidewall and the second sidewall. Jung discloses a gap region comprising a void (260b, [0224]) between a first sidewall and a second sidewall. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a void between the first sidewall and the second sidewall since it is common and well known in the art to separate adjacent memory cells with a dielectric material or a void including an air gap as taught by Jung [0224]. Re: claim 22, Yin discloses the apparatus of claim 11, wherein the first dielectric material (162, [0058]) has a first dielectric constant; and the gap region (170, [0061]) comprises a substance having a second dielectric constant. Yin does not disclose expressly wherein the second dielectric constant is lower than the first dielectric constant corresponding to the first dielectric material. Jung discloses a gap region (260b, [0224]) comprising a substance (e.g. air) having a second dielectric constant lower than a first dielectric constant corresponding to a first dielectric material (40, [0072]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a gap region comprising a substance (e.g. air) having a second dielectric constant lower than a first dielectric constant corresponding to the first dielectric material since a void including an air gap is commonly used in the art to separate adjacent memory cells as taught by Jung (260b, [0224]). Re: claim 23, Yin in view of Jung further discloses the apparatus of claim 22, wherein the gap region comprises a fluid substance (Jung: 260b, [0224]) between the first sidewall and the second sidewall. Re: claim 24, Yin in view of Jung further discloses the apparatus of claim 23, wherein the fluid substance comprises air (Jung: [0224]). ►Claims 25-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones Jr. (US 5,373,463) in view of Yin et al. (US 2021/0376231) (hereinafter, “Yin”) and further in view of Jung (US 2017/0170237). Re: claim 25, Jones Jr. in view of Yin discloses the apparatus of claim 17. Jones Jr. in view of Yin does not disclose wherein the gap region comprises a void between the first sidewall and the second sidewall. Jung discloses a gap region comprising a void (260b, [0224]) between a first sidewall and a second sidewall. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a void between the first sidewall and the second sidewall since it is common and well known in the art to separate adjacent memory cells with a dielectric material or a void including an air gap as taught by Jung [0224]. Re: claim 26, Jones Jr. in view of Yin discloses the apparatus of claim 17, wherein the first dielectric material (Yin: 162, [0058]) has a first dielectric constant; and the gap region (Yin: 170, [0061]) comprises a substance having a second dielectric constant. Jones Jr. in view of Yin does not disclose expressly wherein the second dielectric constant is lower than the first dielectric constant corresponding to the first dielectric material. Jung discloses a gap region (260b, [0224]) comprising a substance (e.g. air) having a second dielectric constant lower than a first dielectric constant corresponding to a first dielectric material (40, [0072]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a gap region comprising a substance (e.g. air) having a second dielectric constant lower than a first dielectric constant corresponding to the first dielectric material since a void including an air gap is commonly used in the art to separate adjacent memory cells as taught by Jung (260b, [0224]). Re: claim 27, Jones Jr. in view of Yin and further in view of Jung further discloses the apparatus of claim 26, wherein the gap region comprises a fluid substance (Jung: 260b, [0224]) between the first sidewall and the second sidewall. Re: claim 28, Jones Jr. in view of Yin and further in view of Jung further discloses the apparatus of claim 27, wherein the fluid substance comprises air (Jung: [0224]). Response to Arguments Applicant's arguments filed 11 February 2026 have been fully considered but they are not persuasive. Applicant argues that Yin fails to disclose a gap region between the first sidewall and the second sidewall since the region between the first sidewall and the second sidewall includes a dielectric material. In response, according to the specification of the instant application the gap may include a solid material [0084]. Therefore, the gap region including a dielectric material as taught by Yin reads on the claimed “gap region”. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 2/24/2026
Read full office action

Prosecution Timeline

May 31, 2023
Application Filed
Nov 07, 2025
Non-Final Rejection — §102, §103
Feb 11, 2026
Response Filed
Feb 25, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
84%
With Interview (+3.2%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 889 resolved cases by this examiner. Grant probability derived from career allow rate.

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