INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE CONTACT STITCHING

Application No. 18/204,204

• Filed: May 31, 2023
• Examiner: ROBERTSON, NOAH CHRISTOPHER
• Assignee: Intel Corporation
• OA Round: 1 (Non-Final)

Office Action

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Election/Restrictions
Applicant’s election without traverse of Species I, and Sub-Species IA, in the reply filed on August 21st, 2026, is acknowledged. Therefore, Claims 3-4, 6-10, and 13 are withdrawn from further considerations pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. As such, the Election/Restriction requirement is hereby made FINAL.

Status of Claims
Claims 1-20 are pending. However, Claims 3-4, 6-10, and 13 have been withdrawn, as stated above. Therefore, Claims 1-2, 5, 11-12, and 14-20 are subject to the within examination.

Information Disclosure Statement
The information disclosure statement (IDS) filed on September 3rd, 2024, is being considered by the examiner.

Specification
The specification is further objected to as the section headings are in bold. Pursuant to MPEP §
608.01(a) and 37 CFR 1.77:
(c) The text of the specification section defined in paragraphs (b)(1) through (b)(12) of this section, if applicable, should be preceded by a section heading in uppercase and without underlining or bold type (emphasis added).

Appropriate correction is required.

Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.

Claim(s) 1, 2, and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung, et al. (US 2022/0319981 A1; hereinafter referred to as Chung).

Regarding Claim 1, Chung discloses an integrated circuit structure (semiconductor device structure 200a, Figs. 2F, 2G), comprising:
a first plurality of horizontally stacked nanowires (nanostructures 104/106, [0015], Fig. 1L-1);
a second plurality of horizontally stacked nanowires laterally spaced apart from the first plurality of horizontally stacked nanowires (nanostructures 104/106, [0015], Fig. 1L-1);
a first epitaxial source or drain structure at an end of the first plurality of horizontally stacked nanowires (first S/D structure 183a, [0040], Fig. 2G; “the first S/D structure 138a and the second SID structure 138b are formed by an epitaxy or epitaxial (epi) process”);
a second epitaxial source or drain structure at an end of the second plurality of horizontally stacked nanowires (second S/D structure 183b, [0040], Fig. 2G; “the first S/D structure 138a and the second SID structure 138b are formed by an epitaxy or epitaxial (epi) process”); and
a conductive contact structure beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure (second contact structure 174a, [0076], Figs. 2F, 2G), the conductive contact structure continuous between the first epitaxial source or drain structure and the second epitaxial source or drain structure (Figs. 2F, 2G), and the conductive contact structure having a first vertical thickness beneath the first epitaxial source or drain structure and the second epitaxial source or drain structure greater than a second vertical thickness in a region between the first epitaxial source or drain structure and the second epitaxial source or drain structure (see Annotated Fig. 2G).

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Regarding Claim 2, Chung discloses the integrated circuit structure of claim 1, wherein the conductive contact structure has a lateral width beneath the first epitaxial source or drain structure and the second epitaxial source or drain structure less than a lateral width in the region between the first epitaxial source or drain structure and the second epitaxial source or drain structure (Fig. 2G).

Regarding Claim 5, Chung discloses the integrated circuit structure of claim 1, wherein the portion of the conductive contact structure having the first vertical thickness is laterally offset from the portion of the conductive contact structure having the second vertical thickness (Fig. 2G).

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.

Claim(s) 11, 12, and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Glass, et al. (US 2020/0105871 A1; hereinafter referred to as Glass) and further in view of Chung.

Regarding Claim 11, Glass discloses a computing device (computing device 1000, [0122]), comprising:
a board (board 1002, [0122], Fig. 10); and
a component coupled to the board (processor 1004, [0122], Fig. 10), the component including an integrated circuit structure (integrated circuit die, [0125]).
Glass fails to explicitly disclose the integrated circuit structure as disclosed in Claim 1.
However, in analogous art, Chung discloses an integrated circuit structure (Chung: semiconductor device structure 200a, Figs. 2F, 2G), comprising:
a first plurality of horizontally stacked nanowires or a first fin (Chung: nanostructures 104/106, [0015], Fig. 1L-1);
a second plurality of horizontally stacked nanowires or a second fin laterally spaced apart from the first plurality of horizontally stacked nanowires (Chung: nanostructures 104/106, [0015], Fig. 1L-1);
a first epitaxial source or drain structure at an end of the first plurality of horizontally stacked nanowires or the first fin (Chung: first S/D structure 183a, [0040], Fig. 2G; “the first S/D structure 138a and the second SID structure 138b are formed by an epitaxy or epitaxial (epi) process”);
a second epitaxial source or drain structure at an end of the second plurality of horizontally stacked nanowires or the second fin (Chung: second S/D structure 183b, [0040], Fig. 2G; “the first S/D structure 138a and the second SID structure 138b are formed by an epitaxy or epitaxial (epi) process”); and
a conductive contact structure beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure (Chung: second contact structure 174a, [0076], Figs. 2F, 2G), the conductive contact structure continuous between the first epitaxial source or drain structure and the second epitaxial source or drain structure (Chung: Figs. 2F, 2G), and the conductive contact structure having a first vertical thickness beneath the first epitaxial source or drain structure and the second epitaxial source or drain structure greater than a second vertical thickness in a region between the first epitaxial source or drain structure and the second epitaxial source or drain structure (Chung: see Annotated Fig. 2G).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the computing device of Glass such that the component used an integrated circuit structure as disclosed by Chung. One would be motivated to do so because the structure of Chung leads to reduced parasitic resistance between contact structures on the frontside and backside of the device, which leads to increased performance (Chung: [0065]).

Regarding Claim 12, Glass/Chung discloses the computing device of claim 11, comprising the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires (Glass: Fig. 3 a first nanowire stack and a second nanowire stack are used in the integrated circuit structure; Chung: [0015]).

Regarding Claim 14, Glass/Chung discloses the computing device of claim 11, further comprising:
a memory coupled to the board (Glass: volatile memory DRAM, Fig. 10).

Regarding Claim 15, Glass/Chung discloses the computing device of claim 11, further comprising:
a communication chip coupled to the board (Glass: communication chip 1006, Fig. 10).

Regarding Claim 16, Glass/Chung discloses the computing device of claim 11, further comprising:
a battery coupled to the board (Glass: BATTERY, Fig. 10).

Regarding Claim 17, Glass/Chung discloses the computing device of claim 11, further comprising:
a camera coupled to the board (Glass: CAMERA, Fig. 10).

Regarding Claim 18, Glass/Chung discloses the computing device of claim 11, further comprising:
a display coupled to the board (Glass: display, [0123], Fig. 10).

Regarding Claim 19, Glass/Chung discloses the computing device of claim 11, wherein the component is a packaged integrated circuit die (Glass: [0125]).

Regarding Claim 20, Glass/Chung discloses the computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Glass: [0121, 0123]).

Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Lee, et al. (US 2024/0258388 A1); discloses an IC with a conductive contact structure;
(b) Liao, et al. (US 2021/0336063 A1); discloses an analogous IC structure;
(c) Ramaswamy, et al. (US 2020/0335592 A1); discloses transistor arrangements;

Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is [phone]. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).

Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.

If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].

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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812

Prosecution Timeline

• May 31, 2023: Application Filed
• Aug 03, 2023: Response after Non-Final Action
• Sep 16, 2026: Non-Final Rejection mailed — §102, §103 (current)