DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/15/2026 has been entered.
Response to Amendments
Applicant's response of 06/02/2026 has been acknowledged. Claims 1, 7, 11, 13, and 18 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 06/02/2026 with respect to the rejection of claims 1, 11, and 18 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Omori (US 20160300804 A1 – hereinafter Omori) in view of Bhagavat et al. (US 11011466 B2 – hereinafter Bhagavat) and Tiemeijer at al. (US 20200402698 A1 – hereinafter Tiemeijer).
Regarding independent claim 1, Omori teaches
(Currently Amended) A semiconductor device ([0002] – “present
invention relates to semiconductor devices” – hereinafter ‘SCD’) comprising:
a substrate (SUB – Fig. 1 – [0051 – “substrate SUB”);
an element layer (Fig. 1 annotated, see below – hereinafter ‘FEOL’) including
circuit elements (TR – Fig. 1 annotated, see below – [0051] – “transistor TR” – a transistor is contained in a circuit element – hereinafter ‘CD’) arranged on the substrate (SUB);
a wiring layer (Fig. 1 annotated, see below – hereinafter ‘BEOL’) on the
element layer (FEOL); and
a redistribution layer (Fig. 1 annotated, see below – hereinafter ‘RDL’) on the
wiring layer (BEOL),
wherein the redistribution layer (RDL) includes a redistribution insulating
layer (PVF – Fig. 1 – [0060] – “passivation film PVF is formed of a silicon nitride film”) and a redistribution conductive layer (MBR – Fig. 1 – [0054] – “metal film MBR”) on the redistribution insulating layer (PVF),
wherein the redistribution conductive layer (RDL) includes a connection pad (MPD – Fig. 1 – [0058] – “pad portion MPD is formed to be in contact with an upper surface of the copper redistribution line CPH”) and first and second inductor structures respectively including first and second inductor redistribution lines having a planar coil shape in a same redistribution conductive layer as each other,
wherein the first and second inductor redistribution lines included in the first and second inductor structures have different thicknesses.
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Omori does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Bhagavat teaches
wherein the first (205a – Fig. 2 – [6:28-34] – “plural conductive pillars, a few of which are labeled 205a, 205b, 205c, 205d and 205e, that connect at their upper ends to one or more of the conductor traces 165a, 165b and 165c of the RDL structure 115 and at their lower ends to conductor structures 210 or the conductor traces 165d, 165e, 165f and 165g that are fabricated in the RDL structure 172” – this is a redistribution line) and second (205b – Fig. 2 – [6:28-34] – “plural conductive pillars, a few of which are labeled 205a, 205b, 205c, 205d and 205e, that connect at their upper ends to one or more of the conductor traces 165a, 165b and 165c of the RDL structure 115 and at their lower ends to conductor structures 210 or the conductor traces 165d, 165e, 165f and 165g that are fabricated in the RDL structure 172” – this is a redistribution line) inductor redistribution lines included in the first (155) and second (150) inductor structures have different thicknesses (fig 5 shows) (bha ([58 = 8:7-16] – “It should be understood that the number of traces and pillars that make up the inductor 155 and disclosed alternatives can be varied. Indeed, it should be noted that the structures that make up a given inductor, such as the inductor 155 or any disclosed alternatives, can be constructed to deliver a desired inductance. For example, the widths, thicknesses, spacings, numbers and material compositions of the conductor traces 165a, 165b, 165c, 165d, 165e, 165f and 165g and the pillars 205b, 205c, 205d, 205e, 205f, 205g and 205h can be selected to yield a desired inductance” – this is interpreted that the thickness of 205 elements can vary in different inductors 150 or 155).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor and redistribution line structure as taught by Bhagavat into Omori.
An ordinary artisan would have been motivated to use the known technique of Bhagavat in the manner set forth above to produce the predictable result of [1:25-29] – “One of the principal advantages of a flip-chip mounting strategy is the relatively short electrical pathways between the integrated circuit and the substrate. These relatively low inductance pathways yield a high speed performance for the electronic device.”
Omori and Bhagavat do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Tiemeijer teaches
first (101 – Fig. 10 – [0040] – “primary/gate coil winding 101 includes first curve-shaped top metal winding layer 111 and a second curve-shaped top metal winding layer 112 formed in the fifth metal layer M9”) and second (102 – Fig. 10 – [0040] – “the upper secondary/drain coil winding 102 includes a concentric, circularly-shaped top metal winding layer 113”) inductor structures respectively including first and second inductor redistribution lines (111 and 112 – Fig. 10 – [0040] – “primary/gate coil winding 101 includes first curve-shaped top metal winding layer 111 and a second curve-shaped top metal winding layer 112 formed in the fifth metal layer M9”) having a planar coil shape (Fig. 10 shows the coil shape and Fig. 11 shows the planar configuration) in a same redistribution conductive layer as each other (M9 – [0040] – “metal layer M9 may be formed into an upper primary/gate coil winding 101 and a secondary/drain coil winding 102 by patterning and etching a topmost relatively thick metal routing layer M9”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the planar coil inductor structure as taught by Tiemeijer into Omori and Bhagavat.
An ordinary artisan would have been motivated to use the known technique of Tiemeijer in the manner set forth above to produce the predictable result [0002] – “an integrated circuit transformer can form two interleaved metal coils in one or more thickest upper layers which include an integer number of approximately circular turns. This can be advantageous since the top metal layers in an integrated circuit process technology have the largest thickness, and thus the lowest resistivity, and are therefore the most suitable layers for transformer windings which generally will carry the largest currents.”
Regarding claim 8, Omori, as modified by Bhagavat and Tiemeijer, teaches claim 1 from which claim 8 depends. Omori further teaches
(Original) The semiconductor device of claim 1, further comprising a protective layer (PID – Fig. 1 – [0058] – “polyimide film PID is formed to cover the redistribution portion CRL”) on the redistribution insulating layer (PVF) and arranged to cover part of the redistribution conductive layer (MBR), wherein the connection pad (MPD) is not covered by the protective layer (PID – [0058] – “opening PHP for exposing the pad portion MPD is formed in the polyimide film PID” – Fig. 1 shows this).
Regarding claim 9, Omori, as modified by Bhagavat and Tiemeijer, teaches claim 8 from which claim 9 depends. Omori further teaches
(Original) The semiconductor device of claim 8, wherein each of a
plurality of inductor line patterns (CPH – Fig. 18 – [0057] – “redistribution line CPH”) is covered by the protective layer (PID – Fig. 18 shows this).
Claims 2, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Bhagavat, Tiemeijer, and Yeon et al. (US 20210028102 A1 – hereinafter Yeon).
Regarding claim 2, Omori as modified by Bhagavat and Tiemeijer, teaches claim 1 from which claim 2 depends. Omori, Bhagavat, and Tiemeijer do not expressly disclose the limitations of claim 1.
However, in an analogous art, Yeon teaches
(Original) The semiconductor device of claim 1, wherein a thickness of the
first inductor redistribution line (117a – Fig. 1 – [0035] – “passive element pattern 117 may include a first plate-type conductive pattern 117a” – this is interpreted as inductor redistribution line) included in the first inductor structure (117 – Fig. 1 – [0033] – “passive element pattern 117” – this is interpreted as the inductor structure) is substantially equal to a thickness of the connection pad (116 – Fig. 1 – [0038] – “the passive element pattern 117 and the connection pads 116 may have a thickness of about 2 μm to about 5 μm” – this is interpreted as both elements having the same thickness).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the thickness of the inductor structure as taught by Yeon into Omori, Bhagavat, and Tiemeijer.
An ordinary artisan would have been motivated to use the known technique of Yeon in the manner set forth above to produce the predictable result to [0004] – “provide semiconductor packages that are thin and lightweight.”
Regarding claim 6, Omori as modified by Bhagavat and Tiemeijer, teaches claim 1 from which claim 6 depends. Omori and Tiemeijer do not expressly disclose the limitations of claim 6.
However, in an analogous art, Bhagavat teaches
the first (155) and second (150) inductor structures.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor and redistribution line structure as taught by Bhagavat into Omori and Tiemeijer.
An ordinary artisan would have been motivated to use the known technique of Bhagavat in the manner set forth above to produce the predictable result as stated above in claim 6.
Omori, Tiemeijer, and Bhagavat do not expressly disclose the limitations of claim 6.
However, in an analogous art, Yeon teaches
(Previously Presented) The semiconductor device of claim 1, wherein a
lower surface of the first (117a – Fig. 1 – [0033] – “bottom surface
of the passive element pattern 117 may be in contact with the top surfaces of the ones of the conductive vias 115”) and second (117b – Fig. 1 – [0033] – “bottom surface of the passive element pattern 117 may be in contact with the top surfaces of the ones of the conductive vias 115”) inductor redistribution lines respectively included in each of the first and second inductor structures is at a same vertical level as a lower surface of the connection pad (116 – Fig. 1 – [0031] – “bottom surfaces of the connection pads 116 may be in contact with top surfaces of the conductive vias 115”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the positioning of the inductor structure as taught by Yeon into Omori, Tiemeijer, and Bhagavat.
An ordinary artisan would have been motivated to use the known technique of Yeon in the manner set forth above to produce the predictable result as stated above in claim 2.
Regarding claim 7, Omori as modified by Bhagavat, Tiemeijer, and Yeon, teaches claim 6 from which claim 7 depends. Omori and Tiemeijer do not expressly disclose the limitations of claim 7.
However, in an analogous art, Bhagavat teaches
the first (155) and second (150) inductor structures.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor and redistribution line structure as taught by Bhagavat into Omori and Tiemeijer.
An ordinary artisan would have been motivated to use the known technique of Bhagavat in the manner set forth above to produce the predictable result as stated above in claim 1.
Omori, Tiemeijer, and Bhagavat do not expressly disclose the limitations of claim 7.
However, in an analogous art, Yeon teaches
(Currently Amended) The semiconductor device of claim 6, wherein the
first (117a) and second (117b) inductor redistribution lines respectively included in each of the first and second inductor structures comprises [[the]] a same material as the connection pad (116 – [0037] – “the passive element pattern 117 may include substantially the same material as the connection pads 116”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the redistribution line and connection pad material as taught by Yeon into Omori, Tiemeijer, and Bhagavat.
An ordinary artisan would have been motivated to use the known technique of Yeon in the manner set forth above to produce the predictable result of reducing manufacturing costs by using the same conductive material.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Bhagavat, Tiemeijer, Yeon, and Nakashiba (US 20200411434 A1 – hereinafter Nakashiba-434).
Regarding claim 3, Omori as modified by Bhagavat, Tiemeijer, and Yeon, teaches claim 2 from which claim 3 depends. Omori, Bhagavat, Tiemeijer, and Yeon do not expressly disclose the limitations of claim 3.
However, in an analogous art, Nakashiba-434 teaches
(Original) The semiconductor device of claim 2, wherein the first (IND2 –
Fig. 2 – [0065] – “inductor IND2”) and second (IND1 – Fig. 2 – [0065] – “inductor IND1”) inductor structures are of a plurality of inductor structures (IND1 and IND2 make up a plurality of induction structures), and wherein the first inductor redistribution line included in the first inductor structure ([0065] – “inductor IND2 may be formed in the multilayer wiring layer MWL or may be formed in a redistribution line layer” – interpreted as having a redistribution line) has a greatest thickness ([0065] – “A thickness of the second inductor IND2 may be greater than or equal to a thickness of the first inductor IND1”) among the inductor redistribution lines included in the plurality of inductor structures.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the plurality of inductor structures as taught by Nakashiba-434 into Omori, Bhagavat, Tiemeijer, and Yeon.
An ordinary artisan would have been motivated to use the known technique of Nakashiba-434 in the manner set forth above to produce the predictable result of [0012] – “a semiconductor device can be miniaturized.”
Regarding claim 4, Omori as modified by Bhagavat, Tiemeijer, and Yeon, teaches claim 2 from which claim 4 depends. Omori, Bhagavat, Tiemeijer, and Yeon do not expressly disclose the limitations of claim 4.
However, in an analogous art, Nakashiba-434 teaches
(Original) The semiconductor device of claim 2, wherein the thickness of
the first inductor redistribution line included in the first inductor structure ([0065] – “inductor IND2 may be formed in the multilayer wiring layer MWL or may be formed in a redistribution line layer” – interpreted as IND2 has a redistribution line) is greater than a thickness ([0065] – “A thickness of the second inductor IND2 may be greater than or equal to a thickness of the first inductor IND1”) of the second inductor redistribution line included in the second inductor structure ([0065] – “inductor IND2 may be formed in the multilayer wiring layer MWL or may be formed in a redistribution line layer” – interpreted as IND1 also has a redistribution line).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the thickness of the inductor structures as taught by Nakashiba-434 into Omori, Bhagavat, Tiemeijer, and Yeon.
An ordinary artisan would have been motivated to use the known technique of Nakashiba-434 in the manner set forth above to produce the predictable result as stated above in claim 3.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Bhagavat, Tiemeijer, Yeon, Nakashiba-434 and Bedair et al. (US 20110018136 A1 – hereinafter Bedair).
Regarding claim 5, Omori as modified by Bhagavat, Tiemeijer, Yeon, and Nakashiba-434, teaches claim 4 from which claim 5 depends. Omori, Bhagavat, Tiemeijer, Yeon, and Nakashiba-434 do not expressly disclose the limitations of claim 5.
However, in an analogous art, Bedair teaches
(Original) The semiconductor device of claim 4, wherein the first (95D – Fig.
3 – [0097] – “power inductor 95D”) and second (95D – Fig. 3 – [0097] – “RF inductor 95C”) inductor structures are of a plurality of inductor structures ([0096] – “plurality of passive devices 95” – inductors are passive devices, hereinafter ‘IDT’), and wherein at least one of the plurality of inductor structures (IDT) comprises a radio frequency (RF) inductor (95D – Fig. 3 – [0097] – “power inductor 95D”), and at least one of the other inductor structures comprises a power inductor (95D – Fig. 3 – [0097] – “power inductor 95D”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor structures as taught by Bedair into Omori, Bhagavat, Tiemeijer, Yeon, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Bedair in the manner set forth above to produce the predictable result of [0003] – “The development of sensors and autonomous platforms for mobile microsystems capable of accessing restricted locations is driving the need for scaled, efficient power generation, conversion and management systems.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Bhagavat, Tiemeijer, and Andoh et al. (US 5095357 A – hereinafter Andoh).
Regarding claim 10, Omori as modified by Bhagavat and Tiemeijer, teaches claim 8 from which claim 10 depends. Omori, Bhagavat, and Tiemeijer do not expressly disclose the limitations of claim 10.
However, in an analogous art, Andoh teaches
(Original) The semiconductor device of claim 8, wherein a ferromagnetic
structure (36 – Fig. 11(a) – [8:30-33] – “ferromagnetic body 36, such as a ferrite, is disposed within that common central opening to improve the mutual inductance of windings 28 and 34”) including a ferromagnetic material is in a central portion (Fig. 11(a) show this – hereinafter ‘ICP’) of the inductor redistribution line (28 – Fig. 11(b) – [8:32-33] – “winding 28” – this is a redistribution line) of each of the first (Fig. 11(b) – element 28 is part of the structure, hereinafter (‘IDT1’) and second (Fig. 11(b) [8:33] – “winding 34” – element 34 is part of the structure, hereinafter (‘IDT2’) inductor structures, and
wherein the protective layer (33 – Fig. 11(a) – [8:28] – “insulating film 33” – this is a protective layer) is in a gap that is a space between adjacent portions of the inductor redistribution line (28) of each of the first and second inductor structures (28 and 34Figs. 11(a) and (11(b) show this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the ferromagnetic material and protection structures as taught by Andoh into Omori, Bhagavat, and Tiemeijer.
An ordinary artisan would have been motivated to use the known technique of Andoh in the manner set forth above to produce the predictable result [1:41-45] – “to provide inductive structures integrable with semiconductor integrated circuits that have increased inductances and inductive coupling, improved performance, reduced areas and volumes, and reduced parasitic capacitances.”
Claims 11-14, and 17 is rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Yeon, Tiemeijer, and Nakashiba-434.
Regarding independent claim 11, Omori teaches:
(Currently Amended) A semiconductor device ([0002] – “present
invention relates to semiconductor devices” – hereinafter ‘SCD’) comprising:
a substrate (SUB – Fig. 1 – [0051 – “substrate SUB”);
an element layer including (Fig. 1 annotated, see below – hereinafter ‘FEOL’)
circuit elements (TR – Fig. 1 annotated, see below – [0051] – “transistor TR” – a transistor is contained in a circuit element – hereinafter ‘CD’) arranged on the substrate (SUB);
a wiring layer (Fig. 1 annotated, see below – hereinafter ‘BEOL’) formed on the
element layer (FEOL) and including an inter-wiring insulating layer, a lower wiring line and an upper wiring line respectively on a lower surface and an upper surface of the inter-wiring insulating layer, and a wiring via passing through the inter-wiring insulating layer and electrically connecting the lower wiring line to the upper wiring line;
a wiring contact plug electrically connecting the lower wiring line to the circuit element; and
a redistribution layer (RDL) formed on the wiring layer (BEOL) and including a redistribution insulating layer (PVF – Fig. 1 – [0060] – “passivation film PVF is formed of a silicon nitride film”) and a redistribution conductive layer (MBR – Fig. 1 – [0054] – “metal film MBR”),
wherein the redistribution conductive layer (RDL) includes a plurality of inductor redistribution lines (CPH – Fig. 18 – [0057] – “redistribution line CPH”) each having a planar coil shape on the redistribution insulating layer (PVF – Fig. 1 – [0060] – “passivation film PVF is formed of a silicon nitride film”), a connection pad (MPD – Fig. 1 – [0058] – “pad portion MPD is formed to be in contact with an upper surface of the copper redistribution line CPH”) connected on the redistribution insulating layer (PVF), a connection pad connected redistribution line (CRL – Fig. 1 – [0057] – “redistribution portion CRL”) extending on the redistribution insulating layer (PVF), and a redistribution via (PVH – Fig. 1 – [0054] – “passivation film PVF is provided with an opening PVH communicating with the third wiring ML3”) that extends through the redistribution insulating layer (PVF) and is electrically connected to the upper wiring line (ML3 – Fig. 1 – [0054] – “passivation film PVF is provided with an opening PVH communicating with the third wiring ML3”) and to one the connection pad connected redistribution line (CRL) or one of the inductor redistribution line (CPH), and
the plurality of inductor redistribution lines include a first inductor redistribution line having a first thickness and a second inductor redistribution line having a second thickness that is less than the first thickness, wherein the first inductor redistribution line and the second inductor redistribution line are in the same material layer as each other.
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Omori does not expressly disclose the other limitations of claim 11.
However, in an analogous art, Yeon teaches
including an inter-wiring insulating layer (112b and 114b – Fig. 1 – {[0022] – “lower redistribution insulating layer 112b”}, {[0027] – “upper redistribution insulating layer 114b”} – these are made of the same material and can be considered the same layer with element 111 embedded), a lower wiring line (112a – Fig. 1 – [0025] – “lower redistribution pattern 112a”) and an upper wiring line (114a – Fig. 1 – [0026] – “upper redistribution pattern 114a”) respectively on a lower surface and an upper surface of the inter-wiring insulating layer (400), and a wiring via (110 – Fig. 1 – [0020] – “through silicon via 110”) passing through the inter-wiring insulating layer (400) and electrically connecting the lower wiring line (112a – [0073] – “semiconductor device 111 may be electrically connected to the through silicon via 110, the lower redistribution pattern 112a”) to the upper wiring line (114a – [0027] – “upper redistribution pattern 114a may be electrically connected to the through silicon via 110 of the first semiconductor device 111”);
a wiring contact plug ([0021] – “the buried conductive layer of the through silicon via 110 may be electrically connected to the first semiconductor element layer 111a” – hereinafter ‘MC’) electrically connecting the lower wiring line (112a) to the circuit element (111a – Fig. 1 – [0019] – “semiconductor element layer 111a may include various kinds of individual elements. The plurality of individual elements may include various microelectronic devices such as, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) (e.g., a complementary-metal-oxide-semiconductor (CMOS) transistor)), a system large-scale integration (LSI) device, an image sensor (e.g., CMOS imaging sensor (CIS)), and/or a micro-electro-mechanical system (MEMS)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the wiring structure as taught by Yeon into Omori.
An ordinary artisan would have been motivated to use the known technique of Yeon in the manner set forth above to produce the predictable result as stated above in claim 2.
Omori and Yeon do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Tiemeijer teaches
each having a planar coil shape (Fig. 10 shows the coil shape and Fig. 11 shows the planar configuration).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor shape structure as taught by Tiemeijer into Omori and Bhagavat.
An ordinary artisan would have been motivated to use the known technique of Tiemeijer in the manner set forth above to produce the predictable result as stated above in claim 1.
Omori, Yeon, and Tiemeijer do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Nakashiba-434 teaches
the plurality of inductor redistribution lines ({IND1 – Fig. 2 – [0065] – “inductor IND1”}, {IND2 – Fig. 2 – [0065] – “inductor IND2”} – this is a plurality) include a first inductor redistribution line (IND2) having a first thickness and a second inductor redistribution line (IND1) having a second thickness that is less than the first thickness ([0065] – “A thickness of the second inductor IND2 may be greater than or equal to a thickness of the first inductor IND1”), wherein the first inductor redistribution line and the second inductor redistribution line are in the same material layer as each other ([0065] – “The second inductor IND2 may be formed in the same layer as the first inductor IND1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the thickness of the inductor redistribution lines structures as taught by Nakashiba-434 into Omori, Bhagavat, Tiemeijer, and Yeon.
An ordinary artisan would have been motivated to use the known technique of Nakashiba-434 in the manner set forth above to produce the predictable result as stated above in claim 3.
Regarding claim 12, Omori as modified by Yeon, Tiemeijer, and Nakashiba-434, teaches claim 11 from which claim 12 depends. Omori, Tiemeijer, and Nakashiba-434 do not expressly disclose the limitations of claim 12.
However, in an analogous art, Yeon teaches
(Original) The semiconductor device of claim 11, wherein the connection
pad (116 – Fig. 1 – [0038] – “the connection pads 116”) and the connection pad connected redistribution line (117 – Fig. 1 – [0038] – “the passive element pattern 117” – this is interpreted as the connection pad connected redistribution line) have the first thickness (116 – Fig. 1 – [0038] – “the passive element pattern 117 and the connection pads 116 may have a thickness of about 2 μm to about 5 μm” – this is interpreted as both elements having the same thickness).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection pad and redistribution line thickness structure as taught by Yeon into Omori, Tiemeijer, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Yeon in the manner set forth above to produce the predictable result as stated above in claim 2.
Regarding claim 13, Omori as modified by Yeon, Tiemeijer, and Nakashiba-434, teaches claim 11 from which claim 13 depends. Omori, Tiemeijer, and Nakashiba-434 do not expressly disclose the limitations of claim 13.
However, in an analogous art, Yeon teaches
(Currently Amended) The semiconductor device of claim 11, wherein the connection
pad (116), the connection pad connected redistribution line (117), and the plurality of inductor redistribution lines comprise [[the]] a same material (116 – [0037] – “the passive element pattern 117 may include substantially the same material as the connection pads 116”), and lower surfaces of the connection pad (116), the connection pad connected redistribution line (117), and the plurality of inductor redistribution lines (117a and 117b – Fig. 1 – {[0035] – “passive element pattern 117 may include a first plate-type conductive pattern 117a”}, {[0036] – “passive element pattern 117 may include a spiral conductive pattern 117b”) – these is interpreted as inductor redistribution line) are in contact with an upper surface of the redistribution insulating layer (114b).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection pad and redistribution line material and position as taught by Yeon into Omori, Tiemeijer, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Yeon in the manner set forth above to produce the predictable result of decreased manufacturing costs due to less materials and less procedures.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 14, Omori as modified by Yeon, Tiemeijer, and Nakashiba-434, teaches claim 11 from which claim 14 depends. Omori further teaches
(Original) The semiconductor device of claim 11, further comprising a
protective layer (PID – Fig. 1 – [0058] – “polyimide film PID is formed to cover the redistribution portion CRL”) arranged to cover the plurality of inductor redistribution lines (CPHs), the connection pad connected redistribution line (CPH – Fig. 1 – [0058] – “redistribution line CPH”), and the redistribution via (PVH), on the redistribution insulating layer (PVF), and wherein the connection pad (MPD) is not covered by the protective layer (PID – [0058] – “opening PHP for exposing the pad portion MPD is formed in the polyimide film PID” – Fig. 1 shows this).
Regarding claim 17, Omori as modified by Yeon, Tiemeijer, and Nakashiba-434, teaches claim 11 from which claim 17 depends. Omori, Tiemeijer, and Nakashiba-434 do not expressly disclose the limitations of claim 13.
However, in an analogous art, Yeon teaches
(Original) The semiconductor device of claim 11, wherein the circuit
element (111 – [0018] – “semiconductor device 111”) includes dynamic random access memory (DRAM) ([0018] – “semiconductor device 111 may be a logic semiconductor device, such as a central processing unit (CPU) and/or an application processor (AP), or a memory semiconductor device, such as dynamic random access memory (DRAM) and/or magnetic RAM (MRAM)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the DRAM as taught by Yeon into Omori, Tiemeijer, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Yeon in the manner set forth above to produce the predictable result of [0003] – “semiconductor devices having high memory capacities and thin, lightweight semiconductor packages including such semiconductor devices.”
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Yeon, Tiemeijer, Nakashiba-434, and Bedair.
Regarding claim 15, Omori as modified by Yeon, Tiemeijer, Nakashiba-434, teaches claim 11 from which claim 15 depends. Omori, Yeon, Tiemeijer, and Nakashiba-434 do not expressly disclose the limitations of claim 15.
However, in an analogous art, Bedair teaches
(Original) The semiconductor device of claim 11, wherein the inductor
redistribution line includes at least two inductor line patterns that extend in parallel to each other (Fig. 5D shows this – [0099] – “integrated passive devices 100, 100A, 110 and 110A (shown in FIGS. 5A through 5F) includes multiple capillary channels (e.g., capillary channel 115 and capillary channel 120), which yields a higher capacitance per unit area than a single channel design” – capillary channels are interpreted as inductor redistribution lines).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor structures as taught by Bedair into Omori, Yeon, Tiemeijer, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Bedair in the manner set forth above to produce the predictable result as indicated above in claim 5.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Yeon, Tiemeijer, Nakashiba-434, and Kim et al. (US 20210066305 A1 – hereinafter Kim).
Regarding claim 16, Omori as modified by Yeon, Tiemeijer, Nakashiba-434, teaches claim 11 from which claim 16 depends. Omori further teaches
connection pad connected redistribution line (CRL).
Omori, Yeon, and Tiemeijer do not expressly disclose the other limitations of claim 16.
However, in an analogous art, Nakashiba-434 teaches
a first inductor redistribution line (IND2) of the plurality of inductor redistribution lines (IND1 and IND2).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor redistribution lines structures as taught by Nakashiba-434 into Omori, Yeon, and Tiemeijer.
An ordinary artisan would have been motivated to use the known technique of Nakashiba-434 in the manner set forth above to produce the predictable result as stated above in claim 3.
Omori, Yeon, Tiemeijer, and Nakashiba-434 do not expressly disclose the other limitations of claim 16.
However, in an analogous art, Kim teaches
(Original) The semiconductor device of claim 11, wherein each of the
connection pad (160 – Fig. 17B – [0096] – “the first contact 160 and the pass conductive layer 165a may have a triple layer structure”), the connection pad connected redistribution line, and a first inductor redistribution line (165a – Fig. 17B – [0096] – “the first contact 160 and the pass conductive layer 165a may have a triple layer structure”) of the plurality of inductor redistribution lines (RDLI) has a stacked structure (160 – Fig. 17B – [0096] – “the first contact 160 and the pass conductive layer 165a may have a triple layer structure”) of at least two sub-conductive patterns ([0096] – “The pass conductive layer 165a is not limited thereto, and may include three or more conductive layers” – this is interpreted as having at least two sub-conductive patterns) with an interface therebetween (an interface is a boundary where sub-conductive patterns meet, therefore Kim conductive layers have an interface) .
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the stacked structure as taught by Kim into Omori, Yeon, Tiemeijer, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0004] – “a semiconductor device with reduced misalignment between contacts and an active region, and a manufacturing method of the same.”
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Bhagavat, Tiemeijer, Yeon, Nakashiba-434, and Kim.
Regarding independent claim 18, Omori teaches:
(Currently Amended) A semiconductor device ([0002] – “present
invention relates to semiconductor devices” – hereinafter ‘SCD’) comprising:
a substrate (SUB – Fig. 1 – [0051 – “substrate SUB”) having an active region;
a word line provided in the substrate;
an element layer (Fig. 1 annotated, see below – hereinafter ‘FEOL’) provided
on the substrate and including a bit line connected to the active region through a direct contact, and a capacitor structure electrically connected to the active region through a buried contact and a landing pad;
a wiring layer (Fig. 1 annotated, see below – hereinafter ‘BEOL’) provided on the element layer (FEOL), and including an inter-wiring insulating layer (IL3 – Fig. 1 – [0053] – “interlayer insulating film IL3”), a lower wiring line (ML2 – Fig. 1 – [0052] – “wirings ML2”) and an upper wiring line (ML3 – Fig. 1 – [0053] – “wirings ML3”) respectively on a lower surface and an upper surface of the inter-wiring insulating layer (IL3 – fig. 1 shows this), and a wiring via (VA2 – Fig. 1 – [0053] – “Vias VA2 are formed to pass through the interlayer insulating film IL3”) passing through the inter-wiring insulating layer (IL3) to electrically connect the lower wiring line (ML2) to the upper wiring line (ML3 – Fig. 1 shows this);
a redistribution layer (Fig. 1 annotated, see below – hereinafter ‘RDL’) including a redistribution insulating layer (PVF – Fig. 1 – [0060] – “passivation film PVF is formed of a silicon nitride film”) and a redistribution conductive layer (MBR – Fig. 1 – [0054] – “metal film MBR”) on the wiring layer (ML3); and
a protective layer (PID – Fig. 1 – [0058] – “polyimide film PID is formed to cover the redistribution portion CRL”) covering part of the redistribution conductive layer (MBR) on the redistribution insulating layer (PVF),
wherein the redistribution conductive layer (MBR) has a planar coil shape on the redistribution insulating layer (PVF) and includes a plurality of inductor redistribution lines (CPH – Fig. 18 – [0057] – “redistribution line CPH”) each constituting an inductor structure (elements PVF, CPH, and MBR constitute an inductor structure), a connection pad (MPD – Fig. 1 – [0058] – “pad portion MPD is formed to be in contact with an upper surface of the copper redistribution line CPH”) connected to a connection pad connected redistribution line (CRL – Fig. 1 – [0057] – “redistribution portion CRL”) on the redistribution insulating layer (PVF), and a redistribution via (PVH – Fig. 1 – [0054] – “passivation film PVF is provided with an opening PVH communicating with the third wiring ML3”) passing through the redistribution insulating layer (PVF) and electrically connected to the upper wiring line (ML3) and connected to the connection pad connected redistribution line (CRL) or one of the inductor redistribution lines (CPH),
the plurality of inductor redistribution lines include a first inductor redistribution line having a first thickness, a second inductor redistribution line having a second thickness that is less than the first thickness, and a third inductor redistribution line having a third thickness that is less than the second thickness, wherein the first inductor redistribution line, the second inductor redistribution line, and the third inductor redistribution line are in a same redistribution conductive layer as each other, and
the connection pad connected redistribution line and the connection pad have the first thickness.
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Omori does not expressly disclose the other limitations of claim 18.
However, in an analogous art, Bhagavat teaches
a third inductor redistribution line (160 – Fig. 1 – [8:56-58] – “inductor 155, but will be illustrative of the construction of the other inductors 150 and 160 as well”) having a third thickness that is less than the second thickness ([8:7-16] – “It should be understood that the number of traces and pillars that make up the inductor 155 and disclosed alternatives can be varied. Indeed, it should be noted that the structures that make up a given inductor, such as the inductor 155 or any disclosed alternatives, can be constructed to deliver a desired inductance. For example, the widths, thicknesses, spacings, numbers and material compositions of the conductor traces 165a, 165b, 165c, 165d, 165e, 165f and 165g and the pillars 205b, 205c, 205d, 205e, 205f, 205g and 205h can be selected to yield a desired inductance” – this is interpreted that the thickness of 205 elements can vary in different inductors 150 or 155).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor and redistribution line structure as taught by Bhagavat into Omori.
An ordinary artisan would have been motivated to use the known technique of Bhagavat in the manner set forth above to produce the predictable result as stated above in claim 1.
Omori, and Bhagavat do not expressly disclose the other limitations of claim 18.
However, in an analogous art, Tiemeijer teaches
wherein the redistribution conductive layer has a planar coil shape (tie (Fig. 10 shows the coil shape and Fig. 11 shows the planar configuration).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor shape structure as taught by Tiemeijer into Omori, and Bhagavat.
An ordinary artisan would have been motivated to use the known technique of Tiemeijer in the manner set forth above to produce the predictable result as stated above in claim 1.
Omori, Bhagavat, and Tiemeijer do not expressly disclose the limitations of claim 18.
However, in an analogous art, Yeon teaches
the connection pad connected redistribution line (117 – Fig. 1 – [0038] – “the passive element pattern 117” – this is interpreted as the connection pad connected redistribution line) and the connection pad (116 – Fig. 1 – [0038] – “the connection pads 116”) have the first thickness (116 – Fig. 1 – [0038] – “the passive element pattern 117 and the connection pads 116 may have a thickness of about 2 μm to about 5 μm” – this is interpreted as both elements having the same thickness).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the thickness of the connection pad structure as taught by Yeon into Omori, Bhagavat, and Tiemeijer.
An ordinary artisan would have been motivated to use the known technique of Yeon in the manner set forth above to produce the predictable result as stated above in claim 2.
Omori, Bhagavat, Tiemeijer, and Yeon do not expressly disclose the limitations of claim 18.
However, in an analogous art, Nakashiba-434 teaches
the plurality of inductor redistribution lines ({IND1 – Fig. 2 – [0065] – “inductor IND1”}, {IND2 – Fig. 2 – [0065] – “inductor IND2”} – this is a plurality) include a first inductor redistribution line (IND2) having a first thickness, a second inductor redistribution line (IND1) having a second thickness that is less than the first thickness ([0065] – “A thickness of the second inductor IND2 may be greater than or equal to a thickness of the first inductor IND1”),
wherein the first inductor redistribution line (IND2), the second inductor redistribution line (IND1), and the third inductor redistribution line are in a same redistribution conductive layer as each other ([0065] – “The second inductor IND2 may be formed in the same layer as the first inductor IND1” – a third inductor can be added by design choice).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the plurality of inductor structures as taught by Nakashiba-434 into Omori, Bhagavat, Tiemeijer, and Yeon.
An ordinary artisan would have been motivated to use the known technique of Nakashiba-434 in the manner set forth above to produce the predictable result as stated above in claim 3.
Omori, Bhagavat, Tiemeijer, Yeon, and Nakashiba-434 do not expressly disclose the limitations of claim 18.
However, in an analogous art, Kim teaches
an active region
(ACT – Fig. 1A – [0016] – “active regions ACT”);
a word line (130 – Fig. 1A – [0021] – “word lines 130”) provided in the
substrate (101 – Fig. 1B – [0021] – “word line 130 may be arranged at equal intervals in the second direction (y direction) and may be formed in a structure buried in the substrate 101”);
an element layer provided on the substrate (101) and including a bit line (170
– Fig. 1A – [0024] – “bit lines 170”) connected to the active region (ACT – [0026] – “first contact 160 electrically connecting the bit line 170 to the active region ACT” – Fig. 1A shows this) through a direct contact (160 – fig. 1A – [0026] – “first contact 160”), and a capacitor structure electrically connected to the active region ([0027] – “the second contact 180 may be a contact connecting a capacitor (not illustrated) to the active region ACT”) through a buried contact (180 – Fig. 1A – “the second contact 180”) and a landing pad (190 – Fig. 1A – [0031] – “landing pad 190”);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the active region structure as taught by Kim into Omori, Bhagavat, Tiemeijer, Yeon, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result as stated above in claim 16.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Bhagavat, Tiemeijer, Yeon, Nakashiba-434, Kim, and Bedair.
Regarding claim 19, Omori as modified by Bhagavat, Tiemeijer, Yeon, Nakashiba-434, and Kim, teaches claim 18 from which claim 19 depends. Omori, Bhagavat, Tiemeijer, Yeon, Nakashiba-434, and Kim do not expressly disclose the limitations of claim 19.
However, in an analogous art, Bedair teaches
(Previously Presented) The semiconductor device of claim 18, wherein the
inductor structures (Fig. 1 – [0096] – “plurality of passive devices 95” – this is a plurality of inductor structures) include a first inductor structure having the first inductor redistribution line, a second inductor structure having the second inductor redistribution line, and a third inductor structure having the third inductor redistribution line (20 – Fig. 1 – [0087] – “As shown in FIG. 1, integrated passive device 1 includes a target well 10 and a capillary channel 20” – this is interpreted as a redistribution line, each inductor structure has its associated redistribution line),
the first inductor redistribution line, the second inductor redistribution line, and the third inductor redistribution line have a same width ([0088] – “A variety of capillary channel (20, 20A-F) lengths and widths may be fabricated using this structure” – it is a design choice to have the same widths for these elements), and
the third inductor structure has greater inductance than the second inductor structure, and the second inductor structure has greater inductance than the first inductor structure ([0100] – “larger inductance values may be achieved with a larger number of turns” – it is be design choice on the inductance size of each inductor structure).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inductor and redistribution line structures as taught by Bedair into Omori, Yeon, Tiemeijer, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Bedair in the manner set forth above to produce the predictable result as indicated above in claim 5.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to design the width and inductance of the inductor structures to achieve the desired results. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with inductor structures having different widths resulting in different inductance values. Bedair teaches that inductor redistribution lines can vary in width and therefore vary inductance values for their specific inductor structure. Therefore it would be a design choice to select widths of the inductor redistribution lines to achieve the desired inductance for that structure.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Omori in view of Bhagavat, Tiemeijer, Yeon, Nakashiba-434, Kim, Bedair, and Naser et al. (US 20210098370 A1 – hereinafter Naser).
Regarding claim 20, Omori as modified by Bhagavat, Tiemeijer, Yeon, Nakashiba-434, Kim, and Bedair, teaches claim 19 from which claim 20 depends. Omori, Bhagavat, Tiemeijer, Yeon, Nakashiba-434, and Kim do not expressly disclose the limitations of claim 20.
However, in an analogous art, Bedair teaches
(Original) The semiconductor device of claim 19, wherein the first inductor
structure (95D – Fig. 3 – [0097] – “power inductor 95D”), the second inductor structure, and the third inductor structure comprise power inductors (bed (95D – Fig. 3 – [0097] – “power inductor 95D” – there is a plurality of inductor structures so it is by design choice to have three power inductors).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power inductors as taught by Bedair into Omori, Yeon, Tiemeijer, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Bedair in the manner set forth above to produce the predictable result as indicated above in claim 5.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to design the device with three power inductors. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with different variety of power inductors. Bedair teaches that a device can have various types of inductors in any combination. Therefore it would be a design choice to select power inductors to achieve the desired device.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Omori, Bhagavat, Tiemeijer, Yeon, Nakashiba-434, Kim, and Bedair do not expressly disclose the limitations of claim 20.
However, in an analogous art, Naser teaches
power inductors operating in response to different operating voltages from each other ([0020] – "inductors 100 may have one or more of a different width of an inductor coil or line (e.g., line 101), a different spacing of inductor coils or lines (e.g., spacing between line 101 in inductor 100), a different line thickness, a different number of spirals or coils, a different outer dimension (a2), or a different inner dimension (a1) where the different size of inductor 100 creates a different inductance” – operating voltage is directly proportional to inductance by the V = L x (di/dt) where V – voltage, L – inductance, and (di/dt) – the rate of change of current through the inductor, therefore it is be design choice for the different inductors to operate in response to different operating voltages.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power inductors as taught by Naser into Omori, Yeon, Tiemeijer, and Nakashiba-434.
An ordinary artisan would have been motivated to use the known technique of Naser in the manner set forth above to produce the predictable result [0002] – “to fit more semiconductor devices and circuits on semiconductor wafers.”
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to design the device with three power inductors operating in response to different operating voltages. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with different variety of power inductors. Naser teaches that an inductor operating power is directly related to the inductance. Therefore it would be a design choice to select power inductors to achieve the desired inductance.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Pertinent Art
For the benefits of the Applicant, US 5556814 A is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including “stacked structure”.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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