DETAILED ACTIONS
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendments/arguments submitted by the Applicant(s) on 12/08/2025.
Status of the Claims
Claims 1-3, 5-6,8-9, 11-14,16, and 18-20 are pending.
Claims 1, 5-6, and 14 are amended.
Claims 4,7,10, 15, and 17 are canceled.
Response to Arguments
Rejections Under 35 U.S.C. 102(a)(1)
Applicant’s Argument:
Applicant argues in the remarks, pages 9-11, filed 12/08/2025, with respect to the rejection(s) of Claim 1 under 35 U.S.C. 102(a)(1) that
“In one or more non-limiting implementations of the present application, the daughter board further comprises a plurality of second ports, the power detecting circuit board is connected to other power detecting circuit boards through plurality of the second ports, which can achieve the running data collection and transmission among the power detecting circuit boards. In addition, the motherboard further comprises a first port, the power detecting circuit board is connected to a remote management platform through the first port, the power detecting circuit board is configured to transmit the running data of the at least one PSU to the remote management platform to achieve out of band management, the first port can connect an external element, the remote management platform, which is out of the power detecting circuit board, then the power
detecting circuit board can transmit the running data of the at least one PSU out of the power detecting circuit board to achieve out of band management of the power detecting circuit board.
BRASSAC fails to disclose or teach the modules 1, 2, 3 comprising any specific structures to connect and output to an external element outside the server 100 to exchange information and allow synchronization signals, nor disclose any out of band management of the modules 1, 2, 3 of the servers 100. See currently amended independent claim 1 which recites features similar to those in the example implementations. Additionally, the daughter board is overlapped with the
motherboard. See currently amended independent claim 1 which recites features similar to those in the example implementations.
Since the modules 1, 2, 3 in BRASSAC do not have any structural description, BRASSAC fails to disclose or teach the overlapped arrangement of the daughter board and the motherboard in amended claim 1. Thus, BRASSAC fails to disclose the features, including the above-discussed features of amended claim 1.
Xiao is cited in the Office action for other features, therefore, Xiao, cannot cure the deficiencies of BRASSAC. Therefore, Applicant respectfully submits that BRASSAC and Xiao, alone or in any combinations thereof, do not teach or suggest the above-discussed features of amended claim 1. Therefore, amended independent claim 1 is patentable distinguishable over these references.”
Examiner’s response:
Applicant’s arguments see remarks pages 9-11, filed 12/08/2025, with respect to the rejection(s) of Claim 1 under 35 U.S.C. 102(a)(1) have been fully considered, and are not persuasive.
BRASSAC teaches in ([0006]) an intelligent platform management interface (IPMI) offers a set of interface specifications for managing, supervising and controlling the physical status of certain components or electronic hardware present in computer equipment. The IMPI interface connects the computer elements (hardware) with a remote management/ administrating system. The IPMI standard makes it possible to monitor a server. The functions of IPMI can generally be activated by a basic input/output system called BIOS (basic input/output system) or by management software furnished by the manufacturer of the equipment. Thus, if needed, for example when an alert associated with an event is issued ( e.g.overheating) of a piece of equipment, the network administrator can, via an appropriate graphic interface and from the same location (e.g., on a local or remote machine), electrically turn off the equipment concerned, restart it, reinitialize its parameters if necessary, or turn on an alternate piece of equipment.
BRASSAC also teaches structure of the modules 1, 2, 3 comprising all the computer system and interfaces. BRASSAC teaches structure comprising all the computer elements and a communication interface. In [0022] teaches a satellite management controller (SMC)component of the system measuring parameters of its module and managing module functions. See paragraph of the in Figure 1, [0015]-[0022], [0022] a satellite management controller (SMC) component of the system capable of measuring the physical parameters of its module and managing the local functions of said module;” and see [0051]-[0067], [0051] Advantageously, each of the modules 1, 2, 3 is identical and comprises the following elements: [0052] one or more processors (CPU) (Central Processing Unit) 10, 11, 20, 21. In the example illustrated, each module 1, 2 is bi-socket, that is, it supports respectively two processors (CPU) 10, 11, 20, 21. Advantageously, the processors (CPU) 10, 11, 20, 21 of the same module 1, 2, 3 are interconnected to each other via a QPI (QuickPath Interconnect) link 101, 201; [0053] a system on a chip (SOC) (…)[0067] managing one or more SMC components 15, 25, for example the supervision of their statuses, reception of measurements or any other data from the SMC components 15, 25, or the transmission of control messages (control) to the SMC components 15, 25”
BRASSAC also teaches that the server consists of plurality of subsystems/ modules such as motherboard and daughterboard. Each of these modules consists of CPU, communication interfaces. Therefore, bother motherboard and daughter card can be connected to remote management system. This is a design choice. see in [0050] “FIG. 1 is an embodiment of a server 100 comprising a plurality of modules 1, 2, 3, three in this example, such as motherboards or printed circuit cards”).
Therefore, applicant argument is not persuasive. The rejections are maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by BRASSAC et al. (US 2016/0062936 A1, hereinafter Brassac).
Regarding Claim 1, Brassac teaches,
A power detecting circuit board electrically connected to at least one power supply unit (PSU),(Brassac, Figure 2,) the at least one PSU (Brassac,[0025], the interconnection unit is electrically powered by the modules, each module comprising at least two power supply units (PSU)), configured to convert alternating current of an electric supply provided by a power distribution system into direct current, to provide power supply for at least one corresponding server, (Brassac, [0075],each module 1, 2, 3 comprises at least two power supply units (PSU), which, by way of example, can be in the form of AC/DC (alternating current/direct current) converters, delivering an input power for each module 1, 2, 3),
the power detecting circuit board configured to detect running data of the at least one PSU; ([0075], The interconnection unit 30 is electrically powered by the modules 1, 2, 3, each sending through Ethernet links of the interconnection 28 a current at a predefined voltage, for example 12 V. Said currents are then added together by an appropriate electronic device that is part of the interconnection unit 30”)
the power detecting circuit board comprising: a motherboard comprising a first connector (Brassac, [0050] Represented in FIG. 1 is an embodiment of a server 100 comprising a plurality of modules 1, 2, 3, three in this example, such as motherboards or printed circuit cards); and
a daughter board overlapped with the motherboard, the daughter board comprising a second connector, the second connector electrically connected to the first connector. (Brassac, [0004] For physical reasons, an SMP server having a large number of sockets must then be divided into several subsystems. These subsystems can, by way of example, be produced by daughter cards connected to a motherboard, blades connected to a backplane distributing the power and signals from the buses, or self-powered modules with voltage and current from the mains. This is referred to as a multi-module SMP server”).
wherein the motherboard further comprises a first port, the power detecting circuit board is connected to a remote management platform through the first port, ((Brassac [006],” the intelligent platform management interface (IPMI) offers a set of interface specifications for managing, i.e., supervising and controlling, the physical status of certain components or electronic hardware present in computer equipment (or elements). the IPMI standard makes it possible to monitor in a server the regulation of temperature, voltage, power supply of microprocessors voltage, power supply of microprocessors, their proper powering up, the humidity level of the components, or the speed of the cooling fans”.
the power detecting circuit board is configured to transmit the running data of the at least one PSU to the remote management platform to achieve out of band management; ((Brassac, [0006] All functions of the IPMI can generally be
activated by a basic input/output system called BIOS (basic input/output system) or by management software furnished by the manufacturer of the equipment. if needed, for example when an alert associated with an event is issued ( e.g.,
overheating) of a piece of equipment, the network administrator can, via an appropriate graphic interface and from the same location (e.g., on a local or remote machine), electrically tum off the equipment concerned, restart it, reinitialize its parameters if necessary, or turn on an alternate piece of
equipment”).the daughter board further comprises a plurality of second ports, the power detecting circuit board is connected to other power detecting circuit boards through plurality of the second ports. (Brassac, The interconnection unit 30 is electrically powered by the modules 1, 2, 3, each sending through Ethernet links of the interconnection 28 a current at a predefined voltage, for example 12 V. Said currents are then added together by an appropriate electronic device that is part
of the interconnection unit 30”).
Regarding Claim 2, Brassac teaches the power detecting circuit board of claim 1, Brassac further teaches wherein the first connector comprises a first pin, the second connector comprises a second pin; ((Brassac, Figure 1-2,[0058] the interconnection 27 enables the communication elements 16, 26 such as BCS2 pertaining to the modules 1, 2, 3 to exchange information, thus ensuring memory coherence of all of the modules 1, 2, 3. The interconnection 27 via the XQPI network also allows synchronization signals to be carried between each module 1, 2, 3, such as clock signals, the synchronization of which is managed by the FPGAs 13, 23”) the first pin is connected to a power source through a first resistor, the second pin is grounded through a second resistor, the first pin and the second pin are switchable to be connected or disconnected (Brassac, [0061] In one embodiment, the interconnection 27 of the communication elements 16, 26 and the interconnection 28 of the SOCs 12, 22 are accomplished via an interconnection unit 30, illustrated in FIG. 2 and described hereinafter. By way of example, the interconnection unit 30 is a backplane, comprising a network switch [0076], “all of the Ethernet links made via the interconnection 27 of the modules 1, 2, 3 cooperate so as to furnish redundant electrical power to the switch of the interconnection unit 30, only said switch comprising active components”).
Regarding Claim 3, Brassac teaches the power detecting circuit board of claim 2, Brassac further teaches wherein the first connector further comprises a plurality of third pins; the second connector further comprises a plurality of fourth pins, the plurality of third pins of the first connector and the plurality of fourth pins of the second connector are correspondingly connected one-to-one. (Brassac, Figure 1-2, [0072]
advantage the interconnection unit 30 is produced based on the topology chosen. For example, in the case of a server 100 with N modules, for an all-to-all topology, each interconnection port of a module 1, 2, 3 must support N-1 high-speed links going to each of its neighbors. If, in a configuration of eight modules, where N=8, each module 1, 2, 3 comprises seven links to eight unidirectional channels, the interconnection unit 30 is then created so as to support 8*7*8, or 448 unidirectional high-speed channels”).
Regarding Claim 5, Brassac teaches the power detecting circuit board of claim 2, Brassac further teaches, wherein the motherboard further comprises a baseboard management controller (BMC) (Brassac, 0007] For the hardware, the supervision of the physical status of the components or electronic hardware is currently provided by a baseboard management controller (BMC), implemented on the motherboard, or on the main card of the hardware to be supervised. For example, for a server, the functions of the BMC are performed by the integration on the
server's motherboard of a system on a chip (SOC), on which firmware is executed, implementing the IPMI standard”), the BMC comprises a General-purpose input/output (GPIO) port, the GPIO port is connected to the first pin of the first connector and configured to detect a level status of the first pin. (Brassac, Figure 1-2, [0065], The BMC components 14, 24 of each of the modules 1, 2, 3 are therefore capable of exchanging information among them, the pooling of their functions and information enabling the server 100, from the point of view of an external hardware management application, to be a single-module server 100. Thus, each BMC component 14, 24 is programmed to manage the high-level functions, i.e., central functions, of the server 100,”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8-9, 11-14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over BRASSAC et al. (US 2016/0062936 A1, hereinafter Brassac and in view of Xiao Shasha (CN 113867514 A, hereinafter Xiao)
Regarding Claim 6, Brassac teaches,
the power detecting system comprising:
a plurality of power detecting circuit boards connected to each other (Brassac, Figure 1-2, [0050] Represented in FIG. 1 is an embodiment of a server 100 comprising a plurality of modules 1, 2, 3, three in this example, such as motherboards or printed circuit ) , each of the plurality of power detecting circuit boards electrically connected to at least one power supply unit (PSU) (Brassac,[0025], the interconnection unit is electrically powered by the modules, each module comprising at least two power supply units (PSU)), ,
the at least one PSU configured to convert alternating current of an electric supply provided by a power distribution system into direct current, to provide power supply for at least one corresponding server (Brassac, [0075], each module 1, 2, 3 comprises at least two power supply units (PSU), which, by way of example, can be in the form of AC/DC (alternating current/direct current) converters, delivering an input power for each module 1, 2, 3);
each of the plurality of power detecting circuit boards comprising:
a motherboard comprising a first connector (Brassac, [0050] Represented in FIG. 1 is an embodiment of a server 100 comprising a plurality of modules 1, 2, 3, three in this example, such as motherboards or printed circuit cards); and a daughter board overlapped with the motherboard, the daughter board comprising a second connector, the second connector electrically connected to the first connector (Brassac, [0004] For physical reasons, an SMP server having a large number of sockets must then be divided into several subsystems. These subsystems can, by way of example, be produced by daughter cards connected to a motherboard, blades connected to a backplane distributing the power and signals from the buses, or self-powered modules with voltage and current from the mains. This is referred to as a multi-module SMP server”);
one of the plurality of power detecting circuit boards serving as a leader detecting circuit board in the power detecting system, rest of the plurality of power detecting circuit boards serving as follower detecting circuit boards in the power detecting system (Brassac, [0034] Advantageously, in said server, each BMC component is programmed to: [0035] identify in a set or subset of modules whether it belongs to a master or slave module, based on identification information from each of the modules of said set or subset”);;
wherein the leader detecting circuit board is configured to obtain running data of the at least one PSU corresponding to the leader detecting circuit board; and each of the follower detecting circuit boards is configured to obtain running data of the at least one PSU corresponding to each of the follower detecting circuit boards (Brassac, ;
wherein the leader detecting circuit board is further configured to obtain the running data of the at least one PSU corresponding to the follower detecting circuit boards, and summarize the running data of the at least one PSU corresponding to the leader detecting circuit board and the running data of the at least one PSU corresponding to the follower detecting circuit boards. (Brassac, [0036]” if it belongs to a master module, configure its FPGA in such a way that the FPGA distributes the clock
signal from the master module to the slave modules of the same set or subset;
[0037] if it belongs to a slave module, configure its FPGA in such a way that the FPGA deactivates the clock signal from the slave module. [0038] Advantageously, in said server, each processor (CPU) of each module comprises time stamp counters (TSC) capable of synchronizing tasks involving a plurality of threads, the synchronization of all of the time stamp counters (TSC) of said processors (CPU) in a set or subset of modules being accomplished by: [0039] the sending of a notification, by each BMC component of each slave module of said set or subset, to the BMC of the master module when the slave module leaves an initialization or reinitialization phase; [0040] a notification to the BMC of the master module when the master module leaves an initialization or reinitialization
phase “)
wherein the motherboard of each of the plurality of power detecting circuit boards further comprises a first port ((Brassac [006],” the intelligent platform management interface (IPMI) offers a set of interface specifications for managing, i.e., supervising and controlling, the physical status of certain components or electronic hardware present in computer equipment (or elements). the IPMI standard makes it possible to monitor in a server the regulation of temperature, voltage, power supply of microprocessors voltage, power supply of microprocessors, their proper powering up, the humidity level of the components, or the speed of the cooling fans”.
the plurality of power detecting circuit boards is connected to the remote management platform through the first port, the plurality of power detecting circuit boards is configured to transmit the summarized of the running data of the at least one PSU corresponding to the leader detecting circuit board and the running data of the at least one PSU corresponding to the follower detecting circuit boards to the remote management platform to achieve out of band management ((Brassac, [0006] All functions of the IPMI can generally be activated by a basic input/output system called BIOS (basic input/output system) or by management software furnished by the manufacturer of the equipment. if needed, for example when an alert associated with an event is issued ( e.g.,overheating) of a piece of equipment, the network administrator can, via an appropriate graphic interface and from the same location (e.g., on a local or remote machine), electrically tum off the equipment concerned, restart it, reinitialize its parameters if necessary, or turn on an alternate piece of
equipment”). the daughter board of each of the plurality of power detecting circuit boards further comprises a plurality of second port, the leader detecting circuit board is connected to the follower detecting circuit boards through the plurality of second ports of each of the leader detecting circuit board and the follower detecting circuit boards. (Brassac, The interconnection unit 30 is electrically powered by the modules 1, 2, 3, each sending through Ethernet links of the interconnection 28 a current at a predefined voltage, for example 12 V. Said currents are then added together by an appropriate electronic device that is part of the interconnection unit 30”).
Brassac is silent on A power detecting system applied in a liquid cooling tank.
However, Xiao teaches a power detecting system applied in a liquid cooling tank (Xiao, Page 2, top paragraph, “an embodiment of the present application provides a method for centralized power supply management of an immersed
liquid-cooled Tank, where each power supply rack Powershelf of the immersed liquid-cooled Tank corresponds to one management board”).
It would have been obvious to a person of ordinary skill before the effective filing date to modify Brassac in view of Xiao to apply the power detection system of server into a cool tank as taught by Xiao, with the benefit of monitoring the centralized management of all power supplies in the immersed liquid cooling Tank and detect the power supply fault location accurately, and reduce the power supply redundancy design cost, and improve the usability and maintainability of the product. (Xiao, Page 3, middle paragraph).
Regarding Claim 8, combination of Brassac and Xiao teaches the power detecting system of claim 6,
Brassac further teaches wherein the first connector comprises a first pin, the second connector comprises a second pin; ((Brassac, Figure 1-2,[0058] the interconnection 27 enables the communication elements 16, 26 such as BCS2 pertaining to the modules 1, 2, 3 to exchange information, thus ensuring memory coherence of all of the modules 1, 2, 3. The interconnection 27 via the XQPI network also allows synchronization signals to be carried between each module 1, 2, 3, such as clock signals, the synchronization of which is managed by the FPGAs 13, 23”) the first pin is connected to a power source through a first resistor, the second pin is grounded through a second resistor, the first pin and the second pin are switchable to be connected or disconnected (Brassac, [0061] In one embodiment, the interconnection 27 of the communication elements 16, 26 and the interconnection 28 of the SOCs 12, 22 are accomplished via an interconnection unit 30, illustrated in FIG. 2 and described hereinafter. By way of example, the interconnection unit 30 is a backplane, comprising a network switch [0076], “all of the Ethernet links made via the interconnection 27 of the modules 1, 2, 3 cooperate so as to furnish redundant electrical power to the switch of the interconnection unit 30, only said switch comprising active components”).
Regarding Claim 9, combination of Brassac and Xiao teaches the power detecting system of claim 8,
Brassac further teaches wherein: in the leader detecting circuit board, the first pin and the second pin are disconnected; in each of the follower detecting circuit boards, the first pin and the second pin are connected. (Brassac, [0036]” if it belongs to a master module, configure its FPGA in such a way that the FPGA distributes the clock signal from the master module to the slave modules of the same set or subset; [0037] if it belongs to a slave module, configure its FPGA in such a way that the FPGA deactivates the clock signal from the slave module. [0039] the sending of a notification, by each BMC component of each slave module of said set or subset, to the BMC of the master module when the slave module leaves an initialization or reinitialization phase; [0040] a notification to the BMC of the master module when the master module leaves an initialization or reinitialization phase”).
Regarding Claim 11, combination of Brassac and Xiao teaches the power detecting system of claim 8,
Brassac further teaches, wherein the motherboard further comprises a baseboard management controller (BMC) (Brassac, 0007] For the hardware, the supervision of the physical status of the components or electronic hardware is currently provided by a baseboard management controller (BMC), implemented on the motherboard, or on the main card of the hardware to be supervised. For example, for a server, the functions of the BMC are performed by the integration on the server's motherboard of a system on a chip (SOC), on which firmware is executed, implementing the IPMI standard”), the BMC comprises a General-purpose input/output (GPIO) port, the GPIO port is connected to the first pin of the first connector and configured to detect a level status of the first pin. (Brassac, Figure 1-2, [0065], The BMC components 14, 24 of each of the modules 1, 2, 3 are therefore capable of exchanging information among them, the pooling of their functions and information enabling the server 100, from the point of view of an external hardware management application, to be a single-module server 100. Thus, each BMC component 14, 24 is programmed to manage the high-level functions, i.e., central functions, of the server 100,”)
.
Regarding Claim 12, combination of Brassac and Xiao teaches the power detecting system of claim 11,
Brassac further teaches wherein when the level status of the first pin of the first connector connected to the GPIO port is a high-level status, the BMC determines the power detecting circuit board comprising the BMC is the leader detecting circuit board; when the level status of the first pin of the first connector connected to the GPIO port is a low-level status, the BMC determines the power detecting circuit board comprising the BMC is one of the follower detecting circuit board. (Brassac, Figure 1-2, [0065], The BMC components 14, 24 of each of the modules 1, 2, 3 are therefore capable of exchanging information among them, the pooling of their functions and information enabling the server 100, from the point of view of an external hardware management application, to be a single-module server 100. Thus, each BMC component 14, 24 is programmed to manage the high-level functions, i.e., central functions, of the server 100,”).
Regarding Claim 13, combination of Brassac and Xiao teaches the power detecting system of claim 12,
Brassac further teaches wherein when the BMC determines the power detecting circuit board comprising the BMC is the leader detecting circuit board, the BMC controls the leader detecting circuit board to detect the running data of the at least one PSU corresponding to the leader detecting circuit board(Brassac, [0034] Advantageously, in said server, each BMC component is programmed to: [0035] identify in a set or subset of modules whether it belongs to a master or slave module, based on identification information from each of the modules of said set or subset”); , and
polls the running data of the at least one PSU corresponding to the follower detecting circuit boards, to summarize the running data of the at least one PSU corresponding to the leader detecting circuit board and the running data of the at least one PSU corresponding to the follower detecting circuit boards; when the BMC determines the power detecting circuit board comprising the BMC is the follower detecting circuit board, the BMC controls the follower detecting circuit board to detect the running data of the at least one PSU corresponding to the follower detecting circuit board, and to transmit the detected running data of the at least one PSU to the leader detecting circuit board. (Brassac, [0036]” if it belongs to a master module, configure its FPGA in such a way that the FPGA distributes the clock signal from the master module to the slave modules of the same set or subset; [0037] if it belongs to a slave module, configure its FPGA in such a way that the FPGA deactivates the clock signal from the slave module. [0038] Advantageously, in said server, each processor (CPU) of each module comprises time stamp counters (TSC) capable of synchronizing tasks involving a plurality of threads, the synchronization of all of the time stamp counters (TSC) of said processors (CPU) in a set or subset of modules being accomplished by: [0039] the sending of a notification, by each BMC component of each slave module of said set or subset, to the BMC of the master module when the slave module leaves an initialization or reinitialization phase; [0040] a notification to the BMC of the master module when the master module leaves an initialization or reinitialization phase “).
Regarding Claim 14, Brassac teaches,
a plurality of power supply units (PSUs) configured to convert alternating current of an electric supply provided by a power distribution system into direct current, to provide power supply for at least one corresponding server( Brassac, [0075], each module 1, 2, 3 comprises at least two power supply units (PSU), which, by way of example, can be in the form of AC/DC (alternating current/direct current) converters, delivering an input power for each module 1, 2, 3); ; and
a power detecting system comprising: a plurality of power detecting circuit boards connected to each other, each of the plurality of power detecting circuit boards electrically connected to at least one of the plurality of PSUs(Brassac,[0025], the interconnection unit is electrically powered by the modules, each module comprising at least two power supply units (PSU)), Figure 1-2, [0050] Represented in FIG. 1 is an embodiment of a server 100 comprising a plurality of modules 1, 2, 3, three in this example, such as motherboards or printed circuit ) ;each of the plurality of power detecting circuit boards comprising: a motherboard comprising a first connector (Brassac, [0050] Represented in FIG. 1 is an embodiment of a server 100 comprising a plurality of modules 1, 2, 3, three in this example, such as motherboards or printed circuit cards);; and a daughter board overlapped with the motherboard, the daughter board comprising a second connector, the second connector electrically connected to the first connector(Brassac, [0004] For physical reasons, an SMP server having a large number of sockets must then be divided into several subsystems. These subsystems can, by way of example, be produced by daughter cards connected to a motherboard, blades connected to a backplane distributing the power and signals from the buses, or self-powered modules with voltage and current from the mains. This is referred to as a multi-module SMP server” . Figure 1-2,[0058] the interconnection 27 enables the communication elements 16, 26 such as BCS2 pertaining to the modules 1, 2, 3 to exchange information, thus ensuring memory coherence of all of the modules 1, 2, 3.);
; one of the plurality of power detecting circuit boards serving as a leader detecting circuit board in the power detecting system, rest of the plurality of power detecting circuit boards serving as follower detecting circuit boards in the power detecting system(Brassac, [0034] Advantageously, in said server, each BMC component is programmed to: [0035] identify in a set or subset of modules whether it belongs to a master or slave module, based on identification information from each of the modules of said set or subset”); ; the leader detecting circuit board is configured to obtain running data of the at least one PSU corresponding to the leader detecting circuit board;each of the follower detecting circuit boards is configured to obtain running data of the at least one PSU corresponding to each of the follower detecting circuit boards; and the leader detecting circuit board is further configured to obtain the running data of the at least one PSU corresponding to the follower detecting circuit boards, and summarize the running data of the at least one PSU corresponding to the leader detecting circuit board and the running data of the at least one PSU corresponding to the follower detecting circuit boards(Brassac, [0036]” if it belongs to a master module, configure its FPGA in such a way that the FPGA distributes the clock
signal from the master module to the slave modules of the same set or subset;
[0037] if it belongs to a slave module, configure its FPGA in such a way that the FPGA deactivates the clock signal from the slave module. [0038] Advantageously, in said server, each processor (CPU) of each module comprises time stamp counters (TSC) capable of synchronizing tasks involving a plurality of threads, the synchronization of all of the time stamp counters (TSC) of said processors (CPU) in a set or subset of modules being accomplished by: [0039] the sending of a notification, by each BMC component of each slave module of said set or subset, to the BMC of the master module when the slave module leaves an initialization or reinitialization phase; [0040] a notification to the BMC of the master module when the master module leaves an initialization or reinitialization
phase “).
wherein the motherboard of each of the plurality of power detecting circuit boards further comprises a first port ((Brassac [006],” the intelligent platform management interface (IPMI) offers a set of interface specifications for managing, i.e., supervising and controlling, the physical status of certain components or electronic hardware present in computer equipment (or elements). the IPMI standard makes it possible to monitor in a server the regulation of temperature, voltage, power supply of microprocessors voltage, power supply of microprocessors, their proper powering up, the humidity level of the components, or the speed of the cooling fans”.
the plurality of power detecting circuit boards is connected to the remote management platform through the first port, the plurality of power detecting circuit boards is configured to transmit the summarized of the running data of the at least one PSU corresponding to the leader detecting circuit board and the running data of the at least one PSU corresponding to the follower detecting circuit boards to the remote management platform to achieve out of band management ((Brassac, [0006] All functions of the IPMI can generally be activated by a basic input/output system called BIOS (basic input/output system) or by management software furnished by the manufacturer of the equipment. if needed, for example when an alert associated with an event is issued ( e.g.,overheating) of a piece of equipment, the network administrator can, via an appropriate graphic interface and from the same location (e.g., on a local or remote machine), electrically tum off the equipment concerned, restart it, reinitialize its parameters if necessary, or turn on an alternate piece of
equipment”). the daughter board of each of the plurality of power detecting circuit boards further comprises a plurality of second port, the leader detecting circuit board is connected to the follower detecting circuit boards through the plurality of second ports of each of the leader detecting circuit board and the follower detecting circuit boards. (Brassac, The interconnection unit 30 is electrically powered by the modules 1, 2, 3, each sending through Ethernet links of the interconnection 28 a current at a predefined voltage, for example 12 V. Said currents are then added together by an appropriate electronic device that is part of the interconnection unit 30”).
Brassac is silent on an immersed liquid cooling tank communicating with a power distribution system and a remote management platform,
However, Xiao teaches an immersed liquid cooling tank communicating with a power distribution system and a remote management platform ((Xiao, Page 2, top paragraph, “an embodiment of the present application provides a method for centralized power supply management of an immersed liquid-cooled Tank, where each power supply rack Powershelf of the immersed liquid-cooled Tank corresponds to one management board”).
It would have been obvious to a person of ordinary skill before the effective filing date to modify Brassac in view of Xiao to apply the power detection system of server into a cool tank as taught by Xiao, with the benefit of monitoring the centralized management of all power supplies in the immersed liquid cooling Tank and detect the power supply fault location accurately, and reduce the power supply redundancy design cost, and improve the usability and maintainability of the product. (Xiao, Page 3, middle paragraph).
Regarding Claim 16, combination of Brassac and Xiao teaches the immersed liquid cooling tank of claim 14,
Brassac further teaches wherein the first connector comprises a first pin, the second connector comprises a second pin, the first pin is connected to a power source through a first resistor, the second pin is grounded through a second resistor, the first pin and the second pin are switchable to be connected or disconnected; wherein in the leader detecting circuit board, the first pin and the second pin are disconnected;in each of the follower detecting circuit boards, the first pin and the second pin are connected Brassac, Figure 1-2, [0072] advantage the interconnection unit 30 is produced based on the topology chosen. For example, in the case of a server 100 with N modules, for an all-to-all topology, each interconnection port of a module 1, 2, 3 must support N-1 high-speed links going to each of its neighbors. If, in a configuration of eight modules, where N=8, each module 1, 2, 3 comprises seven links to eight unidirectional channels, the interconnection unit 30 is then created so as to support 8*7*8, or 448 unidirectional high-speed channels”).
Regarding Claim 18, combination of Brassac and Xiao teaches the immersed liquid cooling tank of claim 16,
Brassac further teaches, wherein the motherboard further comprises a baseboard management controller (BMC), the BMC comprises a General-purpose input/output (GPIO) port, the GPIO port is connected to the first pin of the first connector and configured to detect a level status of the first pin, to determine the power detecting circuit board comprising the BMC being the leader detecting circuit board or the follower detecting circuit board, and control a running of the power detecting circuit board according to the determined result. Brassac, Figure 1-2, [0024] “the interconnection of the communication elements and interconnection of the SOCs are accomplished by means of an interconnection unit, the interconnection unit comprising a network of programmable ports (FPGA). [0029] the determination by the BMC component of the address of its module and of the addresses of the modules to which it is interconnected, the determination of said addresses being performed based on the identifier (ID) received by the FPGA. [0030] Advantageously, in said server, the identifier (ID) sent by the FPGA of the interconnection unit is determined based on each physical connection location of each of the modules to the interconnection module”. [0050] Represented in FIG. 1 is an embodiment of a server 100 comprising a plurality of modules 1, 2, 3, three in this example, such as motherboards or printed circuit cards”);
Regarding Claim 19, combination of Brassac and Xiao teaches the immersed liquid cooling tank of claim 18,
Brassac further teaches, wherein when the level status of the first pin of the first connector connected to the GPIO port is a high-level status, the BMC determines the power detecting circuit board comprising the BMC is the leader detecting circuit board; when the level status of the first pin of the first connector connected to the GPIO port is a low-level status, the BMC determines the power detecting circuit board comprising the BMC is the follower detecting circuit board. (Brassac, Figure 1-2, [0065], The BMC components 14, 24 of each of the modules 1, 2, 3 are therefore capable of exchanging information among them, the pooling of their functions and information enabling the server 100, from the point of view of an external hardware management application, to be a single-module server 100. Thus, each BMC component 14, 24 is programmed to manage the high-level functions, i.e., central functions, of the server 100,”).
Regarding Claim 20, combination of Brassac and Xiao teaches the immersed liquid cooling tank of claim 19,
Brassac further teaches, wherein when the BMC determines the power detecting circuit board comprising the BMC is the leader detecting circuit board, the BMC controls the leader detecting circuit board to detect the running data of the at least one PSU corresponding to the leader detecting circuit board(Brassac, [0034] Advantageously, in said server, each BMC component is programmed to: [0035] identify in a set or subset of modules whether it belongs to a master or slave module, based on identification information from each of the modules of said set or subset”);, and polls the running data of the at least one PSU corresponding to the follower detecting circuit boards, and to summarize the running data of the at least one PSU corresponding to the leader detecting circuit board and the running data of the at least one PSU corresponding to the follower detecting circuit boards; when the BMC determines the power detecting circuit board comprising the BMC is the follower detecting circuit board, the BMC controls the follower detecting circuit board to detect the running data of the at least one PSU corresponding to the follower detecting circuit board, and to transmit the detected running data of the at least one PSU to the leader detecting circuit board. (Brassac, [0036]” if it belongs to a master module, configure its FPGA in such a way that the FPGA distributes the clock signal from the master module to the slave modules of the same set or subset; [0037] if it belongs to a slave module, configure its FPGA in such a way that the FPGA deactivates the clock signal from the slave module. [0038] Advantageously, in said server, each processor (CPU) of each module comprises time stamp counters (TSC) capable of synchronizing tasks involving a plurality of threads, the synchronization of all of the time stamp counters (TSC) of said processors (CPU) in a set or subset of modules being accomplished by: [0039] the sending of a notification, by each BMC component of each slave module of said set or subset, to the BMC of the master module when the slave module leaves an initialization or reinitialization phase; [0040] a notification to the BMC of the master module when the master module leaves an initialization or reinitialization phase “).
Conclusion
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huahua REN (US 2023/0217633 A1) recites “A container data center is provided. The data center is provided in a shipping container, and the container data center includes a cooling system including a plurality of cooling devices for cooling the data center; a power supply and distribution system including a power supply circuit for supplying power to the data center; and a control system electrically connected to the cooling system and the power supply and distribution system; wherein the control system comprises a plurality of control devices, the plurality of control devices each configured to control a part of the cooling devices, and when a first part of the plurality of control devices cannot work, a working mode of a second part of the control devices is adjusted to control the plurality of the cooling devices”. (Abstract)
b. Siheng LUO, (US 2022/0229479 A1) recites “A power supply unit (PSU)-based power supply system. A first output port of the PSU is connected to a main control component of a main board by using a voltage converter, and
is used to supply power to the main control component in a system standby stale. A second output port of the PSU may be connected to a load variable component of the main board; or the first output port and the second output port of the PSU may be connected to the load variable component by means of a power switching apparatus, and an enabling end of the PSU is grounded, so that both the first output port and the second output port have a voltage output when the PSU is inserted into the main board. A current value output by the second output port is relatively large load variable, which meets a power supply requirement of the load variable component. The second output port of the PSU is connected to each power-on running component of the main
board by means of a switch component, and the switch component is in an off state in the system standby state. After the system is powered on, the switch component is in an on state, so that each power-on running component does not
have extra power consumption when the system is in standby mode” (abstract).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/DILARA SULTANA/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 3/26/2026