Office Action Predictor
Last updated: April 15, 2026
Application No. 18/205,456

ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION

Non-Final OA §112
Filed
Jun 02, 2023
Examiner
ROLAND, CHRISTOPHER M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
65%
Grant Probability
Moderate
1-2
OA Rounds
3y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 65% of resolved cases
65%
Career Allow Rate
347 granted / 537 resolved
-3.4% vs TC avg
Strong +60% interview lift
Without
With
+60.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
33 currently pending
Career history
570
Total Applications
across all art units

Statute-Specific Performance

§103
50.0%
+10.0% vs TC avg
§102
21.3%
-18.7% vs TC avg
§112
24.2%
-15.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 537 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Applicant states that this application is a continuation or divisional application of the prior-filed application. A continuation or divisional application cannot include new matter. Applicant is required to delete the benefit claim or change the relationship (continuation or divisional application) to continuation-in-part because this application contains the following matter not disclosed in the prior-filed application: “e.g. by forming one or more gate electrode stacks, such as gate electrode stacks 200 as depicted in Figure 2,” as disclosed in paragraph [0058]. Information Disclosure Statement Information disclosure statements filed 5 June 2023, 22 February 2024, and 24 May 2024 have been fully considered. Drawings The drawings are objected to because: FIG. 1L identifies a second fin portion (164) that has a second height greater than a first height of a first fin portion (146). However, in FIGs. 1M, 1N, and 2, the second fin portion (164) is shown having a same height as the first fin portion (146). The second fin portion (164) of FIG. 1L appears to comprise two different elements. The drawings render unclear whether the second fin portion (164) is a single element or a pair of elements. FIG. 3 fails to show a third fin. FIGs. 1 and 2 disclose a plurality of fins each having one of three different heights: a semiconductor fin (118) having a fin height, a first fin (146) having a first height, and a second fin (164) having a second height different from the first height. FIG. 3A appears to only show two different fin heights: a first fin height defined by elements (304 and 305), and a second fin height defined by element (399). FIG. 3A identifies an isolation region (306). This appears to be the same feature as recessed ILD layer (128’’) shown in FIG. 2, but it is unclear based on the renumbering, the apparent difference in relative height, and the fact that the distinct trench isolation layer (168’’) is absent. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 200 as disclosed in paragraph [0058]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of claim 4, “forming a second molecular brush layer selectively on the second hardmask layer,” the subject matter of claim 8, “forming one or more gate electrode stacks on the exposing protruding portions of each of the plurality of semiconductor fins,” in combination with the subject matter of claim 1, “removing a second fin of the plurality of semiconductor fins,” and the subject matter of claim 10, “wherein removing the first fin of the plurality of semiconductor fins comprises etching the portion of the second patterned hardmask selective to exposed portions of the first patterned hardmask,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the subject matter of claim 8, “forming one or more gate electrode stacks on the exposing protruding portions of each of the plurality of semiconductor fins,” in combination with the subject matter of claim 1, “removing a second fin of the plurality of semiconductor fins,” and the subject matter of claim 10, “wherein removing the first fin of the plurality of semiconductor fins comprises etching the portion of the second patterned hardmask selective to exposed portions of the first patterned hardmask,” must find support in the specification. Claim Objections Claim 8 is objected to because of the following informalities: Claim 8 recites the limitation, “one or more gate electrode stacks on the exposing protruding portions.” This appears to contain a typographical error and may be corrected as, “one or more gate electrode stacks on the exposed protruding portions.” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 8 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 recites the limitation, “forming one or more gate electrode stacks on the exposing protruding portions of each of the plurality of semiconductor fins.” It is unclear how this feature is incorporated into the method of claim 1 which recites, “subsequent to removing the first fin, removing a second fin of the plurality of semiconductor fins.” As best understood by Examiner, the only embodiment comprising a gate electrode stack (308) is shown in FIG. 3 which at best shows only a single removed fin (399) and does not appear to correspond to the method steps shown in FIGs. 1-2. Claim 10 recites the limitation, “wherein removing the first fin of the plurality of semiconductor fins comprises etching the portion of the second patterned hardmask selective to exposed portions of the first patterned hardmask.” It is unclear how removing the first fin of the plurality of semiconductor fins comprises etching the portion of the second patterned hardmask selective to exposed portions of the first patterned hardmask. As best understood by Examiner, removing the second fin of the plurality of semiconductor fins comprises etching the portion of the second patterned hardmask selective to exposed portions of the first patterned hardmask. Allowable Subject Matter Claims 1-7 and 9 are allowed. Claims 8 and 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The prior art of record fails to teach the method of fabricating a semiconductor structure of claim 1 in the combination of limitations as claimed, noting particularly the limitation, “forming a segregated di-block co-polymer on the first patterned hardmask and on the second hardmask layer, the segregated di-block co-polymer comprising alternating first and second polymer blocks having a pitch between first blocks approximately equal to half the pitch of the features of the first patterned hardmask.” Wei et al. (US Patent Application Publication 2013/0309838) and Chiang et al. (US Patent Application Publication 2015/0069528) represent the closest prior art of record. See the 35 U.S.C. 103 rejections of claims 1 and 6 made in parent application no. 16/068095. However, neither of these references teach alternating first and second polymer blocks having a pitch between first blocks approximately equal to half the pitch of the features of the first patterned hardmask as claimed. Sudo (US Patent Application Publication 2013/0065326) of record suffers from a similar deficiency. Cheng et al. (US Patent Application Publication 2018/0047575, hereinafter Cheng ‘575) teaches (FIG. 7) alternating first (700) and second (702) co-polymers. However, the first (700) and second (702) co-polymers of Cheng ‘575 are formed over only a first hardmask layer (104), not a first and second hardmask layer as claimed. Further, Cheng ‘575 is not prior art. Shieh et al. (US Patent 8,975,129), Colburn et al. (US Patent Application Publication 2016/0071771), and Webb et al. (US Patent Application Publication 2016/0233298), although prior art, suffer from a similar deficiency. Schenker et al. (US Patent 10,892,223), Schenker et al. (US Patent 11,373,950), Schenker et al. (US Patent 11,854,787), and Schenker et al. (US Patent 12,218,052) teach the method of fabricating a semiconductor structure of claim 1 as claimed. However, these references are not prior art. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.R./Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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Prosecution Timeline

Jun 02, 2023
Application Filed
Jan 03, 2026
Non-Final Rejection — §112
Apr 06, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
65%
Grant Probability
99%
With Interview (+60.3%)
3y 2m
Median Time to Grant
Low
PTA Risk
Based on 537 resolved cases by this examiner. Grant probability derived from career allow rate.

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