Prosecution Insights
Last updated: July 17, 2026
Application No. 18/205,774

DISPLAY PANEL, PREPARING METHOD THEREOF, AND DISPLAY DEVICE

Final Rejection §102§103
Filed
Jun 05, 2023
Priority
Dec 30, 2022 — CN 202211740543.8
Examiner
PUNCHBEDDELL, SEYON ALI-SIMAH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tianma Advanced Display Technology Institute (Xiamen) Co., Ltd.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
61 granted / 79 resolved
+9.2% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
31 currently pending
Career history
110
Total Applications
across all art units

Statute-Specific Performance

§103
91.6%
+51.6% vs TC avg
§102
3.9%
-36.1% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 79 resolved cases

Office Action

§102 §103
DETAILED ACTION Response to Arguments Applicant’s arguments in regards to claim 1 filed 04/13/2026 have been fully considered but are not persuasive. Applicant argues on page 3 of the instant Remarks Zhou (US 2024/0047629 A1), fails to teach the following: “a light-shielding structure, wherein at least part of the light-shielding structure is at least located between a light-emitting element of the plurality of light-emitting elements and the thin-film transistor...” The Examiner respectfully disagrees. The Applicant asserts “as clearly shown in Zhou's Fig. 2, the light-emitting chip 30 is embedded directly within the opening of the light blocking layer 20 and sits directly on the pixel electrode 111. Therefore, in the vertical direction directly beneath the light-emitting chip 30, there is a physical void (the opening)”. The Examiner disagrees with this assertion. As shown below and with supporting teaching from paragraph 56 of Zhou, the openings correspond to the pixel electrode layer 111, so that a surface of the pixel electrode layer 111 away from the planarization layer 110 is exposed. There are no void areas shown or described in the teachings of Zhou as asserted by the applicant. Therefore, the rejection of claim 1 is maintained. PNG media_image1.png 425 898 media_image1.png Greyscale In regard to claim 17, the Examiner acknowledges Applicants request for the claim to be withdrawn from consideration and held in abeyance pending the allowance of the generic base claim, as the claim is drawn to a non-elected species shown in Fig. 25. Applicant’s arguments in regard to claim 10, have been fully considered and are persuasive. Therefore, the 35 U.S.C 112(b) rejection has been withdrawn. Examiner acknowledges the title of the invention has been changed and is clearly indicative of the invention to which the claims are directed. Therefore the specification objection has been withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 16 and 34 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhou (US 2024/0047629 A1). In regard to claim 1, Zhou teaches a display panel (a display panel 1) ( Fig. 2 and paragraph 23), comprising: a substrate (a substrate layer 101) (Fig. 2 and paragraph 23); a plurality of driver circuits (a plurality of thin film transistors) located on a side of the substrate, wherein a driver circuit of the plurality of driver circuits comprises a thin-film transistor (the plurality of thin film transistors are shown on the top side of the substrate layer 101) (Fig. 2 and paragraph 51); a plurality of light-emitting elements (light emitting chips 30) located on a side of the plurality of driver circuits facing away from the substrate (the light emitting chips 30 are shown on the topside of the plurality of thin film transistors in Fig. 2), wherein at least one of the plurality of light-emitting elements is electrically connected to the plurality of driver circuits (the light emitting chips 30 are electrically connected to the thin film transistors in the array substrate 10 by the pixel electrode layer 111) (Fig. 2 and paragraph 57); and a light-shielding structure (a light blocking layer 20) (Fig. 2 and paragraph 56), wherein at least part of the light-shielding structure is at least located between a light-emitting element of the plurality of light-emitting elements and the thin-film transistor (the light blocking layer 20 is shown over the thin film transistor in Fig. 2), and the light-shielding structure covers at least an active layer (an active layer 104) of the thin-film transistor in a direction perpendicular to a plane in which the substrate is located (the light blocking layer 20 is shown over the active layer 104 in Fig. 2). In regard to claim 16, Zhou teaches wherein a driver circuit of the plurality of driver circuits comprises a first metal structure (a pixel electrode layer 111) located on a side of the active layer of the thin-film transistor facing away from the substrate (a pixel electrode layer 111 is shown on the topside of the active layer 104) (Fig. 2 and paragraph 55); and at least part of the light-shielding structure and the first metal structure are disposed in a same layer (the pixel electrode layer 111 is shown in the same layer as the light blocking layer 20 in Fig. 2). In regard to claim 34, Zhou teaches a display device, comprising a display panel (the display device includes a display panel 1) ( Fig. 1 and paragraph 50), wherein the display panel comprises: a substrate (a substrate layer 101) (Fig. 2 and paragraph 23); a plurality of driver circuits (a plurality of thin film transistors) located on a side of the substrate, wherein a driver circuit of the plurality of driver circuits comprises a thin-film transistor (the plurality of thin film transistors are shown on the top side of the substrate layer 101) (Fig. 2 and paragraph 51); a plurality of light-emitting elements (light emitting chips 30) located on a side of the plurality of driver circuits facing away from the substrate (the light emitting chips 30 are shown on the topside of the plurality of thin film transistors in Fig. 2), wherein at least one of the plurality of light-emitting elements is electrically connected to the plurality of driver circuits (the light emitting chips 30 are electrically connected to the thin film transistors in the array substrate 10 by the pixel electrode layer 111) (Fig. 2 and paragraph 57); and a light-shielding structure (a light blocking layer 20) (Fig. 2 and paragraph 56), wherein at least part of the light-shielding structure is at least located between a light-emitting element of the plurality of light-emitting elements and the thin-film transistor (the light blocking layer 20 is shown over the thin film transistor in Fig. 2), and the light-shielding structure covers at least an active layer (an active layer 104) of the thin-film transistor in a direction perpendicular to a plane in which the substrate is located (the light blocking layer 20 is shown over the active layer 104 in Fig. 2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6-8, 10-11 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou as applied to claim 1 above, in view of Lu et al. (US 2022/0310693 A1; hereinafter “Lu”) In regard to claim 6, Zhou teaches the display panel, further comprising: bank structures (a light reflecting layer 40) (Fig. 2 and paragraph 58), wherein a bank structure of the bank structures is located on a side of the light-shielding structure facing away from the substrate and located at least between two adjacent light-emitting elements of the plurality of light-emitting elements (the light reflecting layer 40 is shown on the top of the light blocking layer 20 in Fig. 1), wherein a first gap is between the bank structure and a light-emitting element of the two adjacent light-emitting elements (the light reflecting layer 40 maintains a gap distance with the peripheral side surfaces of the light emitting chips 30) (paragraph 58); However, Zhou doesn’t explicitly teach in a direction parallel to the plane in which the substrate is located, a value range of a size d1 of the first gap is 0 pm < d1 <LO, wherein LO is a size of the light-emitting element in the direction parallel to the plane in which the substrate is located. Lu teaches a display panel (a micro light emitting diode display substrate as shown in Fig. 15) (Fig. 15 and paragraph 69), wherein a direction parallel to the plane in which a substrate (an underlay substrate 100) is located (Fig. 15 and paragraph 69), a value range of a size d1 of a first gap (a gap between a micro light emitting diode 300 and a black matrix layer 214) is 0 pm < d1 <L0, wherein L0 is a size of a light-emitting element (a micro light emitting diode 300) in the direction parallel to the plane in which the substrate is located (the gap between a micro light emitting diode 300 and a black matrix layer 214 is shown to be smaller than the light emitting diode 300 in Fig. 15). It would have been obvious to one skilled in the art to combine the teachings of Zhou in view of Lu to have in a direction parallel to the plane in which the substrate is located, a value range of a size d1 of the first gap is 0 pm < d1 <LO, wherein LO is a size of the light-emitting element in the direction parallel to the plane in which the substrate is located since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results. In regard to claim 7, Zhou teaches a surface of a side of the bank structure facing away from the substrate is a third surface (the top surface of the light reflecting layer 40 functions as the third surface) (Fig. 1); and a surface of a side of a light-emitting element of the plurality of light-emitting elements facing away from the substrate is a second surface (the top surface of the light emitting chip 30 functions as the second surface) (Fig. 2), wherein third surfaces and second surfaces satisfy at least one of: at least one of the third surfaces is flush with the second surface, or at least one of the third surfaces is located on a side of the second surface facing away from the substrate (the top surface light reflecting layer 40 is located in the lateral direction of the top surface of the light emitting chip 30) (Fig. 1). In regard to claim 8, Zhou doesn’t explicitly teach wherein the bank structure comprises a first bank portion and a second bank portion, wherein the second bank portion is located on a side of the first bank portion facing away from the substrate; and a size of the second bank portion is less than or equal to a size of the first bank portion in the direction parallel to the plane in which the substrate is located. Lu teaches wherein the bank structure comprises a first bank portion (a first bank portion is annotated as FP in Fig. 15 below) and a second bank portion (a second bank portion is labeled as SP in annotated Fig. 15 below), wherein the second bank portion is located on a side of the first bank portion facing away from the substrate (the second bank portion is shown on the topside of the first bank portion in annotated Fig. 15 below); and a size of the second bank portion is less than or equal to a size of the first bank portion in the direction parallel to the plane in which the substrate is located (due to the shape be trapezoidal the second bank portion SP has less width than the first bank portion FP). It would have been obvious to one skilled in the art to combine the teachings of Zhou with the teachings of Lu to have the bank structure comprises a first bank portion and a second bank portion, wherein the second bank portion is located on a side of the first bank portion facing away from the substrate; and a size of the second bank portion is less than or equal to a size of the first bank portion in the direction parallel to the plane in which the substrate is located since this layout aids in the manufacture of a device containing a light shielding layer and a water oxygen protection layer as taught by Lu (paragraph 81). PNG media_image2.png 588 904 media_image2.png Greyscale In regard to claim 10, Zhou teaches the display panel, further comprising: bank structures (a light reflecting layer 40) (Fig. 2 and paragraph 58), wherein a bank structure of the bank structures is located on a side of the light-shielding structure facing away from the substrate and located at least between two adjacent light-emitting elements of the plurality of light-emitting elements (the light reflecting layer 40 is shown on the top of the light blocking layer 20 in Fig. 1); and a first gap is between the bank structure and a light-emitting element of the two adjacent light-emitting elements (the light reflecting layer 40 maintains a gap distance with the peripheral side surfaces of the light emitting chips 30) (paragraph 58). However, Zhou does not explicitly teach wherein the bank structure comprises a first bank portion and a second bank portion; and the second bank portion is located on a side of the first bank portion facing away from the substrate; and a size of a first gap between the first bank portion and the light- emitting element is less or equal to a size of a first gap between the second bank portion and the light-emitting element. Lu teaches wherein the bank structure comprises a first bank portion (a first bank portion is annotated as FP in Fig. 15 above) and a second bank portion (a second bank portion is labeled as SP in annotated Fig. 15 above), and the second bank portion is located on a side of the first bank portion facing away from the substrate (the second bank portion is shown on the topside of the first bank portion in annotated Fig. 15 above); and a size of a first gap between the first bank portion and a light- emitting element (a micro light emitting diode 300) is less or equal to a size of a first gap between the second bank portion and the light-emitting element (as shown in annotated Fig. 15 the gap between the micro light emitting diode 300 and the first bank portions is smaller than the gap between the micro light emitting diode 300 and the second bank portion is labeled as SP due to the shape of the black matrix 214). It would have been obvious to one skilled in the art to combine the teachings of Zhou with the teachings of Lu to have the bank structure comprises a first bank portion and a second bank portion; and the second bank portion is located on a side of the first bank portion facing away from the substrate; and a size of a first gap between the first bank portion and the light- emitting element is less or equal to a size of a first gap between the second bank portion and the light-emitting element since this layout aids in the manufacture of a device containing a light shielding layer and a water oxygen protection layer as taught by Lu (paragraph 81). In regard to claim 11, Zhou teaches wherein a material of the bank structure is the same as a material of the light-shielding structure, or a reflectance of the bank structure is greater than a reflectance of the light-shielding structure (it is known to those skilled in the art the light blocking layer 20 has a lower reflectivity than the light reflecting layer 40). In regard to claim 26, Zhou doesn’t explicitly teach wherein the light-shielding structure comprises a black photoresist or a titanium dioxide-doped photoresist. Lu teaches a light-shielding structure comprises a black photoresist or a titanium dioxide-doped photoresist (a black matrix layer 214 functions as a black photoresist) (Fig. 15 and paragraph 81). It would’ve been obvious to one skilled in the art to combine the teachings of Zhou with the teachings of Lu to have a light-shielding structure comprises a black photoresist or a titanium dioxide-doped photoresist since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Lu as applied to claim 8 above, and further in view of Shirahata et al. (US 2017/0117338 A1; hereinafter “Shirahata”). In regard to claim 9, Zhou in view of Lu don’t explicitly teach further comprising: reflection structures, wherein a reflection structure of the reflection structures is located on a surface of a side of the bank structure facing the light-emitting element, wherein a reflectance of the reflection structure is greater than a reflectance of the bank structure, and the reflectance of the reflection structure is greater than a reflectance of the light-shielding structure. Shirahata teaches a display panel (a display device 1A) (Fig. 1 and paragraph 22), comprising: reflection structures (a first reflective layer 23) (Fig. 3 and paragraph 35), wherein a reflection structure of the reflection structures is located on a surface of a side of a bank structure (a side of a bank layer 31) facing a light-emitting element (the first reflective layer 23 is shown facing the lower electrode 20, the light-emitting layer 40, and the upper electrode 50 which constitute the emitting element layer) (Fig. 3 and paragraphs 30 and 35), wherein a reflectance of the reflection structure is greater than a reflectance of the bank structure (the resin of the bank layer 31 would have a lower reflectivity than the aluminum of the first reflective layer 23) (paragraphs 28 and 38), and the reflectance of the reflection structure is greater than a reflectance of a light-shielding structure (the first reflective layer 23 is formed of Al, the second reflective layer 25 may be formed of a material (Mo, etc.) having a light reflectance lower than that of Al) (paragraph 38). It would have been obvious to one skilled in the art to combine the teachings of Zhou in view of Lu with the teachings of Shirahata to have a reflection structure of the reflection structures located on a surface of a side of the bank structure facing the light-emitting element, wherein a reflectance of the reflection structure is greater than a reflectance of the bank structure, and the reflectance of the reflection structure is greater than a reflectance of the light-shielding structure since this layout allows for possible suppression of external light reflection while ensuring light extraction efficiency in the display device as taught by Shirahata. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou as applied to claim 1 above. In regard to claim 18, Zhou discloses the claimed invention except for wherein a value range of a thickness T1 of the light-shielding structure in the direction perpendicular to the plane in which the substrate is located is T1> 1/OD, wherein OD denotes an optical density value of the light- shielding structure, or an optical density (OD) value of the light-shielding structure satisfies OD> 1.0. However, as the light blocking layer 20 includes a photoresist material with a light shielding property, the Examiner takes official notice that the light blocking layer has an optical density>1, as it shields light and does not transmit it. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893 /SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 05, 2023
Application Filed
Jan 21, 2026
Non-Final Rejection mailed — §102, §103
Apr 13, 2026
Response Filed
May 14, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
83%
With Interview (+6.1%)
3y 6m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 79 resolved cases by this examiner. Grant probability derived from career allowance rate.

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