Prosecution Insights
Last updated: April 19, 2026
Application No. 18/206,428

SWITCHING MODE POWER SUPPLY AND CONTROLLING METHOD THEREOF

Non-Final OA §103
Filed
Jun 06, 2023
Examiner
SHAW, LAUREN ASHLEY
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
95%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
19 granted / 20 resolved
+27.0% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
21 currently pending
Career history
41
Total Applications
across all art units

Statute-Specific Performance

§103
46.2%
+6.2% vs TC avg
§102
40.5%
+0.5% vs TC avg
§112
12.7%
-27.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 20 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1, 4-11, and 14-20 are pending in this application. Claims 2-3 and 12-13 are cancelled. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) were submitted on 06/06/2023, 11/06/2023, 08/09/2024 and 06/13/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings were received on 06/06/23. These drawings are acceptable. Specification The disclosure is objected to because of the following informalities: Abstract line 5, “the converter being outputting a direct current (DC) voltage” appears it should be replaced with “the converter outputting a direct current (DC) voltage” Similar correction as above in par [0007] “the converter Appropriate correction is required. Claim Objections Claim 1 is objected to because of the following informalities: Claim 1 line 6 the phrase “the converter being outputting a direct current (DC) voltage” appears it should be replaced with “the converter Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4-6, 9, 11, 14-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bessho et al. (US 5977530 A), hereinafter Bessho and further in view of Ishizuka et al. (US 6127789 A), hereinafter Ishizuka. Regarding claims 1 and 11, Bessho discloses a switching mode power supply (fig 20, switching power supply including switching devices 3 and 6, driving circuit 7, and feedback loop) comprising: a power input unit (fig 20, AC input to DC power supply 1) configured to receive an input alternating current (AC) voltage (col 7 lines 37-38 “AC power supply is converted to DC voltage V.sub.DC from AC voltage by the full wave rectifier, and applied to a circuit…”); a rectification unit (fig 20, full wave rectifier within power supply 1) configured to rectify the input AC voltage (implicit); a condenser (fig 20, capacitor 51) configured to smooth the rectified input AC voltage (fig 20, see the position of capacitor 51 in parallel across the rectifier's output and the input to the switching stage, to act as a reservoir capacitor. It charges up during the peaks of the rectified voltage and then discharges when the voltage drops, thereby "smoothing" the waveform and reducing the ripple voltage); a detection unit configured to detect a surge current flowing in the condenser (fig 20, first resistive divider in block 52 and comparator 54 which receive voltage signal entering block 52 that is proportional to the overall current being drawn by the power converter circuit, which includes the current flowing into the resonant tank components (50 and 51). During a "surge" or inrush event, especially upon start-up, the current through the inductor 50 and capacitor 51 rapidly increases. Comparator 54 compares this scaled voltage against reference voltage source 53. If the surge current is high enough to generate a voltage that exceeds a threshold, the comparator output will trigger an immediate response from the driving/control circuit (block 7). Additionally, driving circuit 7 further detailed in fig 10, contains a current detector 41); and a converter (fig 20, including semiconductor switching device 3 and 6, transformer 2, rectifier on the secondary side of the transformer and additional components not labelled) comprising switching elements (fig 20, semiconductor switching device 3 and 6) the converter being outputting a direct current (DC) voltage (fig 1 and 20, secondary coil of the leakage transformer 2 is converted to high DC voltage by the full wave voltage doubler rectifier 8 (not labelled in fig 20, see fig 1) based on a voltage applied to a first end of the condenser and a second end of the condenser and on/off duty ratios of the switching elements (fig 20, voltage and current detections of the capacitor 51 are sent through 52, 54, and 59 and input to driving circuit 7 to control the switching devices 3 and 6; col 5 lines 13-17 “Electric power is configured to be controlled by changing the ratio of the ON time of pulses for driving the first semiconductor switching device to that for the second semiconductor switching device, and at the same time, keeping the frequency constant.”); wherein the switching elements are configured to be turned off based on the surge current being detected by the detection unit (col 16 lines 54+ and col 17 lines 1-28, the section describes how the circuit reacts to a voltage surge by implementing a stop signal to driving circuit 7, turning the switching devices off), and wherein the switching mode power supply further comprises a controller (fig 10 and 20, driving circuit 7 is further detailed in fig 10 with controlling functions) configured to: control a magnitude of the DC voltage output by the converter by controlling on/off operations of the switching elements (col 14 lines 47-65 describe the operation of the driving circuit 7 to control the output voltage at the secondary transformer coil by controlling the switching elements on/off times; see col 4 lines 57-64 and col 5 lines 12-20 for additional explanation of the driving circuit to control the switching elements on/off time), and based on the detection unit detecting the surge current while the converter outputs the DC voltage, turn off the switching elements (col 16 lines 55+ describes how the circuit reacts to a lightning surge, to protect the circuit the operation is stopped utilizing the voltage detector 52 to detect the surge and the driver 7 sends signals to the switching devices to turn off), wherein the switching elements comprise a first switching element and a second switching element that is structurally identical to the first switching element (fig 20, switching device 3 and 6 are IGBTs), and wherein the detection unit comprises: a first resistance having a first end to which a current flowing in the condenser is applied (fig 20, first resistor in block 52 see connection at input to capacitor 51), and a second end connected to a ground terminal (fig 2, resistor in block 52 connected to ground); and a comparator (fig 20, comparator 54) configured to: compare a voltage applied to the first end of the first resistance due to the current flowing in the condenser and a reference voltage (fig 20, comparator 54 inverting input reference voltage source 53 and non-inverting input from block 52), and output a first output voltage (col 15 lines 52+ “The comparator 54 compares the output of the voltage detector 52 and the voltage level of the reference voltage source 53. If the output of the voltage detector 52 is greater, the comparator 54 outputs a stop signal to the driving circuit 7 to stop the operation of the circuit.”). Bessho does not explicitly disclose a current detector in its disclosure however Bessho does disclose the components for a current detector as disclosed in the instant application’s current detector 151 (Bessho fig 20, first resistor in 52 connected to ground and comparator with Vreg input). Motivation in Bessho’s disclosure for an alternate configuration can be found in col 17 lines 23-27 “With this configuration, the operation of the circuit may be immediately stopped at occurrence of excessive voltage by lightning surge or sparking. The circuit can also be configured with less components by sharing parts of the circuit.” Ishizuka discloses a power supply circuit. Ishizuka discloses a current detection unit (fig 5, 205; col 9 line 38-43 “The voltage/current sensor 205 is in such a well-known configuration that the lamp voltage … is detected by dividing the output voltage of the operating circuit 204 by the resistors 214 and 215 and the lamp current is detected according to voltage drop in the resistor 216”). Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Bessho with substitution of one known element for another such as the voltage/current detector as taught by Ishizuka or to combine prior art reference teachings to arrive at the claimed invention. The advantage of this design is that by adding a single resistor the voltage detector of Bessho could also function as a current/voltage detector of Ishizuka to be able to detect an abnormal current input to the capacitor. Regarding claim 4 and 14, Bessho and Ishizuka disclose the switching mode power supply of claim 1, wherein the comparator (Bessho fig 20, comparator 54) is further configured to, based on a voltage due to the surge current being applied to the first end of the first resistance while outputting the first output voltage, output a second output voltage (Bessho col 15 lines 52+; by design a comparators output is low (first voltage) or high (second voltage)), and wherein the controller is further configured to, based on the second output voltage being output by the comparator, turn off the switching elements (Bessho col 15 lines 52+ describes when a surge is detected the comparator 54 outputs the stop signal to the driving circuit 7 which in turn disables the driving signal V.sub.G that is required at the IGBT gate for turning on, thus the IGBTs transition and remain OFF until the comparator signal is low). Regarding claim 5 and 15, Bessho and Ishizuka disclose the switching mode power supply of claim 4, further comprising a voltage detection unit (Bessho fig 20, resistor divider with connections to AC input and AC supply voltage detector in block 56) comprising a second resistance (Bessho fig 20, resistor divider to the left of block 56), wherein the voltage detection unit is configured to provide a current flowing between the power input unit and the rectification unit through the second resistance (Bessho fig 20, see voltage detector between AC supply voltage and rectifier and resistive divider that received the AC power supply voltage/current), and wherein the controller is further configured to, based on a first voltage detected due to a current applied to the controller through the second resistance being greater than or equal to a first predetermined value, turn off the switching elements (Bessho col 15 lines 52+ describes when a surge is detected the comparator 54 outputs the stop signal to the driving circuit 7 which in turn disables the driving signal V.sub.G that is required at the IGBT gate for turning on, thus the IGBTs transition and remain OFF until the comparator signal is low). Regarding claim 6 and 16, Bessho and Ishizuka disclose the switching mode power supply of claim 5, further comprising a third resistance (Bessho fig 20, resistive divider to the right of the capacitor in block 52) that is connected in parallel with the second resistance (Bessho fig 20, second resistance to the left of block 56 is in parallel with third resistance in block 52) when the comparator outputs the second output voltage, and wherein the controller is configured to, based on a second voltage, detected based on a current applied through the second resistance and the third resistance connected in parallel, being greater than or equal to the first predetermined value, turn off the switching elements (Bessho col 16 lines 55+ and col 17 lines 1-27 describe the function of the AC supply voltage detector 56 and its interaction with the resistors, diodes, and comparator at occurrence of excessive voltage by lightning surge or sparking, the configuration allows for the operation of the circuit to be immediately stopped, by outputting the stop signal to the driving circuit 7, turning off the switching elements). Regarding claim 9 and 19, Bessho and Ishizuka disclose the switching mode power supply of claim 1, further comprising a voltage detection unit configured to detect a magnitude of a voltage input through the power input unit, wherein the controller is further configured to, based on a voltage detected by the voltage detection unit becoming lower than or equal to a third predetermined value after the switching elements are turned off, control the on/off operations of the switching elements (Bessho col 16 lines 6-54 describe a spark situation in the circuit that would warrant excessive current I.sub.C1 flows and the voltage V.sub.C51 suddenly drops. When V.sub.C51 increases suddenly and exceeds a certain level “third threshold value”, the output signal is transmitted. This signal stops the driving circuit 7 which turns the switching elements off). Claims 7-8, 10, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Bessho et al. (US 5977530 A), hereinafter Bessho and further in view of Ishizuka et al. (US 6127789 A), hereinafter Ishizuka and Yu (US 11081876 B2). Regarding claim 7 and 17, Bessho and Ishizuka disclose the switching mode power supply of claim 1. Bessho and Ishizuka fail to disclose a varistor connected in parallel with the condenser, wherein a voltage applied to the first end of the condenser and the second end of the condenser is clamped at a second predetermined value by the varistor, based on a voltage greater than or equal to the second predetermined value being applied to the first end of the condenser and the second end of the condenser. Yu discloses a control circuit for switch mode power supply. Yu discloses a varistor (e.g. Fig 1, metal-oxide varistor MOV 138/118 or clamp 116) connected in parallel with the condenser (fig 1, 138 and 116 shown connected in parallel to C1), wherein a voltage applied to the first end of the condenser and the second end of the condenser is clamped at a second predetermined value by the varistor (fundamental principle that a varistor limits or "clamps" voltage is a well-established function in electrical engineering but not directly specified in Yu. A varistor connected in parallel with a capacitor provides both surge protection and transient voltage suppression when the voltage across the varistor exceeds its specific "clamping" or breakdown voltage (a predetermined value), its resistance decreases dramatically and non-linearly), based on a voltage greater than or equal to the second predetermined value being applied to the first end of the condenser and the second end of the condenser (col 4-5 lines 65-67 and 1-2 "The clamp circuit 116 limits the voltage across primary winding L1 126 to protect the power switch S1 136 from damage by excessive voltage. The clamp circuits 116 can be any voltage clamp circuits available in the existing art."). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Bessho and Ishizuka and incorporate the use of a varistor in parallel to the capacitor as taught by Yu. The advantage of this design is for when a high-voltage surge or transient occurs, the varistor's resistance drops rapidly, allowing it to conduct the excess current away from the protected circuit. This effectively "clamps" the voltage to a safe level, preventing damage to sensitive components. Regarding claim 8 and 18, Bessho, Ishizuka and Yu disclose the switching mode power supply of claim 7, wherein the second predetermined value is lower than an inner voltage of the switching elements (Yu col 6 lines 18-33). Regarding claim 10 and 20, Bessho, Ishizuka and Yu disclose the switching mode power supply of claim 1, wherein a capacity of the condenser is lower than or equal to 47uF (Yu col 7 lines 11-13 “the circuit BOM may only require one 10 uF C1 112 and Q1 314 if using a controller U1 322”). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren A Shaw whose telephone number is (571)272-3074. The examiner can normally be reached Mon-Fri 7-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN ASHLEY SHAW/Examiner, Art Unit 2838 /THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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Prosecution Timeline

Jun 06, 2023
Application Filed
Apr 21, 2025
Non-Final Rejection — §103
Jun 06, 2025
Interview Requested
Jun 26, 2025
Examiner Interview Summary
Jun 26, 2025
Applicant Interview (Telephonic)
Jul 24, 2025
Response Filed
Sep 08, 2025
Final Rejection — §103
Nov 24, 2025
Request for Continued Examination
Nov 29, 2025
Response after Non-Final Action
Jan 15, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+7.7%)
2y 7m
Median Time to Grant
High
PTA Risk
Based on 20 resolved cases by this examiner. Grant probability derived from career allow rate.

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