Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-2, 7-8, 11-14 and 17-18 are currently pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 7-8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Gibson et al. (U.S. Pub. No. 20110239220 A1) in view of Lo et al. (U.S. Pub. No. 20180321980 A1), further in view of Berninger et al. (U.S. Patent No. 11258806 B1), further in view of Khan et al. (U.S. Pub. No. 20230014795 A1), and further in view of Applicant Admitted Prior Art (AAPA).
Gibson, Lo and AAPA were previously cited.
As per claim 1, Gibson teaches the invention substantially as claimed including an electronic device comprising:
memory, including one or more storage media, storing instructions (par. 0096 "machine-readable medium" refers to any computer program product, apparatus and/or device (e.g. … memory; Fig. 1,System Memory 150);
memory resource allocation hardware (par. 0038 the management module 106 can control the allocation of resources by determining/controlling the task performance profiles); and
at least one processor including processing circuitry (par. 0043 processor system 10 can execute instructions), wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:
execute a plurality of tasks … (par. 0023 The scheduler module can schedule a plurality of tasks to be executed; par. 0006 Execution of a plurality of tasks by a processor system are monitored)
while the plurality of tasks are being executed, generate a plurality of profiles including first memory resource allocation information for each of the plurality of tasks … (par. 0036 The management module 106 can create, and/or retrieve previously created performance profiles from system memory; par. 0010 Each task can have an associated performance profile … The associated performance profile can specify at least one performance parameter … for example, be a cache occupancy quota specifying an initial maximum and/or minimum amount of buffers to be used by the task and the cache occupancy quota can be dynamically adjusted during execution of the task);
generate second memory resource allocation information …; control the memory resource allocation hardware to allocate a memory resource, based on the second memory resource allocation information, so as to reduce a response time of the at least one foreground task (par. 0094 Based on the monitoring, at 520,tasks requiring adjustment of performance resources are identified … performance resources of the processor system allocated to each identified task are adjusted. The adjusting can include … adjusting an amount of cache and/or buffer [which results in second memory resource allocation] to be utilized by the task; par. 0038 management module 106 can control the allocation of resources by determining/controlling the task performance profiles (e.g. through a set of policies/rules, etc.). For example, by controlling the allocation of performance resources to all tasks, each task can be provided with throughput and response time guarantees. In addition, by allocating the minimum performance resources to all tasks, a minimal amount of processor resources of the processor system 10 and/or a computing system incorporating the processor system 10 (that includes the I/O subsystem module 108 and the system memory 150, etc.) performance resources are utilized);
Gibson does not expressly disclose: measure a response time of a task; using a designated algorithm, the designated algorithm being based on a model trained by machine learning on the plurality of profiles, wherein the second memory resource allocation information has a response time that is shorter than a first response time corresponding to the first response time information.
However, Lo teaches: measure a response time of a task (par. 0098 the execution time of the prediction slice can be measured; par. 0005 predicting execution time of the plurality of program tasks on one or more computing cores using the plurality of program features); using a designated algorithm, the designated algorithm being based on a model trained by machine learning on the plurality of profiles (par. 0103 For each job, the model [machine learning model] is first used to determine the appropriate core and frequency … the model is updated using the execution time of that job. This continuous on-line learning enables the DVFS controller to adapt to run-time interference), wherein the second memory resource allocation information has a response time that is shorter than a first response time corresponding to the first response time information (par. 0005 … controlling [allocation of] resources for the one or more computing cores based on the predicted execution time of the plurality of program tasks; par. 0163 wherein resources that can be controlled by the disclosed technique include voltage, amount of memory, amount of cache space, interconnection bandwidth, or memory bandwidth; par. 0098 The execution of the prediction slice and DVFS switch reduces the amount of time available for a job to execute and still satisfy its budget. It is noted, for example increasing amount of resource [e.g. voltage/frequency, memory] results in reduced/shorter response time).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique of controlling resources for execution of tasks to reduce execution time of Lo with the system and method of Gibson resulting in a system and method which provides for controlling allocation of amounts of resources to reduce response time as in Lo. One of ordinary skill in the art would have been motivated to make this combination for the purpose of improving energy efficiency while meeting response-time requirement for both computer software [tasks] and hardware (par. 0004).
Gibson and Lo do not expressly teach: based on a number of the generated plurality of profiles being greater than or equal to a designated value and the electronic device being in an idle state, update the designated algorithm based on the generated plurality of profiles.
However, Berninger teaches: based on a number of the generated plurality of profiles being greater than or equal to a designated value …, update the designated algorithm based on the generated plurality of profiles (col. 3, lines 23-27 Thereafter, in response to a triggering event (e.g., time-based trigger, change in a profile or predetermined number or percentage of profiles, etc.), the machine learning-based model may be updated by conducting analytics on the indicia included within the profiles).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique updating a machine learning model of Berninger with the system and method of Gibson and Lo resulting in a system and method which provides for updating a machine learning model based on a predefined number of profiles being generated as in Berninger. One of ordinary skill in the art would have been motivated to make this combination for the purpose of improving the accuracy of the model in identifying correct categorized profile associated with the test profiles (col. 6, lines 53-55).
Gibson, Lo and Berninger do not expressly teach: based on …. the electronic device being in an idle state, update the designated algorithm.
However, Khan teaches: based on …. the electronic device being in an idle state, update the designated algorithm (par. 0107 the terminal 102-1 will not update the previous machine-learning model with the optimized model 135 until an idle period has occurred).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique of performing updates to an algorithm when idle period has occurred of Khan with the system and method of Gibson, Lo and Berninger resulting in a system and method which provides for performing updates to a machine learning model when device is in idle state as in Khan. One of ordinary skill in the art would have been motivated to make this combination for the purpose of avoiding any disruptions to the client devices (par. 0107).
Gibson, Lo, Berninger and Khan do not expressly describe: execute a plurality of tasks including at least one foreground task and at least one background task.
However, AAPA teaches: execute a plurality of tasks including at least one foreground task and at least one background task (par. 0007 one foreground task and one background task operate [execute] simultaneously and both tasks are memory-intensive tasks).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique of executing plurality of tasks including foreground and back ground tasks of AAPA with the system and method of Gibson, Lo, Berninger and Khan resulting in a system which provides for executing foreground and backgrounds tasks simultaneously as in AAPA. One of ordinary skill in the art would have been motivated to make this combination for the purpose of improving response time of foreground tasks.
As per claim 2, Gibson further teaches: memory resource monitoring hardware (par. 0023 The metering module can monitor execution of the plurality of tasks), wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to generate each of the plurality of profiles by: acquiring a cache access count and memory bandwidth of each of the plurality of tasks from the memory resource monitoring hardware (par. 0047 The metering module 110, when used to monitor memory operations (bandwidth); par. 0048 A monitored value related to the work performed or work completed can be measured by counting the accesses to memory, instructions completed, and/or other measurable quantities that are meaningful measurements of work by the currently executing task(s); par. 0050 a meter module may measure; memory accesses or cache miss occurrences (i.e., failed attempts to read or write a piece of data in the buffer resulting in a main memory access); and based on at least one of the cache access count being greater than or equal to a designated value or the memory bandwidth being greater than or equal to a designated value, measuring the response time of the at least one foreground task (par. 0038 For example, by controlling the allocation of performance resources to all tasks, each task can be provided with throughput and response time guarantees; par. 0054 execution time can be derived from the previous executions of the task (running on the processor system) and can be a measure of the cumulative time for the task's expected work to be completed).
As per claim 5, Gibson further teaches: generate, in the plurality of tasks, a group for at least one task having a same memory resource allocation information configured in each of the plurality of tasks; and transmit identification information of the group and the configured memory resource allocation information to the memory resource allocation hardware (par. 0007 each task can be selected from a group comprising: a single task, a group of tasks; par. 0040 Performance profiles can be assigned to groups of tasks similar to the performance profile for an individual task. In one implementation, tasks that are members of a group share a common performance profile and the performance resource parameters can be derived from that common profile; par. 0041 A multiplicity of groups can exist where tasks are members of one or more groups that specify both common and separate performance profile parameters where the parameters utilized by the performance resource manager are derived from the various performance profiles).
As per claim 7, it is an operating method having similar limitations as claim 1. Thus, claim 7 is rejected for the rationale as applied to claim 1.
As per claim 8, it is an operating method having similar limitations as claim 2. Thus, claim 8 is rejected for the rationale as applied to claim 2.
As per claim 11, it is an operating method having similar limitations as claim 5. Thus, claim 11 is rejected for the rationale as applied to claim 5.
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Gibson, Lo, Berninger, Khan and AAPA, and further in view of Hsieh et al. (US 20210297149 A).
As per claim 6, Gibson, Lo, Berninger, Khan and AAPA do not expressly teach: based on a change in the identification information of the task, transmit the identification information of the group comprising the task and the changed identification information of the task to the memory resource allocation hardware.
However, Hsieh teaches: based on a change in the identification information of the task, transmit the identification information of the group comprising the task and the changed identification information of the task to the memory resource allocation hardware (0145 based on the updated location information and/or that the selected group ID may have expired, and in response may select a new group ID; par. 0146 In operation S5040, the UE device 201 transmits the updated group ID to the NTN device 300).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique responsive to determining updated group ID, transmitting the group Ide to NTN device of Hsieh with the system and method of Gibson, Lo, Berninger, Khan and AAPA resulting in a system and method in which responsive to determining an updated ID for a task/task group, transmitting updated task/task group to resource allocation module as in Hsieh. One of ordinary skill in the art would have been motivated to make this combination for the purpose of efficiently re-scheduling tasks based on the update group ID (par. 0146). Further, it would allow for efficient execution tracking of tasks.
As per claim 12, it is an operating method having similar limitations as claim 6. Thus, claim 12 is rejected for the rationale as applied to claim 6.
Claims 13-14, 71-18 are rejected under 35 U.S.C. 103 as being unpatentable over Gibson et al. (U.S. Pub. No. 20110239220 A1) in view of Lo et al. (U.S. Pub. No. 20180321980 A1), further in view of Berninger et al. (U.S. Patent No. 11258806 B1), and further in view of Khan et al. (U.S. Pub. No. 20230014795 A1).
Gibson and Lo were cited in a previous office action.
As per claim 13, Gibson teaches the invention substantially as claimed including an electronic device comprising:
memory, including one or more storage media (par. 0096 "machine-readable medium" refers to any computer program product, apparatus and/or device (e.g. … memory; Fig. 1,System Memory 150), storing instructions;
memory resource allocation hardware (par. 0038 the management module 106 can control the allocation of resources by determining/controlling the task performance profiles); and
at least one processor including processing circuitry (par. 0043 processor system 10 can execute instructions), wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:
obtain at least one profile comprising information related to a memory resource allocation for the task … (par. 0036 The management module 106 can create, and/or retrieve previously created performance profiles from system memory; par. 0010 Each task can have an associated performance profile … The associated performance profile can specify at least one performance parameter … for example, be a cache occupancy quota specifying an initial maximum and/or minimum amount of buffers to be used by the task and the cache occupancy quota can be dynamically adjusted during execution of the task);
configure memory resource allocation to the task based on memory resource allocation information for minimizing the response time; and transmit the information of the task and the configured memory resource allocation information to the memory resource allocation hardware (par. 0038 management module 106 can control the allocation of resources by determining/controlling the task performance profiles (e.g. through a set of policies/rules, etc.). For example, by controlling the allocation of performance resources to all tasks, each task can be provided with throughput and response time guarantees. In addition, by allocating the minimum performance resources to all tasks, a minimal amount of processor resources of the processor system 10 and/or a computing system incorporating the processor system 10 … performance resources are utilized; par. 0023 scheduler module can schedule a plurality of tasks to be executed by the at least one processor).
Gibson does not expressly describe: measure a response time of a task; determine the memory resource allocation for minimizing the response time of the task using a designated algorithm, wherein the designated algorithm is based on a model trained by machine learning on the at least one profile.
However, Lo teaches: measure a response time of a task (par. 0098 the execution time of the prediction slice can be measured; par. 0005 predicting execution time of the plurality of program tasks on one or more computing cores using the plurality of program features); determine the memory resource allocation for minimizing the response time of the task (par. 0005 … controlling [allocation of] resources for the one or more computing cores based on the predicted execution time of the plurality of program tasks; par. 0163 wherein resources that can be controlled by the disclosed technique include voltage, amount of memory, amount of cache space, interconnection bandwidth, or memory bandwidth; par. 0098 The execution of the prediction slice and DVFS switch reduces the amount of time available for a job to execute and still satisfy its budget. It is noted, for example increasing amount of resource [e.g. voltage, memory] results in reduced/shorter response time) using a designated algorithm, wherein the designated algorithm is based on a model trained by machine learning on the at least one profile (par. 0103 For each job, the model [machine learning model] is first used to determine the appropriate core and frequency … the model is updated using the execution time of that job. This continuous on-line learning enables the DVFS controller to adapt to run-time interference).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique of controlling resources for execution of tasks to reduce execution time of Lo with the system and method of Gibson resulting in a system and method which provides for controlling allocation of amounts of resources to reduce response time as in Lo. One of ordinary skill in the art would have been motivated to make this combination for the purpose of improving energy efficiency while meeting response-time requirement for both computer software [tasks] and hardware (par. 0004).
Gibson and Lo do not expressly teach: based on a number of the generated plurality of profiles being greater than or equal to a designated value and the electronic device being in an idle state, update the designated algorithm based on the generated plurality of profiles.
However, Berninger teaches: based on a number of the generated plurality of profiles being greater than or equal to a designated value …, update the designated algorithm based on the generated plurality of profiles (col. 3, lines 23-27 Thereafter, in response to a triggering event (e.g., time-based trigger, change in a profile or predetermined number or percentage of profiles, etc.), the machine learning-based model may be updated by conducting analytics on the indicia included within the profiles).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique updating a machine learning model of Berninger with the system and method of Gibson and Lo resulting in a system and method which provides for updating a machine learning model based on a predefined number of profiles being generated as in Berninger. One of ordinary skill in the art would have been motivated to make this combination for the purpose of improving the accuracy of the model in identifying correct categorized profile associated with the test profiles (col. 6, lines 53-55).
Gibson, Lo and Berninger do not expressly teach: based on …. the electronic device being in an idle state, update the designated algorithm.
However, Khan teaches: based on …. the electronic device being in an idle state, update the designated algorithm (par. 0107 the terminal 102-1 will not update the previous machine-learning model with the optimized model 135 until an idle period has occurred).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique of performing updates to an algorithm when idle period has occurred of Khan with the system and method of Gibson, Lo and Berninger resulting in a system and method which provides for performing updates to a machine learning model when device is in idle state as in Khan. One of ordinary skill in the art would have been motivated to make this combination for the purpose of avoiding any disruptions to the client devices (par. 0107).
As per claim 14, Gibson further teaches: acquire a cache access count and a memory bandwidth of the task before the at least one profile is obtained (par. 0047 The metering module 110, when used to monitor memory operations (bandwidth); par. 0048 A monitored value related to the work performed or work completed can be measured by counting the accesses to memory, instructions completed, and/or other measurable quantities that are meaningful measurements of work by the currently executing task(s); par. 0050 a meter module may measure; memory accesses or cache miss occurrences (i.e., failed attempts to read or write a piece of data in the buffer resulting in a main memory access), wherein the measuring the response time of the task is performed based on at least one of the cache access count being greater than or equal to a designated value or the memory bandwidth being greater than or equal to a designated value (par. 0038 For example, by controlling the allocation of performance resources to all tasks, each task can be provided with throughput and response time guarantees; par. 0054 execution time can be derived from the previous executions of the task (running on the processor system) and can be a measure of the cumulative time for the task's expected work to be completed).
As per claim 17, Gibson further teaches: generate, in a plurality of tasks, a group for at least one task having a same memory resource allocation information configured in each of the plurality of tasks, wherein the transmitting comprises transmitting identification information of the group and the configured memory resource allocation information to the memory resource allocation hardware (par. 0007 wherein each task can be selected from a group comprising: a single task, a group of tasks; par. 0040 Performance profiles can be assigned to groups of tasks similar to the performance profile for an individual task. In one implementation, tasks that are members of a group share a common performance profile and the performance resource parameters can be derived from that common profile).
As per claim 18, Gibson further teaches: store the identification information of the group and the configured memory resource allocation information in the task group directory; and based on a change in the identification information of the task, transmit the identification information of the group comprising the task stored in the task group directory and the changed identification information of the task to the memory resource allocation hardware (par. 0006 wherein execution of a plurality of tasks by a processor system are monitored. Based on this monitoring, tasks requiring additional performance resources are identified by calculating a progress error and/or one or more progress limit errors for each task. Thereafter, performance resources of the processor system allocated to each identified task are adjusted).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Gibson, Lo, Berninger, and Khan, and further in view of Hsieh et al. (US 20210297149 A).
As per claim 6, Gibson, Lo, Berninger and Khan do not expressly teach: store the identification information of the group and the configured memory resource allocation information in the task group directory based on a change in the identification information of the task, transmit the identification information of the group comprising the task stored in the task group directory and the changed identification information of the task to the memory resource allocation hardware.
However, Hsieh teaches: store the identification information of the group and the configured memory resource allocation information in the task group directory; and based on a change in the identification information of the task, transmit the identification information of the group comprising the task stored in the task group directory and the changed identification information of the task to the memory resource allocation hardware (par. 0041 the group information including a plurality of group identifiers (IDs); par. 0145 based on the updated location information and/or that the selected group ID may have expired, and in response may select a new group ID; par. 0146 In operation S5040, the UE device 201 transmits the updated group ID to the NTN device 300).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the technique responsive to determining updated group ID, transmitting the group Ide to NTN device of Hsieh with the system and method of Gibson, Lo, Berninger and Khan resulting in a system and method in which responsive to determining an updated ID for a task/task group, transmitting updated task/task group to resource allocation module as in Hsieh. One of ordinary skill in the art would have been motivated to make this combination for the purpose of efficiently re-scheduling tasks based on the update group ID (par. 0146). Further, it would allow for efficient execution tracking of tasks.
Response to Arguments
Applicant's arguments filed 01/28/2026 have been fully considered but they are not persuasive.
(1) The applicant argues in page 14 for claim 1 that Lo does not disclose or suggest "a designated algorithm, the designated algorithm being based on a model trained by machine learning on the plurality of profiles,"
As per point 1, the examiner respectfully submits that the prior art cited reasonably teaches the limitations as claimed. For example, Lo, par. 0103, describes that a model [machine learning model] is first used to determine the appropriate core and frequency for each job, wherein after the job finishes, the model is updated using the execution time of that job, and that this continuous on-line learning enables the DVFS controller to adapt to run-time. Applicant’s argument is not persuasive.
(2) The applicant argues in page 14 for claim 1 that none of Gibson, Lo, or AAPA discloses or suggests an electronic device configured to "generate second memory resource allocation information … wherein the second memory resource allocation information has a response time that is shorter than a first response time corresponding to the first response time information”
As per point 2, the examiner respectfully disagrees. For example, Lo, par. 0005, clearly describes controlling [allocation of] resources for the one or more computing cores based on the predicted execution time of the plurality of program tasks, par. 0163, where the resource that can be controlled include voltage, amount of memory, amount of cache space. Further, par. 0098, describes that execution of a prediction slice and DVSF reduces the amount time for a job to execute and still satisfy. That is, a resource allocation that increases the amount of resources [the voltage or memory mount] results in reduced or shorter response time of a task. Therefore, applicant’s arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Willy W. Huaracha whose telephone number is (571) 270-5510. The examiner can normally be reached on M-F 8:30-5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached on (571) 272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WH/
Examiner, Art Unit 2195
/BRADLEY A TEETS/ Supervisory Patent Examiner, Art Unit 2197
Prosecution Insights