DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuckerman et al. (US Pat No. 11,467,827) in view of Neumann et al. (US PG Pub No. 2024/0270263 A1).
Zuckerman was disclosed in IDS dated 09/20/2024.
Regarding claim 1, Zuckerman teaches a computing system
a central chiplet including:
(a) a shared memory storing a plurality of programs associated with a plurality of parallel workload pipelines (col 5 lines 36-48, multiple producer processors compute and output data to respective locations in a buffer in a memory, such as a static random-access memory),
(b) one or more processors configured to execute a scheduling program (col 5 lines 36-48, wherein system comprises a processing pipeline comprising multiple, sequential stages of parallel computations), and
(c) a cache memory accessible by the plurality of chiplets (col 5 lines 36-48, multiple producer processors compute and output data to respective locations in a buffer in a memory, such as a static random-access memory); and
wherein,
Zuckerman does not teach a computer system for operating a vehicle and a sensor data input chiplet configured to, while the vehicle operates, (i) receive sensor data from a plurality of sensors of the vehicle, and (ii) store the sensor data in the cache memory of the central chiplet; and performing the scheduling upon sensor data being cached by the sensor data input chiplet.
Neumann teaches a control device for operating a vehicle comprising a SoC (single chip) or a MCM (multi-chip module) having multiple chips or chiplets, wherein the control device comprising a calculation region (i.e. central chiplet), which calculates the lanes or trajectories and outputs the corresponding driving recommendations or driving commands and a verification region (i.e. sensor data input chiplet) which verifies the integrity of the input data received from the external control units and sensors of the vehicle and makes the checked input data available to the calculation region ([0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include a sensor data input chiplet for receiving sensor data from a plurality of sensors of the vehicle, and storing the sensor data in the cache memory of the central chiplet. One would be motivated by the desire to extend Zuckerman to be used for vehicle driving applications.
Regarding claim 2, Zuckerman teaches wherein the respective workloads are each referenced by a workload identifier that includes an address within a uniform memory address space where data associated with each workload is stored (col 6 lines 1-19, wherein these command inputs drive respective processing elements to read a certain range of input data from buffer, apply the corresponding work unit to the input data, output the resulting output data, and report completion back to scheduler; each work unit is identified by a corresponding index).
Regarding claim 3, Zuckerman teaches wherein the plurality of chiplets includes a plurality of workload processing chiplets, and instructions corresponding to the respective workloads are executed on either the sensor data input chiplet or one of the plurality of workload processing chiplets (col 6 lines 1-19, wherein a scheduler reads program instructions from a program memory and distributes corresponding command inputs to producer processors and consumer processors).
Regarding claim 4, Zuckerman teaches wherein one of the respective workloads executed on the sensor data input chiplet includes pre-processing the sensor data (col 6 lines 1-19, wherein processing elements carry out the work units invoked by the commands by reading data from appropriate addresses in an input buffer and then writing the computational results to appropriate address ranges in buffer).
Regarding claim 5, Zuckerman teaches wherein the plurality of workload processing chiplets store processed data in the cache memory, and additional workloads in the plurality of parallel workload pipelines execute based on the processed data (col 5 lines 49-58, wherein consumer processors will output data to a further buffer and will thus serve as the producers for consumers in a subsequent processing stage, and so forth over multiple successive stages and buffers in the pipeline).
Regarding claim 6, Zuckerman teaches wherein the plurality of workload processing chiplets access entries in a reservation table in the shared memory to determine whether a set of dependency conditions are satisfied to begin execution of the respective workloads (col 6 lines 1-19, wherein consumer processors receive command inputs in respective command buffers; these command inputs drive respective processing elements to read a certain range of input data from buffer).
Regarding claim 7, Zuckerman teaches the plurality of workload processing chiplets update the reservation table with a starting time and a finishing time for executing each workload (col 11 lines 12-29, wherein processor evaluates the runtime patterns of access to the input and output buffers during runtime of the object code generated).
Regarding claim 8, Zuckerman teaches wherein the plurality of workload processing chiplets includes a machine learning accelerator chiplet to calculate inferences using machine learning (col 1 lines 24-36, wherein the convolutional layers are interleaved in a pipeline with other computational layers that perform operations such as pooling and linear unit rectification).
Regarding claim 9, Neumann teaches wherein the plurality of workload processing chiplets includes an autonomous drive chiplet to calculate autonomous driving algorithms ([0034]).
Regarding claims 10-20, they are the system and computer readable medium claims of claims 1-9 above. Therefore, they are rejected for the same reasons as claims 1-9 above.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC C WAI whose telephone number is (571)270-1012. The examiner can normally be reached Monday - Friday 9-5.
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/Eric C Wai/Primary Examiner, Art Unit 2195
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