DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 28 April 2026 and 24 August 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 20 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 20 has been amended to include “the at least one additional command being executed without receiving a separate command to access the second location in the memory”. This limitation is not supported by the application as originally filed. Applicant identifies paragraph 0010 as providing support for this amendment. Paragraph 0010 states “Advantageously, the command trigger unit is programmable in an application-specific manner, such that an application developer and/or a compiler is able to predefine how execution of one processing-in-memory command will trigger execution of additional processing-in-memory commands to best suit the needs of the application.” However, just because execution of one command will trigger the execution, that does not mean that separate commands do not also need to be received. For example, that same sentence states that “the command trigger unit is programmable in an application-specific manner”, which implies that at least one additional command that programs the command trigger unit must be received. The limitation in question is a negative limitation. The combination of an absence of a positive recitation of this feature and teachings in the specification that imply other commands are received that are not positively recited lead the Examiner to conclude that this limitation is not supported by the application as originally filed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9, 10, 13-17, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2022/0157371).
In regards to claim 1, Kim teaches a device comprising:
a memory (semiconductor device 1000, figure 2) storing a tracking table (register array 110, figure 3) and including an in-memory processor (“When a read operation is performed on an operand, the processing circuit 200 may perform a predetermined in-memory processing in response to the read operation.”, paragraph 0036) configured to:
receive a command (“To this end, the memory controller sets a type of the request as a read request and an address as the address B of the second operand b, and provides the read request to the semiconductor device 1000.”, paragraph 0176);
execute the command by:
accessing data stored at a first location in the memory (“Accordingly, the data output from the bank 11 is stored in the second operand register 212 as the second operand b.”, paragraph 0177); and
generating an output by performing at least one operation using the data stored at the first location in the memory (“Accordingly, the data output from the bank 11 is stored in the second operand register 212 as the second operand b.”, paragraph 0177); and
in response to executing the command (“When a read operation is performed on an operand, the processing circuit 200 may perform a predetermined in-memory processing in response to the read operation.”, paragraph 0036; “Accordingly, when a read command for in-memory processing is performed, one of the first or second register enable signals M1V or M2V activates, which causes the match signal MATCH to activate, and as a result data output from the bank 11 is provided to the processing circuit 200.”, paragraph 0120):
identify that an entry of the tracking table associates the first location in the memory (“For example, in FIG. 11, the first match signal MATCH1 is activated during a period between t0 and t1 in which the read command RD is activated and an address A that is the same as that stored in the first register 111 is applied by the address input circuit 60. Since the second match signal MATCH2 and the third match signal MATCH3 are generated similarly, the description thereof will not be repeated.”, paragraphs 0099-0100) with at least one additional command (“As illustrated in FIG. 9, when the setting signal D is ‘0000’, the processing circuit 200 performs a multiplication and accumulation (MAC) operation”, paragraph 0131) that involves accessing different data stored at a second location in the memory (first operand register 211, figure 10), wherein the first location and the second location are different storage locations (bank 11 is different than first operand register 211); and
execute, based on the entry in tracking table, the at least one additional command using the different data stored at the second location in the memory (paragraph 0147; See also figure 9).
In regards to claim 2, Kim further teaches that the at least one operation comprises providing the output to a third location in the memory (“Accordingly, the data output from the bank 11 is stored in the second operand register 212 as the second operand b.”, paragraph 0177), wherein the command is received with information identifying the third location in the memory (“The arithmetic circuit 200 includes a first selection circuit 220 that outputs the second operand b or 1 according to a setting signal D[0], … a second selection circuit 240 that outputs the second operand b, 0, or an accumulated value ACC according to a setting signal D[2:1]”, paragraph 0147) and the at least one additional command is executed in response to writing the output to the third location in the memory (“When a read operation is performed on an operand, the processing circuit 200 may perform a predetermined in-memory processing in response to the read operation.”, paragraph 0036; “Accordingly, when a read command for in-memory processing is performed, one of the first or second register enable signals M1V or M2V activates, which causes the match signal MATCH to activate, and as a result data output from the bank 11 is provided to the processing circuit 200.”, paragraph 0120).
In regards to claim 3, Kim further teaches that the third location in the memory comprises a storage location local to the in-memory processor (Figure 10 shows how the second operand register 212 is part of the processing circuit 200).
In regards to claim 4, Kim further teaches that the at least one operation comprises reading data from the first location in the memory and executing the at least one additional command is performed in response to reading the data from the first location in the memory (“When a read operation is performed on an operand, the processing circuit 200 may perform a predetermined in-memory processing in response to the read operation.”, paragraph 0036; “Accordingly, when a read command for in-memory processing is performed, one of the first or second register enable signals M1V or M2V activates, which causes the match signal MATCH to activate, and as a result data output from the bank 11 is provided to the processing circuit 200.”, paragraph 0120).
In regards to claim 5, Kim further teaches that the command includes a command trigger bit and the in-memory processor executes the at least one additional command in response to the command trigger bit being a predefined value (“Also, the column address comparator 132 outputs the second column comparison signal CC2 by determining whether a column address provided from the address input circuit 60 is the same as an address or included in an address range stored in the second register 112.”, paragraph 0083; “For example, in FIG. 11, the first match signal MATCH1 is activated during a period between t0 and t1 in which the read command RD is activated and an address A that is the same as that stored in the first register 111 is applied by the address input circuit 60. Since the second match signal MATCH2 and the third match signal MATCH3 are generated similarly, the description thereof will not be repeated.”, paragraphs 0099-0100).
In regards to claim 6, Kim further teaches that the at least one additional command is executed in response to the in-memory processor identifying that a condition in the entry of the tracking table is satisfied (“For example, in FIG. 11, the first match signal MATCH1 is activated during a period between t0 and t1 in which the read command RD is activated and an address A that is the same as that stored in the first register 111 is applied by the address input circuit 60. Since the second match signal MATCH2 and the third match signal MATCH3 are generated similarly, the description thereof will not be repeated.”, paragraphs 0099-0100; “Accordingly, when a read command for in-memory processing is performed, one of the first or second register enable signals M1V or M2V activates, which causes the match signal MATCH to activate, and as a result data output from the bank 11 is provided to the processing circuit 200.”, paragraph 0120).
In regards to claim 9, Kim further teaches that the tracking table is stored locally at the in-memory processor or at a storage location in the memory that is accessible by the in-memory processor (“To this end, the semiconductor device 1000 further includes a processing control circuit 100, a processing circuit 200, and a switch circuit 300.”, paragraph 0030; “The processing control circuit 100 includes a register array 110, a register control circuit 120, and a command identification circuit 130.”, paragraph 0043).
In regards to claim 10, Kim further teaches that the tracking table is programmed by a host from which the command is received (“Next, a second register 112 is set at S120. To this end, the memory controller sets a type of request as a write request, an address as the second register address ADDR2, and a data DATA as the address B of the second operand b or an address range including the address B, and provides the write request to the semiconductor device 1000.”, paragraphs 0164-0165).
In regards to claim 13, Kim further teaches that the in-memory processor is configured to execute the at least one additional command independent of traffic on a connection between the in-memory processor and a host from which the command is received (“This indicates that the semiconductor device 1000 of the present embodiment does not require a special state or a special command for in-memory processing.”, paragraph 0127).
In regards to claim 14, Kim further teaches a different in-memory processor (“In another embodiment, as many register arrays 110 as the number of banks may exist, and one register array 110 may be used only for one processing circuit 200.”, paragraph 0070) configured to:
receive the command (“To this end, the memory controller sets a type of the request as a read request and an address as the address B of the second operand b, and provides the read request to the semiconductor device 1000.”, paragraph 0176);
generate a different output by executing the command (“In such an embodiment, the register array 110 may be independently set for each bank or each processing circuit.”, paragraph 0071); and
execute another command that is different than the at least one additional command based on a different entry of the tracking table, the different entry being associated with the different output (“In such an embodiment, the register array 110 may be independently set for each bank or each processing circuit.”, paragraph 0071; See also figure 9).
In regards to claim 15, Kim teaches a device comprising:
a host (memory controller, paragraph 0176) configured to:
send a command (“To this end, the memory controller sets a type of the request as a read request and an address as the address B of the second operand b, and provides the read request to the semiconductor device 1000.”, paragraph 0176) for execution by an in-memory processor (“When a read operation is performed on an operand, the processing circuit 200 may perform a predetermined in-memory processing in response to the read operation.”, paragraph 0036); and
cause the in-memory processor to:
execute the command by:
accessing data stored at a first location in a memory (“Accordingly, the data output from the bank 11 is stored in the second operand register 212 as the second operand b.”, paragraph 0177); and
generating an output by performing at least one operation using the data stored at the first location in the memory (“Accordingly, the data output from the bank 11 is stored in the second operand register 212 as the second operand b.”, paragraph 0177); and
in response to executing the command (“When a read operation is performed on an operand, the processing circuit 200 may perform a predetermined in-memory processing in response to the read operation.”, paragraph 0036; “Accordingly, when a read command for in-memory processing is performed, one of the first or second register enable signals M1V or M2V activates, which causes the match signal MATCH to activate, and as a result data output from the bank 11 is provided to the processing circuit 200.”, paragraph 0120):
identify that an entry of a tracking table associates the first location in the memory (“For example, in FIG. 11, the first match signal MATCH1 is activated during a period between t0 and t1 in which the read command RD is activated and an address A that is the same as that stored in the first register 111 is applied by the address input circuit 60. Since the second match signal MATCH2 and the third match signal MATCH3 are generated similarly, the description thereof will not be repeated.”, paragraphs 0099-0100) with an additional command (“As illustrated in FIG. 9, when the setting signal D is ‘0000’, the processing circuit 200 performs a multiplication and accumulation (MAC) operation”, paragraph 0131) that involves accessing different data stored at a second location in the memory (first operand register 211, figure 10), wherein the first location and the second location are different storage locations (bank 11 is different than first operand register 211); and
execute, based on the entry in tracking table, the additional command using the different data stored at the second location in the memory (paragraph 0147; See also figure 9).
In regards to claim 16, Kim further teaches that the host is further configured to program the tracking table by populating the tracking table with entries prior to sending the command (paragraphs 0162-0170).
In regards to claim 17, Kim further teaches a memory controller (row control circuit 20, column control circuit 30, and processing control circuit 100, figure 2), wherein the host is configured to send the command to the memory controller for scheduling at the in-memory processor with an indication that the command is configured to cause execution of the additional command locally at the in-memory processor (“For example, in FIG. 11, the first match signal MATCH1 is activated during a period between t0 and t1 in which the read command RD is activated and an address A that is the same as that stored in the first register 111 is applied by the address input circuit 60. Since the second match signal MATCH2 and the third match signal MATCH3 are generated similarly, the description thereof will not be repeated.”, paragraphs 0099-0100, the address being the indication).
In regards to claim 19, Kim further teaches that the in- memory processor is caused to execute the additional command independent of receiving the additional command via a connection between the host and the in- memory processor after receiving the command via the connection between the host and the in-memory processor (“This indicates that the semiconductor device 1000 of the present embodiment does not require a special state or a special command for in-memory processing.”, paragraph 0127).
In regards to claim 20, Kim teaches a method comprising:
receiving, at an accelerator, a command from a host (“To this end, the memory controller sets a type of the request as a read request and an address as the address B of the second operand b, and provides the read request to the semiconductor device 1000.”, paragraph 0176; “When a read operation is performed on an operand, the processing circuit 200 may perform a predetermined in-memory processing in response to the read operation.”, paragraph 0036);
executing, by the accelerator, the command by:
accessing data stored at a first location in a memory (“Accordingly, the data output from the bank 11 is stored in the second operand register 212 as the second operand b.”, paragraph 0177); and
generating an output by performing at least one operation using the data stored at the first location in the memory (“Accordingly, the data output from the bank 11 is stored in the second operand register 212 as the second operand b.”, paragraph 0177); and
in response to executing the command (“When a read operation is performed on an operand, the processing circuit 200 may perform a predetermined in-memory processing in response to the read operation.”, paragraph 0036; “Accordingly, when a read command for in-memory processing is performed, one of the first or second register enable signals M1V or M2V activates, which causes the match signal MATCH to activate, and as a result data output from the bank 11 is provided to the processing circuit 200.”, paragraph 0120):
identifying, by the accelerator, that an entry of a tracking table associates the first location in the memory (“For example, in FIG. 11, the first match signal MATCH1 is activated during a period between t0 and t1 in which the read command RD is activated and an address A that is the same as that stored in the first register 111 is applied by the address input circuit 60. Since the second match signal MATCH2 and the third match signal MATCH3 are generated similarly, the description thereof will not be repeated.”, paragraphs 0099-0100) with at least one additional command (“As illustrated in FIG. 9, when the setting signal D is ‘0000’, the processing circuit 200 performs a multiplication and accumulation (MAC) operation”, paragraph 0131) that involves accessing different data stored at a second location in the memory (first operand register 211, figure 10), wherein the first location and the second location are different storage locations (bank 11 is different than first operand register 211); and
executing, by the accelerator and based on the entry in tracking table, the at least one additional command using the different data stored at the second location in the memory (paragraph 0147; See also figure 9), the at least one additional command being executed without receiving a separate command to access the second location in the memory (“The second register enable signal M2V activates the second operand register 212 to latch data when the second match signal MATCH2 and the valid data signal DV are activated.”, paragraph 0109; “The delay register 213 operates in synchronization with the clock signal CLK, but activation is controlled according to the second register enable signal M2V. The output signal M2D of the delay register 213 has a form in which the second register enable signal M2V is delayed for a predetermined time.”, paragraphs 0150-0151; “The accumulation register 280 accumulates the output of the third selection circuit 270 to a previously stored value in synchronization with the clock signal CLK when the output signal M2D of the delay register 213 is activated.”, paragraph 0155; These steps show how the value gets stored in the accumulation register independent of whether a MATCH1 read occurs).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0157371) in view of Tseng et al. (“Data-triggered Multithreading for Near-Data Processing”).
In regards to claim 7, Kim teaches claim 6. Kim fails to teach that the condition in the entry of the tracking table is satisfied responsive to the first location in the memory storing a value indicated in the entry of the tracking table. Tseng teaches that the condition in the entry of the tracking table is satisfied responsive to the first location in the memory storing a value indicated in the entry of the tracking table (“The DTM model allows the user to declare a data trigger after an assignment statement, by which the system only triggers multithreaded execution when the destination value of the assignment changes.”, section 2, paragraph 2) in order “to alleviate the problem of generating unwanted threads” (section 2, paragraph 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim with Tseng such that the condition in the entry of the tracking table is satisfied responsive to the first location in the memory storing a value indicated in the entry of the tracking table in order “to alleviate the problem of generating unwanted threads” (id.).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0157371) in view of Lee et al. (US 2020/0293319).
In regards to claim 8, Kim further teaches a memory controller (row control circuit 20, column control circuit 30, and processing control circuit 100, figure 2). Kim fails to teach that the in-memory processor is further configured to instruct the memory controller to delay scheduling of additional commands in response the at least one additional command being executed based on the entry of the tracking table. Lee teaches that the in-memory processor is further configured to instruct the memory controller to delay scheduling of additional commands in response the at least one additional command being executed based on the entry of the tracking table (“In addition, according to an embodiment of the inventive concept, when a transaction for the memory operation is generated by the memory controller 100 while the memory device 200 processes an operation, the memory operation may be delayed until operation processing has completed or for a time spent on stopping an operation processing.”, paragraph 0042). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim with Lee such that the in-memory processor is further configured to instruct the memory controller to delay scheduling of additional commands in response the at least one additional command being executed based on the entry of the tracking table in order to avoid collisions.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0157371) in view of Ham et al. (US 2023/0195651).
In regards to claim 11, Kim teaches claim 10. Kim fails to teach that the in-memory processor is further configured to transmit a notification to the host indicating performance of the at least one additional command in response to executing the at least one additional command. Ham teaches that the in-memory processor is further configured to transmit a notification to the host indicating performance of the at least one additional command in response to executing the at least one additional command (“Results of the normalization and ReLU calculations at S16 may be provided to the GPU 11 as read replies at S153.”, paragraph 0072) so that the results can be used to perform matrix multiplication (paragraph 0073). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim with Ham such that the in-memory processor is further configured to transmit a notification to the host indicating performance of the at least one additional command in response to executing the at least one additional command so that the results can be used to perform matrix multiplication (id.).
In regards to claim 12, Kim teaches claim 1. Kim fails to teach that the entry of the tracking table includes a field describing a threshold number of times the at least one additional command is to be executed, wherein the in-memory processor is configured to execute the at least one additional command responsive to determining that the threshold number of times the at least one additional command is to be executed has not been exceeded. Ham teaches that the entry of the tracking table includes a field describing a threshold number of times the at least one additional command is to be executed (“The NDP kernel table includes an NDP kernel ID field, a code location field, a number of static registers field, a number of dynamic registers field, a number of requests per micro-context field, and a number of remaining micro-contexts field.”, paragraph 0112), wherein the in-memory processor is configured to execute the at least one additional command responsive to determining that the threshold number of times the at least one additional command is to be executed has not been exceeded (“When the first write request packet is processed, the number of remaining packets corresponding to the NDP kernel ID 0 and pivot index 0 in the micro-context table is decreased by 1 and set to 3.”, paragraph 0166; “In response to the number of remaining packets for micro-context 0 being set to 0, the number of remaining micro-contexts corresponding to NDP kernel ID 0 in the NDP kernel table is decreased by 1 and set to 1.”, paragraph 0173; “Thereafter, four write request packets corresponding to micro-context 1 may be processed in a similar manner.”, paragraph 0174). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim with Ham such that the entry of the tracking table includes a field describing a threshold number of times the at least one additional command is to be executed, wherein the in-memory processor is configured to execute the at least one additional command responsive to determining that the threshold number of times the at least one additional command is to be executed has not been exceeded in order to support a particular data size.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0157371) in view of Murphy (US 2019/0266105).
In regards to claim 18, Kim teaches claim 15. Kim fails to teach that the host is further configured to execute at least one operation while the in-memory processor is executing the additional command. Murphy teaches that the host is further configured to execute at least one operation while the in-memory processor is executing the additional command (“Moreover, in some embodiments, memory processing circuitry implemented in a memory module may autonomously perform data processing operations, for example, without receiving a trigger (e.g., instruction) from host processing circuitry. In fact, in some embodiments, the memory processing circuitry may opportunistically perform data processing operations, for example, while the host processing circuitry is performing other tasks.”, paragraph 0030; “For example, the memory processing circuitry may pre-process data being retrieved to the host processing circuitry and/or post-process data received from the host processing circuitry for storage, thereby enabling processing performed by the host processing circuitry to be reduced and, thus, freeing the host processing circuitry for other tasks.”, paragraph 0020) thereby “improving operational efficiency of computing systems” (paragraph 0020). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim with Murphy such that the host is further configured to execute at least one operation while the in-memory processor is executing the additional command thereby “improving operational efficiency of computing systems” (id.).
Response to Arguments
Applicant's arguments filed 5 August 2026 have been fully considered but they are not persuasive.
In response to the arguments regarding claim 1, Kim’s second register 112 stores an address that associates that address with at least one additional command, specifically the command specified in the fourth register 114 shown in figure 9. The registers are not unrelated data fields, but specify addresses and commands associated with the processing-in-memory operation. By accessing the address specified in the second register 112, the command specified in the fourth register 114 is triggered and the result is stored in the accumulation register. Kim’s command does not require reading the first operand. The operation of the circuit show in figure 10 of Kim uses the 1st Operand Register 211 regardless of what data has been stored there.
The MAC operation of Kim is an additional command that is triggered. The MAC operation is different from a read operation and can therefore be considered an additional command. The MAC operation is triggered in the sense that when MATCH2 occurs due to the address matching the second register 112, the M2V signal occurs causing the circuit in figure 10 to perform the operation and store the output in the accumulation register.
In response to the arguments regarding claim 2, the Examiner disagrees. The operands are a location in memory. Kim teaches that the semiconductor device 1000 is a memory device (paragraph 0024). The Examiner is considering the entire memory device 1000 to be the memory. Figure 2 shows that the semiconductor device includes processing circuit 200. Figure 10 shows that the 2nd operand register 212 is part of processing circuit 200. Thus, the 2nd operand register 212 is a location in memory. The setting signals D are inputs to multiplexers 220 and 240, which select between the 2nd operand register 212 and other values, thereby identifying the location in memory. In the first clock cycle after M2V is triggered, the data is latched into the 2nd operand register 212. In the following clock cycle, the processing occurs, and the output is latched into the accumulation register 280. Thus, the processing can be considered to be in response to writing the output to the third location in the memory.
In response to the arguments regarding claim 5, the Examiner is considering one of the bits in the incoming column address to be the claimed command trigger bit. This is one of the bits that is used in determining whether to execute the additional command. The use of the word “includes” makes it clear that the claim is open-ended. Thus, the consideration of other bits in the incoming addresses are not prohibited by the claim language.
In response to the arguments regarding claim 8, Lee teaches that the memory operation may be delayed until operation processing has completed (paragraph 0042). Lee further teaches that “the operation processing result may be transmitted to the host HOST” (paragraph 0076). Furthermore, Lee’s PIM includes loops, branches, and jumps (paragraphs 0113-0114) which makes the latency unpredictable. This shows that Lee delays additional commands until the result of the additional command is transmitted to the host.
In response to the arguments regarding claim 15, as explained above in regards to claim 1, Kim’s register array 110 does contain such entries. Kim’s memory controller does cause the semiconductor device 1000 to automatically execute the MAC processing based on an entry that associates the address with the MAC processing.
In response to the arguments regarding claim 20, the Examiner is considering Kim’s 1st operand register 211 as teaching the claimed 2nd location in the memory. Kim’s semiconductor device 1000 does not require issuing the 1st read request S210 to access the 1st operand register 211. The 1st operand register 211 is accessed as part of performing the MAC processing in response to the 2nd read request S220.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 28 September 2026
