DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant has submitted the following:
Claims 1-20 are pending examination;
Claims 1, 9, and 15 are newly amended.
Response to Arguments
Applicant's arguments filed 01/30/2026 have been fully considered but they are not persuasive.
Applicant argues that, regarding rejections under 35 USC 101, newly amended independent claims 1, 9, and 15 recite limitations that cannot be performed in the human mind, and therefore is not mental processes.
Examiner respectfully disagrees. The limitation “generating, by at least one processor, a plurality of wafer level maps by measuring the wafer, using a photo level measuring device, after each one of a plurality of process operations is performed on the wafer” amounts to collecting information, analyzing it, and displaying certain results of said analysis (MPEP 2106.04(a)(2).III.A). Further, the use of at least one processor amounts to the use of a generic computer to perform the mental processes (MPEP 2106.04(a)(2).III.C). Examiner notes that the generation of a plurality of wafer level maps could be performed in the human mind with a physical aid (MPEP 2106.04(a)(2).B: “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.”). (see detailed action under Claim Rejections 35 USC 101, below).
Applicant argues that none of the prior art teaches the limitations of newly amended independent claims 1, 9, and 15.
Examiner respectfully disagrees. Previously cited Zhang teaches an analogous method of detecting defects of a wafer. Previously cited Chen teaches an analogous method, comprising:
measuring the wafer after each one of a plurality of process operations is performed on the wafer and indicating an earliest one of the plurality of process operations in time after which the defect occurred ([0026] lines 6-25, “At block 104, circuit performance (CP) tests, in-line defect tests, bin tests, wafer acceptance tests (WAT or electrical test method) and/or defect tests can be performed by applying the appropriate test criteria to the fabricated wafers. For example, a defect map can be formed using KLA-Tencor equipment. At block 106, a test data set is collected from testing the fabricated wafers at block 104. At block 105, a respective wafer map is formed for each of the wafers based on the collected test data set. For example, during the fabrication process of the plurality of semiconductor wafers, various in-process layers of each of the plurality of wafers can be verified by an in-line defect test to collect a test data set. A respective wafer map can be formed for each wafer using the test data collected and/or measured at various points on various in-line process layers (e.g. film deposition layers, lithography layers, etching layers, diffusion layers) of the wafer. In some embodiments, wafer maps can be generated based on a test data set measured at various points at each of the various in-process layers during fabrication of each of the plurality of wafers.”; [0027] lines 17-21, “At block 112, if no objects are determined to be present on a wafer map, then the wafer is determined to be suitable for use and no further processing is performed on the wafer map. In some embodiments, the non-defect wafer maps can be discarded.”). The in-line or in-process steps are the process operations (“e.g. film deposition layers, lithography layers, etching layers, diffusion layers”). The wafer map generated at each of the various in-process layers during fabrication, where non-defect wafer maps are discarded, is the detection of the earliest process operation after the defect occurred.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention in each of these claims is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Specifically, representative Claim 1 recites:
“A method of detecting defects of a wafer, the method comprising:
generating, by at least one processor, a plurality of wafer level maps by measuring the wafer, using a photo level measuring device, after each one of a plurality of process operations is performed on the wafer;
generating, by the at least one processor, a composite wafer map comprising defect points by combining the plurality of wafer level;
sorting, by the at least one processor, the defect points according to defect clusters based on positions of the defect points included in the composite wafer map; and
detecting, by the at least one processor, for each of the defect clusters, an initial process operation in which a defect occurred, from among the plurality of process operations, based on operation information indicating an earliest one of the plurality of process operations in time after which the defect occurred.”
The claim limitations considered to fall within in the abstract idea are highlighted in bold font above; the remaining features are “additional elements.”
Step 1 of the subject matter eligibility analysis entails determining whether the claimed subject matter falls within one of the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: process, machine, manufacture, or composition of matter. Claim 1 recites a process and is therefore falls within a statutory category.
Step 2A, Prong One of the analysis entails determining whether the claim recites a judicial exception such as an abstract idea. Under a broadest reasonable interpretation, the highlighted portion of claim 1 comprises process steps that fall within the abstract idea judicial exception. Specifically, under the 2019 Revised Patent Subject matter Eligibility Guidance, the highlighted subject matter falls within the mental processes category.
Individually and collectively, the steps:
“generating […] a plurality of wafer level maps by measuring the wafer, using a photo level measuring device, after each one of a plurality of process operations is performed on the wafer”;
“generating […] a composite wafer map comprising defect points by combining a plurality of wafer level maps generated by measuring the wafer according to respective process operations”;
“sorting […] the defect points according to defect cluster”; and
“detecting […] an initial process operation in which a defect occurred, from among the plurality of process operations, based on operation information indicating an earliest one of the plurality of process operations in time after which the defect occurred.”
may be performed as mental processes. Generating a plurality of wafer level maps by measuring the wafer is collecting information and the display of certain information collected and analyzed, which may be performed as mental processes. Generating a composite wafer map is the output of analysis, which may be performed as mental processes. Sorting the defect points is an analysis of information, and may be performed as mental processes. Detecting an initial process operation is an identification step, which may be performed as mental processes. The type of high-level information collecting and analyzing data recited in these elements has been found by the Federal Circuit to constitute patent ineligible matter (see Electric Power Group v. Alstom, S.A., 830 F.3d 1350, 1353-54, 119 USPQ2d 1739, 1741-42 (Fed. Cir. 2016), a claim to "collecting information, analyzing it, and displaying certain results of the collection and analysis," where the data analysis steps are recited at a high level of generality such that they could practically be performed in the human mind).
Similar limitations comprise the mental processes type abstract idea recited by independent claims 9 and 15.
Step 2A, Prong Two of the analysis entails determining whether a claim includes additional elements that integrate the recited judicial exception (e.g., abstract idea) into a practical application. In view of the various considerations encompassed by the Step 2A, Prong Two analysis, claim 1 does not include additional elements that integrate the recited abstract idea into a practical application. Based on the individual and collective limitations of claim 1, applying a broadest reasonable interpretation, the most significant of such considerations appear to include: improvements to the functioning of a computer, or to any other technology or technical field (MPEP 2106.05(a)); applying the judicial exception with, or by use of, a particular machine (MPEP 2106.05(b)); and effecting a transformation or reduction of a particular article to a different state or thing (MPEP 2106.05(c)).
Regarding improvements to the functioning of a computer or other technology, none of the “additional elements” in any combination appear to integrate the abstract idea to technologically improve any aspect of a system that may be used to implement the highlighted steps such a generic computer. Any alleged improvement would be an improvement in the abstract idea, and thus not an improvement in technology (MPEP 2106.05(a).II “However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology.”.). The additional element of “at least one processor” is a generic computer, and the claim amounts to mere instructions to implement the abstract idea in a generic computer (MPEP 2106.05(f)).
Regarding application of the judicial exception with, or by use of, a particular machine, none of the “additional elements” in any combination appear to integrate the abstract idea in a particularized manner of implementing the abstract idea process steps. Instead the claim as a whole amounts to analyzing information (“generating”, “sorting”, and “detecting” steps).
Regarding effectuation of a transformation or reduction of a particular article to a different state or thing, the claim includes no such transformation or reduction. Instead the claim as a whole amounts to analyzing information (“generating”, “sorting”, and “detecting” steps). The composite wafer map generated is a representation of information and not a particular article that is transformed.
Independent claim 9 recites additional elements, including “an apparatus for detecting defects of a wafer”, “a memory storing a program”, and “a processor”. The additional elements are recited generically and not utilized in a particular manner. The additional elements amount to mere instructions to implement the process steps on a generic computer (see MPEP 2106.05(f)), and therefore is not an improvement in technology. None of the additional elements, alone or in combination, amount to a transformation of a particular article. Therefore, independent claim 9 does not integrate the judicial exception into a practical application.
Independent claim 15 recites additional elements, including “a non-transitory computer-readable storage medium” and “a processor”. The additional elements are recited generically and not utilized in a particular manner. The additional elements amount to mere instructions to implement the process steps on a generic computer (see MPEP 2106.05(f)), and therefore is not an improvement in technology. None of the additional elements, alone or in combination, amount to a transformation of a particular article. Therefore, independent claim 15 does not integrate the judicial exception into a practical application.
The above additional elements, considered individually and in combination with the claim elements reciting an abstract idea do not reflect an improvement to other technology or technical field, and, therefore, do not integrate the judicial exception into a practical application. Therefore, the claims are directed to a judicial exception and require further analysis under Step 2B.
Regarding Step 2B, independent claims 1, 9 and 16, do not include additional elements that are sufficient to amount to significantly more than the judicial exception because they are generically recited and are well-understood/conventional in the relevant art as evidenced by the prior art of record as indicated in the rejections under 35 U.S.C. §103.
Independent claims 1, 9, and 15 are therefore not patent eligible.
Dependent claim 2-8, 10-14, and 16-20 provide additional features/steps which are part of the process steps that includes the abstract idea of the independent claims (Step 2A, Prong One). None of dependent claims 2-8, 10-14, and 16-20 recite additional elements that integrate the abstract idea into practical application (Step 2A, Prong Two).
Claims 2, 10, and 16 recite additional details on the sorting step, including setting a first defect point as a reference point, adding the reference point to a cluster, searching for an adjacent point, and adding the adjacent point to the cluster, which may be performed as mental processes. Claims 3-7, 11-13, and 17-19 recite further details on the sorting and searching steps, which may be performed as mental processes. Claims 8, 14, and 20 further recite extracting a defect point, which is an analysis which may be performed as mental processes.
Claims 2-8, 10-14, and 16-20 all fail the “significantly more” test under the step 2B for the same reasons as discussed with regards to the independent claims.
Therefore, dependent claims 2-8, 10-14, and 16-20 are also ineligible subject matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-12, 14-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zheng et al. (US 20220223481 A1, previously cited) in view of Chen et al. (US 20130288403 A1, previously cited).
Regarding claim 1, Zheng teaches A method of detecting defects of a wafer (Abstract), the method comprising:
generating([0090] “According to the embodiment of the present disclosure, the number of defects, the types of defects, and the defect locations on each of the wafers are detected by a conventional method. The defects such as crystal original particles, pits, particles, scratches, bright field defects, and slips can be detected by laser scanning (such as using KLA SP series and Hitachi LS series of a laser scanning apparatus), SIRD detection, infrared scanning, or the like, besides, air holes are detected by infrared scanning, X-ray, or the like. The detection data of forgoing defects is output from the apparatus. The detection data may be images of the wafers or all defect information documents. In this method, the defect distribution map can be constructed directly based on the images (the defect image, and a detection image) of the forgoing wafers or all defect information documents.”). The conventional methods for forming images (e.g. infrared scanning, laser scanning apparatus, X-ray) are the photo level measuring device, which generate the plurality of wafer level maps (i.e. image of wafer, “defect image and a detection image”);
generating a composite wafer map ([0048] lines 4-9, “According to an embodiment of the present disclosure, the method includes: providing at least one stacked wafer; constructing a defect distribution map based on a defect information on each of the wafers, where, the defect information includes the number of defects, types of the defects, and locations of the defects”). The defect distribution map is the composite wafer map
comprising defect points ([0029] lines 2-3, “the defect region is formed by a plurality of defect points.”) by combining the plurality of wafer level maps ([0020] lines 3-9, “acquiring images of the plurality of wafers that are from the same ingot, and positioning points are formed on edges of the plurality of wafers, respectively; stereoscopically overlapping and processing the images of the plurality of wafers based on the positioning points, thereby acquiring an overlapped image of the plurality of wafers”; [0063] lines 4-9, “the 3D defect distribution map corresponds to one cylindrical 3D space, and a specific size of the 3D defect distribution map is the same as a volume occupied by the plurality of stacked wafers, where, all the defects on the plurality of wafers and locations of the defects are marked.”). The overlapping of images, creating the 3D defect distribution map, is the combining of a plurality of wafer level maps.;
sorting the defect points according to defect clusters based on positions of the defect points included in the composite wafer map ([0091] lines 11-16, “searching for defects on the overlapped images to determine whether there are continuous defects, wherein, the continuous defects occur at the same location on at least two adjacent wafers, presence of the continuous defects is an indication that the defect originates from the preparation and processing process of the wafer”; see determination of continuous defects of paragraphs [0023] and [0026]).
Zheng does not teach the method, comprising:
generating, by at least one processor, a plurality of wafer level maps, after each one of a plurality of process operations is performed on the wafer;
detecting, by at least one processor, for each of the defect clusters an initial process operation in which a defect occurred, from among the plurality of process operations indicating an earliest one of the plurality of process operations in time after which the defect occurred.
Chen teaches an analogous method of detecting defects on a wafer (Abstract), comprising:
generating, by at least one processor (Fig. 10, processor(s) 1002), a plurality of wafer level maps, after each one of a plurality of process operations is performed on the wafer . ([0026] lines 6-25, “At block 104, circuit performance (CP) tests, in-line defect tests, bin tests, wafer acceptance tests (WAT or electrical test method) and/or defect tests can be performed by applying the appropriate test criteria to the fabricated wafers. For example, a defect map can be formed using KLA-Tencor equipment. At block 106, a test data set is collected from testing the fabricated wafers at block 104. At block 105, a respective wafer map is formed for each of the wafers based on the collected test data set. For example, during the fabrication process of the plurality of semiconductor wafers, various in-process layers of each of the plurality of wafers can be verified by an in-line defect test to collect a test data set. A respective wafer map can be formed for each wafer using the test data collected and/or measured at various points on various in-line process layers (e.g. film deposition layers, lithography layers, etching layers, diffusion layers) of the wafer. In some embodiments, wafer maps can be generated based on a test data set measured at various points at each of the various in-process layers during fabrication of each of the plurality of wafers.”);
detecting, by at least one processor (Fig. 10, processor(s) 1002), for each of the defect clusters (Fig. 1, wafer finger print; cluster algorithm of [0046]-[0047]) an initial process operation in which a defect occurred, from among the plurality of process operations indicating an earliest one of the plurality of process operations in time after which the defect occurred. ([0026] lines 6-25, “At block 104, circuit performance (CP) tests, in-line defect tests, bin tests, wafer acceptance tests (WAT or electrical test method) and/or defect tests can be performed by applying the appropriate test criteria to the fabricated wafers. For example, a defect map can be formed using KLA-Tencor equipment. At block 106, a test data set is collected from testing the fabricated wafers at block 104. At block 105, a respective wafer map is formed for each of the wafers based on the collected test data set. For example, during the fabrication process of the plurality of semiconductor wafers, various in-process layers of each of the plurality of wafers can be verified by an in-line defect test to collect a test data set. A respective wafer map can be formed for each wafer using the test data collected and/or measured at various points on various in-line process layers (e.g. film deposition layers, lithography layers, etching layers, diffusion layers) of the wafer. In some embodiments, wafer maps can be generated based on a test data set measured at various points at each of the various in-process layers during fabrication of each of the plurality of wafers.”; [0027] lines 17-21, “At block 112, if no objects are determined to be present on a wafer map, then the wafer is determined to be suitable for use and no further processing is performed on the wafer map. In some embodiments, the non-defect wafer maps can be discarded.”). The in-line or in-process steps are the process operations (“e.g. film deposition layers, lithography layers, etching layers, diffusion layers”). The wafer map generated at each of the various in-process layers during fabrication, where non-defect wafer maps are discarded, is the detection of the earliest process operation after the defect occurred.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Zheng to include the process operations of Chen because the inclusion of the process operations in which the defect occurs would yield predictable and advantageous results, including identifying operations which may be causing defects in the wafer and potentially correcting the operation to prevent future defects.
Regarding claim 2, Zheng in view of Chen teaches The method of claim 1.
Zheng further teaches the method, wherein the sorting of the defect points according to the defect clusters comprises:
adding the reference defect point to a first defect cluster of the defect clusters; searching for a defect point that is adjacent to the reference defect point, from among the defect points; and adding the defect point that is adjacent to the reference defect point to the first defect cluster of the defect clusters ([0083] lines 1-12, “Therefore, when the defects with the same defect location on the different wafers are located inside the wafer, in an embodiment of the present disclosure, a plurality of densely distributed defects on one wafer are regarded as one defect region. If the defect region appears in the same location of the plurality of the wafers, the plurality of defect regions are defects with the same defect location on the different wafers. While two adjacent defect regions are not completely the same, it can be determined whether the defects are the same defects with the same defect location on the different wafers based on the differences of the coordinates of the center point of the defect region.”);
Zheng does not teach the method, comprising: setting a first defect point, which is selected from among the defect points included in the composite wafer map, as a reference defect point
Chen teaches an analogous method of sorting points according to defect clusters (clustering algorithm of paragraph [0046]), comprising:
setting a first defect point (Fig. 1, steps 110, 115), which is selected from among the defect points included in the composite wafer map ([0027] lines 3-7, “An object, as defined herein, is a collection of test data on a wafer map formed for a respective wafer that is indicative of wafer failure. In various embodiments, an object can be a collection of test data formed by two or more adjacent failure die.”), as a reference defect point (Fig. 1, step 115; [0030] lines 14-15, “an object index can define the relative position or percent coverage of the object relative to the wafer map.”; [0031] lines 1-4, “one or more respective object indices for selecting a respective object on each of the respective selected wafer maps are selected at block 115.”).The object index, defining a position on the wafer, is the selected defect point and the respective object index is the reference defect point.
Regarding claim 3, Zheng in view of Chen teaches The method of claim 2.
Chen further teaches the method, wherein the searching for the defect point that is adjacent to the reference defect point comprises:
determining a distance between the reference defect point and each of the defect points included in the composite wafer map (Chen [0046] lines 15-24 “a respective wafer fingerprint can be formed for each of the respective selected wafer maps using the formula D.sub.min(C.sub.i, C.sub.j)=min d(a,b) where a.epsilon.Ci, b.epsilon.Cj where d again represents a distance (e.g. Euclidean distance) between i and j, two points in pattern clusters C.sub.i and C.sub.j and D.sub.min represents the cluster distance. In this algorithm, the distance of the closest points of the two clusters can be compared. If the computed cluster distance in either algorithm is below a certain predetermined threshold, then the two clusters are completely merged.”); and
extracting, from the defect points, a defect point that is located at a distance from the reference defect point that is less than or equal to a critical threshold value (Chen: lines 21-24, “If the computed cluster distance in either algorithm is below a certain predetermined threshold, then the two clusters are completely merged.”). The merging of clusters that are below a predetermined threshold is the extracting a defect point that is located at a distance from the reference point that is less than or equal to a critical threshold value.
Regarding claim 4, Zheng in view of Chen teaches The method of claim 3.
Chen further teaches the method, wherein the distance is determined using a Lp norm value regarding a position of the reference defect point and respective positions of the defect points (Chen: [0046] lines 21-24,“If the computed cluster distance in either algorithm is below a certain predetermined threshold, then the two clusters are completely merged.”). The cluster distance, set by the predetermined threshold, is the norm value.
Regarding claim 5, Zheng in view of Chen teaches The method of claim 3.
Chen further teaches the method, further comprising:
updating the extracted defect point as a second reference defect point; and
searching for the defect point that is adjacent to the second reference defect point (Chen: [0047] lines 9-10, “The algorithm can then iterate until no more merging occurs, at which point all pattern clusters are formed.”). The iteration of the clustering algorithm utilizes the merged data points, including the extracted defect point, as a second reference defect point, in searching for other adjacent points, and therefore searches for a defect point that is adjacent to the second reference defect point.
Regarding claim 6, Zheng in view of Chen teaches The method of claim 2.
Zheng further teaches the method, further comprising determining whether there is at least one unsorted defect point not belonging to any one of the defect clusters from among the defect points (Zheng: [0059] lines 3-8, “determining as a qualified region the predetermined region where the number of the predetermined defects is less than the set threshold, and determining as an unqualified region the predetermined region where the number of the predetermined defects is greater than or equal to the set threshold.”). The qualified region includes at least one unsorted defect point not belonging to any one of the defect clusters.
Regarding claim 9, Zheng teaches An apparatus for detecting defects of a wafer (Abstract), the apparatus comprising:
generate a plurality of wafer level maps by measuring the wafer, using a photo level measuring device ([0090] “According to the embodiment of the present disclosure, the number of defects, the types of defects, and the defect locations on each of the wafers are detected by a conventional method. The defects such as crystal original particles, pits, particles, scratches, bright field defects, and slips can be detected by laser scanning (such as using KLA SP series and Hitachi LS series of a laser scanning apparatus), SIRD detection, infrared scanning, or the like, besides, air holes are detected by infrared scanning, X-ray, or the like. The detection data of forgoing defects is output from the apparatus. The detection data may be images of the wafers or all defect information documents. In this method, the defect distribution map can be constructed directly based on the images (the defect image, and a detection image) of the forgoing wafers or all defect information documents.”). The conventional methods for forming images (e.g. infrared scanning, laser scanning apparatus, X-ray) are the photo level measuring device, which generate the plurality of wafer level maps (i.e. image of wafer, “defect image and a detection image”);
generate a composite wafer map ([0048] lines 4-9, “According to an embodiment of the present disclosure, the method includes: providing at least one stacked wafer; constructing a defect distribution map based on a defect information on each of the wafers, where, the defect information includes the number of defects, types of the defects, and locations of the defects”). The defect distribution map is the composite wafer map
comprising defect points ([0029] lines 2-3, “the defect region is formed by a plurality of defect points.”) by combining a plurality of wafer level maps ([0020] lines 3-9, “acquiring images of the plurality of wafers that are from the same ingot, and positioning points are formed on edges of the plurality of wafers, respectively; stereoscopically overlapping and processing the images of the plurality of wafers based on the positioning points, thereby acquiring an overlapped image of the plurality of wafers”; [0063] lines 4-9, “the 3D defect distribution map corresponds to one cylindrical 3D space, and a specific size of the 3D defect distribution map is the same as a volume occupied by the plurality of stacked wafers, where, all the defects on the plurality of wafers and locations of the defects are marked.”). The overlapping of images, creating the 3D defect distribution map, is the combining of a plurality of wafer level maps. ;
sort the defect points according to defect clusters based on positions of the defect points included in the composite wafer map ([0091] lines 11-16, “searching for defects on the overlapped images to determine whether there are continuous defects, wherein, the continuous defects occur at the same location on at least two adjacent wafers, presence of the continuous defects is an indication that the defect originates from the preparation and processing process of the wafer”; see determination of continuous defects of paragraphs [0023] and [0026]).
Zheng does not teach the apparatus comprising:
a memory storing a program; and
a processor configured to execute the program stored in the memory to:
generate a plurality of wafer level maps by measuring the wafer, after each one of a plurality of process operations is performed on the wafer;
detect, for each of the defect clusters, an initial process operation in which a defect occurred, from among the plurality of process operations, based on operation information indicating an earliest one of the plurality of process operations in time after which the defect occurred.
Chen teaches an analogous apparatus for detecting defects on a wafer (Abstract), comprising:
a memory (Fig. 10, main memory 1004, secondary memory 1008) storing a program ([0060] lines 9-14, “Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible machine readable storage medium for execution by, or to control the operation of, data processing apparatus.”); and
a processor (Fig. 10, processor(s) 1002) configured to execute the program stored in the memory ([0059] lines 1-4, “Processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output.”) to:
generate a plurality of wafer level maps by measuring the wafer, after each one of a plurality of process operations is performed on the wafer ([0026] lines 6-25, “At block 104, circuit performance (CP) tests, in-line defect tests, bin tests, wafer acceptance tests (WAT or electrical test method) and/or defect tests can be performed by applying the appropriate test criteria to the fabricated wafers. For example, a defect map can be formed using KLA-Tencor equipment. At block 106, a test data set is collected from testing the fabricated wafers at block 104. At block 105, a respective wafer map is formed for each of the wafers based on the collected test data set. For example, during the fabrication process of the plurality of semiconductor wafers, various in-process layers of each of the plurality of wafers can be verified by an in-line defect test to collect a test data set. A respective wafer map can be formed for each wafer using the test data collected and/or measured at various points on various in-line process layers (e.g. film deposition layers, lithography layers, etching layers, diffusion layers) of the wafer. In some embodiments, wafer maps can be generated based on a test data set measured at various points at each of the various in-process layers during fabrication of each of the plurality of wafers.”);
detect, for each of the defect clusters (Fig. 1, wafer finger print; cluster algorithm of [0046]-[0047]), an initial process operation in which a defect occurred, from among the plurality of process operations, based on operation information indicating an earliest one of the plurality of process operations in time after which the defect occurred ([0026] lines 6-25, “At block 104, circuit performance (CP) tests, in-line defect tests, bin tests, wafer acceptance tests (WAT or electrical test method) and/or defect tests can be performed by applying the appropriate test criteria to the fabricated wafers. For example, a defect map can be formed using KLA-Tencor equipment. At block 106, a test data set is collected from testing the fabricated wafers at block 104. At block 105, a respective wafer map is formed for each of the wafers based on the collected test data set. For example, during the fabrication process of the plurality of semiconductor wafers, various in-process layers of each of the plurality of wafers can be verified by an in-line defect test to collect a test data set. A respective wafer map can be formed for each wafer using the test data collected and/or measured at various points on various in-line process layers (e.g. film deposition layers, lithography layers, etching layers, diffusion layers) of the wafer. In some embodiments, wafer maps can be generated based on a test data set measured at various points at each of the various in-process layers during fabrication of each of the plurality of wafers.”; [0027] lines 17-21, “At block 112, if no objects are determined to be present on a wafer map, then the wafer is determined to be suitable for use and no further processing is performed on the wafer map. In some embodiments, the non-defect wafer maps can be discarded.”). The in-line or in-process steps are the process operations (“e.g. film deposition layers, lithography layers, etching layers, diffusion layers”). The wafer map generated at each of the various in-process layers during fabrication, where non-defect wafer maps are discarded, is the detection of the earliest process operation after the defect occurred.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Zheng to include the memory, processor, and process operations of Chen because the inclusion of the process operations in which the defect occurs would yield predictable and advantageous results, including identifying operations which may be causing defects in the wafer and potentially correcting the operation to prevent future defects. The memory and processor amount to a generic computer, which is well-known in the art and the utilization of a generic computer to perform the process step would yield predictable results.
Regarding claim 10, Zheng in view of Chen teaches The apparatus of claim 9.
Zheng further teaches the apparatus, wherein the processor is further configured to:
add the reference defect point to a first defect cluster of the defect clusters; search for a defect point of the defect points that is adjacent to the reference defect point; and add the defect point that is adjacent to the reference defect point to the first defect cluster (Zheng: [0083] lines 1-12, “Therefore, when the defects with the same defect location on the different wafers are located inside the wafer, in an embodiment of the present disclosure, a plurality of densely distributed defects on one wafer are regarded as one defect region. If the defect region appears in the same location of the plurality of the wafers, the plurality of defect regions are defects with the same defect location on the different wafers. While two adjacent defect regions are not completely the same, it can be determined whether the defects are the same defects with the same defect location on the different wafers based on the differences of the coordinates of the center point of the defect region.”).
Zheng does not teach the apparatus, comprising:
set a first defect point, which is selected from among the defect points included in the composite wafer map, as a reference defect point
Chen teaches an analogous apparatus for sorting points into defect clusters (clustering algorithm of paragraph [0046]), comprising:
set a first defect point (Chen: Fig. 1, steps 110, 115), which is selected from among the defect points included in the composite wafer map (Chen: [0027] lines 3-7, “An object, as defined herein, is a collection of test data on a wafer map formed for a respective wafer that is indicative of wafer failure. In various embodiments, an object can be a collection of test data formed by two or more adjacent failure die.”), as a reference defect point (Chen: Fig. 1, step 115; [0030] lines 14-15, “an object index can define the relative position or percent coverage of the object relative to the wafer map.”; [0031] lines 1-4, “one or more respective object indices for selecting a respective object on each of the respective selected wafer maps are selected at block 115.”).The object index, defining a position on the wafer, is the selected defect point and the respective object index is the reference defect point;
Regarding claim 11, Zheng in view of Chen teaches The apparatus of claim 10.
Chen further teaches the apparatus, wherein the processor is further configured to:
determine a distance between the reference defect point and each of the defect points included in the composite wafer map (Chen [0046] lines 15-24 “a respective wafer fingerprint can be formed for each of the respective selected wafer maps using the formula D.sub.min(C.sub.i, C.sub.j)=min d(a,b) where a.epsilon.Ci, b.epsilon.Cj where d again represents a distance (e.g. Euclidean distance) between i and j, two points in pattern clusters C.sub.i and C.sub.j and D.sub.min represents the cluster distance. In this algorithm, the distance of the closest points of the two clusters can be compared. If the computed cluster distance in either algorithm is below a certain predetermined threshold, then the two clusters are completely merged.”); and
extract, from the defect points, a defect point located at a distance from the reference defect point that is less than or equal to a critical threshold value (Chen: lines 21-24, “If the computed cluster distance in either algorithm is below a certain predetermined threshold, then the two clusters are completely merged.”). The merging of clusters that are below a predetermined threshold is the extracting a defect point that is located at a distance from the reference point that is less than or equal to a critical threshold value.
Regarding claim 12, Zheng in view of Chen teaches The apparatus of claim 11.
Chen further teaches the apparatus, wherein the processor is further configured to:
update the extracted defect point as a second reference defect point; and
search for a defect point of the defect points that is adjacent to the second reference defect point (Chen: [0047] lines 9-10, “The algorithm can then iterate until no more merging occurs, at which point all pattern clusters are formed.”). The iteration of the clustering algorithm utilizes the merged data points, including the extracted defect point, as a second reference defect point, in searching for other adjacent points, and therefore searches for a defect point that is adjacent to the second reference defect point.
Regarding claim 15, Zheng teaches instructions that, when executed perform operations comprising:
generating a plurality of wafer level maps by measuring a wafer, using a photo level measuring device ([0090] “According to the embodiment of the present disclosure, the number of defects, the types of defects, and the defect locations on each of the wafers are detected by a conventional method. The defects such as crystal original particles, pits, particles, scratches, bright field defects, and slips can be detected by laser scanning (such as using KLA SP series and Hitachi LS series of a laser scanning apparatus), SIRD detection, infrared scanning, or the like, besides, air holes are detected by infrared scanning, X-ray, or the like. The detection data of forgoing defects is output from the apparatus. The detection data may be images of the wafers or all defect information documents. In this method, the defect distribution map can be constructed directly based on the images (the defect image, and a detection image) of the forgoing wafers or all defect information documents.”). The conventional methods for forming images (e.g. infrared scanning, laser scanning apparatus, X-ray) are the photo level measuring device, which generate the plurality of wafer level maps (i.e. image of wafer, “defect image and a detection image”);
generating a composite wafer map ([0048] lines 4-9, “According to an embodiment of the present disclosure, the method includes: providing at least one stacked wafer; constructing a defect distribution map based on a defect information on each of the wafers, where, the defect information includes the number of defects, types of the defects, and locations of the defects”). The defect distribution map is the composite wafer map
comprising defect points ([0029] lines 2-3, “the defect region is formed by a plurality of defect points.”) by combining a plurality of wafer level maps ([0020] lines 3-9, “acquiring images of the plurality of wafers that are from the same ingot, and positioning points are formed on edges of the plurality of wafers, respectively; stereoscopically overlapping and processing the images of the plurality of wafers based on the positioning points, thereby acquiring an overlapped image of the plurality of wafers”; [0063] lines 4-9, “the 3D defect distribution map corresponds to one cylindrical 3D space, and a specific size of the 3D defect distribution map is the same as a volume occupied by the plurality of stacked wafers, where, all the defects on the plurality of wafers and locations of the defects are marked.”). The overlapping of images, creating the 3D defect distribution map, is the combining of a plurality of wafer level maps.;
sorting the defect points according to defect clusters based on positions of the defect points included in the composite wafer map ([0091] lines 11-16, “searching for defects on the overlapped images to determine whether there are continuous defects, wherein, the continuous defects occur at the same location on at least two adjacent wafers, presence of the continuous defects is an indication that the defect originates from the preparation and processing process of the wafer”; see determination of continuous defects of paragraphs [0023] and [0026])
Zheng does not teach A non-transitory computer-readable storage medium configured to store instructions that, when executed by a processor, cause the processor to perform operations comprising:
generating a plurality of wafer level maps by measuring a wafer, after each one of a plurality of process operations is performed on the wafer;
detecting, for each of the defect clusters, an initial process operation in which a defect occurred, from among the plurality of process operations, based on operation information indicating an earliest one of the plurality of process operations in time after which the defect occurred.
Chen teaches an analogous A non-transitory computer-readable storage medium configured to store instructions ([0060] lines 14-20, “The tangible storage medium can be a computer readable medium. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a hard disk drive, a tape drive, an optical drive (such as, but not limited to CDROM, DVD, or BDROM) or the like, or a combination of one or more of them.”) that, when executed by a processor (Fig. 10, processor(s) 1002), cause the processor to perform operations ([0059] lines 1-4, “Processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output.”); [0060] lines 9-14, “Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible machine readable storage medium for execution by, or to control the operation of, data processing apparatus.”) comprising:
generating a plurality of wafer level maps by measuring a wafer, after each one of a plurality of process operations is performed on the wafer ([0026] lines 6-25, “At block 104, circuit performance (CP) tests, in-line defect tests, bin tests, wafer acceptance tests (WAT or electrical test method) and/or defect tests can be performed by applying the appropriate test criteria to the fabricated wafers. For example, a defect map can be formed using KLA-Tencor equipment. At block 106, a test data set is collected from testing the fabricated wafers at block 104. At block 105, a respective wafer map is formed for each of the wafers based on the collected test data set. For example, during the fabrication process of the plurality of semiconductor wafers, various in-process layers of each of the plurality of wafers can be verified by an in-line defect test to collect a test data set. A respective wafer map can be formed for each wafer using the test data collected and/or measured at various points on various in-line process layers (e.g. film deposition layers, lithography layers, etching layers, diffusion layers) of the wafer. In some embodiments, wafer maps can be generated based on a test data set measured at various points at each of the various in-process layers during fabrication of each of the plurality of wafers.”);
detecting, for each of the defect clusters (Fig. 1, wafer finger print; cluster algorithm of [0046]-[0047]) an initial process operation in which a defect occurred, from among the plurality of process operations indicating an earliest one of the plurality of process operations in time after which the defect occurred. ([0026] lines 6-25, “At block 104, circuit performance (CP) tests, in-line defect tests, bin tests, wafer acceptance tests (WAT or electrical test method) and/or defect tests can be performed by applying the appropriate test criteria to the fabricated wafers. For example, a defect map can be formed using KLA-Tencor equipment. At block 106, a test data set is collected from testing the fabricated wafers at block 104. At block 105, a respective wafer map is formed for each of the wafers based on the collected test data set. For example, during the fabrication process of the plurality of semiconductor wafers, various in-process layers of each of the plurality of wafers can be verified by an in-line defect test to collect a test data set. A respective wafer map can be formed for each wafer using the test data collected and/or measured at various points on various in-line process layers (e.g. film deposition layers, lithography layers, etching layers, diffusion layers) of the wafer. In some embodiments, wafer maps can be generated based on a test data set measured at various points at each of the various in-process layers during fabrication of each of the plurality of wafers.”; [0027] lines 17-21, “At block 112, if no objects are determined to be present on a wafer map, then the wafer is determined to be suitable for use and no further processing is performed on the wafer map. In some embodiments, the non-defect wafer maps can be discarded.”). The in-line or in-process steps are the process operations (“e.g. film deposition layers, lithography layers, etching layers, diffusion layers”). The wafer map generated at each of the various in-process layers during fabrication, where non-defect wafer maps are discarded, is the detection of the earliest process operation after the defect occurred.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the instructions of Zheng to include the non-transitory computer-readable storage medium, processor, and process operations of Chen because the inclusion of the process operations in which the defect occurs would yield predictable and advantageous results, including identifying operations which may be causing defects in the wafer and potentially correcting the operation to prevent future defects. The storage medium and processor amount to a generic computer, which is well-known in the art and the utilization of a generic computer to perform the process step would yield predictable results.
Regarding claim 16, Zheng in view of Chen teaches The non-transitory computer-readable storage medium of claim 15.
Zheng further teaches the storage medium, wherein the sorting of the defect points according to the defect clusters comprises:
adding the reference defect point to a first defect cluster of the first defect clusters; searching for a defect point of the defect points that is adjacent to the reference defect point; and adding the defect point that is adjacent to the reference defect point to the first defect cluster (Zheng: [0083] lines 1-12, “Therefore, when the defects with the same defect location on the different wafers are located inside the wafer, in an embodiment of the present disclosure, a plurality of densely distributed defects on one wafer are regarded as one defect region. If the defect region appears in the same location of the plurality of the wafers, the plurality of defect regions are defects with the same defect location on the different wafers. While two adjacent defect regions are not completely the same, it can be determined whether the defects are the same defects with the same defect location on the different wafers based on the differences of the coordinates of the center point of the defect region.”
Zheng does not teach the storage medium, comprising:
setting a first defect point, which is selected from among the defect points included in the composite wafer map, as a reference defect point
Chen teaches analogous instructions for sorting points into defect clusters (clustering algorithm of paragraph [0046]), comprising:
setting a first defect point (Chen: Fig. 1, steps 110, 115), which is selected from among the defect points included in the composite wafer map (Chen: [0027] lines 3-7, “An object, as defined herein, is a collection of test data on a wafer map formed for a respective wafer that is indicative of wafer failure. In various embodiments, an object can be a collection of test data formed by two or more adjacent failure die.”), as a reference defect point (Chen: Fig. 1, step 115; [0030] lines 14-15, “an object index can define the relative position or percent coverage of the object relative to the wafer map.”; [0031] lines 1-4, “one or more respective object indices for selecting a respective object on each of the respective selected wafer maps are selected at block 115.”).The object index, defining a position on the wafer, is the selected defect point and the respective object index is the reference defect point.
Regarding claim 17, Zheng in view of Chen teaches The non-transitory computer-readable storage medium of claim 16.
Chen further teaches wherein the searching for the defect point that is adjacent to the reference defect point comprises:
determining a distance between the reference defect point and each of the defect points (Chen [0046] lines 15-24 “a respective wafer fingerprint can be formed for each of the respective selected wafer maps using the formula D.sub.min(C.sub.i, C.sub.j)=min d(a,b) where a.epsilon.Ci, b.epsilon.Cj where d again represents a distance (e.g. Euclidean distance) between i and j, two points in pattern clusters C.sub.i and C.sub.j and D.sub.min represents the cluster distance. In this algorithm, the distance of the closest points of the two clusters can be compared. If the computed cluster distance in either algorithm is below a certain predetermined threshold, then the two clusters are completely merged.”); and
extracting, from the defect points, a defect point located at a distance from the reference defect point that is less than or equal to a critical threshold value (Chen: lines 21-24, “If the computed cluster distance in either algorithm is below a certain predetermined threshold, then the two clusters are completely merged.”). The merging of clusters that are below a predetermined threshold is the extracting a defect point that is located at a distance from the reference point that is less than or equal to a critical threshold value.
Regarding claim 18, Zheng in view of Chen teaches The non-transitory computer-readable storage medium of claim 17.
Chen further teaches the storage medium, further comprising:
updating the extracted defect point as a second reference defect point; and searching for a defect point of the defect points that is adjacent to the second reference defect point (Chen: [0047] lines 9-10, “The algorithm can then iterate until no more merging occurs, at which point all pattern clusters are formed.”). The iteration of the clustering algorithm utilizes the merged data points, including the extracted defect point, as a second reference defect point, in searching for other adjacent points, and therefore searches for a defect point that is adjacent to the second reference defect point.
Claim(s) 7, 13, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zheng in view of Chen as applied to claims 6, 10, and 17, respectfully, above, and further in view of Chu et al. (US 11587222 B2, previously cited).
Regarding claim 7, Zheng in view of Chen teaches The method of claim 6.
Zheng further teaches the method, further comprising:
based on determining that there is at least one unsorted defect point (Zheng: [0059] lines 3-8, “determining as a qualified region the predetermined region where the number of the predetermined defects is less than the set threshold, and determining as an unqualified region the predetermined region where the number of the predetermined defects is greater than or equal to the set threshold.”). The qualified region includes at least one unsorted defect point not belonging to any one of the defect clusters..
Zheng does not teach the method, comprising:
searching for a defect point of the defect points that is adjacent to the third reference defect point and adding the third reference defect point to a second defect cluster of the defect clusters.
Chen further teaches the method, comprising:
searching for a defect point of the defect points that is adjacent to the third reference defect point and adding the third reference defect point to a second defect cluster of the defect clusters (Chen: [0047] lines 9-10, “The algorithm can then iterate until no more merging occurs, at which point all pattern clusters are formed.”). The iteration of the clustering algorithm utilizes the merged data points, including the extracted defect point, as a second reference defect point, in searching for other adjacent points, and therefore searches for a defect point that is adjacent to the second reference defect point.
Zheng in view of Chen does not teach the method, comprising:
updating a second defect point selected from among the at least one unsorted defect point as a third reference defect point.
Chu teaches an analogous method of determining defects on a wafer (Abstract; Fig. 16, S200 “obtaining inspection data of a wafer”), comprising:
updating a second defect point (original data 30) selected from among the at least one unsorted defect point as a third reference defect point (col 9 lines 30-36, “data processing device 100 gathers the original data by a batch size, updates an existing clustering model using the original data gathered by the batch size, and clusters the original data included in a new batch. In this regard, it may be understood that the clustering model learning unit 150 simultaneously serves as a training stage and an inferring stage of the machine learning.”; lines 43-50, “The cluster manager 170 generates and updates information on each cluster formed by each original data input as the training data. The information on each cluster may include, for example, a score for each cluster or a grade based thereon, a hierarchical structure for each cluster, a result of automatic labeling for each cluster, and a score for each cluster according to user input for a result of clustering or a result of post-adjustment of a grade based thereon.”; Fig. 8, steps S210-S212). One of ordinary skill in the art would recognize that the clustering manager, updating the clustering information (by user or iteratively as step S210) and then merging clusters (step S212), the method of Chu is using an unsorted defect point as a reference point.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Zheng in view of Chen to include the selection of an unsorted defect point as a reference defect point of Chu because the inclusion of unsorted defect point as a reference defect point would yield predictable results of inclusion in the clustering process previously unsorted defect information, thereby including more information in the analysis.
Regarding claim 13, Zheng in view of Chen teaches The apparatus of claim 10.
Zheng further teaches the apparatus, wherein the processor is further configured to:
determine whether there is at least one unsorted defect point not belonging to any one of the defect clusters from among the defect points (Zheng: [0059] lines 3-8, “determining as a qualified region the predetermined region where the number of the predetermined defects is less than the set threshold, and determining as an unqualified region the predetermined region where the number of the predetermined defects is greater than or equal to the set threshold.”). The qualified region includes at least one unsorted defect point not belonging to any one of the defect clusters.
based on determining that there is at least one unsorted defect point (Zheng: [0059] lines 3-8, “determining as a qualified region the predetermined region where the number of the predetermined defects is less than the set threshold, and determining as an unqualified region the predetermined region where the number of the predetermined defects is greater than or equal to the set threshold.”). The qualified region includes at least one unsorted defect point not belonging to any one of the defect clusters., (Zheng: [0083] lines 1-12, “Therefore, when the defects with the same defect location on the different wafers are located inside the wafer, in an embodiment of the present disclosure, a plurality of densely distributed defects on one wafer are regarded as one defect region. If the defect region appears in the same location of the plurality of the wafers, the plurality of defect regions are defects with the same defect location on the different wafers. While two adjacent defect regions are not completely the same, it can be determined whether the defects are the same defects with the same defect location on the different wafers based on the differences of the coordinates of the center point of the defect region.”).
Zheng does not teach the apparatus, comprising:
update a second defect point selected from among the at least one unsorted defect point as a third reference defect point and add the third reference defect point to a second defect cluster of the defect clusters;
search for a defect point of the defect points that is adjacent to the third reference defect point
Chen further teaches the apparatus comprising:
search for a defect point of the defect points that is adjacent to the third reference defect point (Chen: [0047] lines 9-10, “The algorithm can then iterate until no more merging occurs, at which point all pattern clusters are formed.”). The iteration of the clustering algorithm utilizes the merged data points, including the extracted defect point, as a second reference defect point, in searching for other adjacent points, and therefore searches for a defect point that is adjacent to the second reference defect point.
Zheng in view of Chen teaches does not teach the apparatus, comprising:
update a second defect point selected from among the at least one unsorted defect point as a third reference defect point and add the third reference defect point to a second defect cluster of the defect clusters;
Chu teaches an analogous apparatus (Fig. 2) for determining defects on a wafer (Abstract; Fig. 16, S200 “obtaining inspection data of a wafer”), comprising:
updating a second defect point (original data 30) selected from among the at least one unsorted defect point as a third reference defect point (col 9 lines 30-36, “data processing device 100 gathers the original data by a batch size, updates an existing clustering model using the original data gathered by the batch size, and clusters the original data included in a new batch. In this regard, it may be understood that the clustering model learning unit 150 simultaneously serves as a training stage and an inferring stage of the machine learning.”; lines 43-50, “The cluster manager 170 generates and updates information on each cluster formed by each original data input as the training data. The information on each cluster may include, for example, a score for each cluster or a grade based thereon, a hierarchical structure for each cluster, a result of automatic labeling for each cluster, and a score for each cluster according to user input for a result of clustering or a result of post-adjustment of a grade based thereon.”; Fig. 8, steps S210-S212). One of ordinary skill in the art would recognize that the clustering manager, updating the clustering information (by user or iteratively as step S210) and then merging clusters (step S212), the method of Chu is using an unsorted defect point as a reference point.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Zheng in view of Chen to include the selection of an unsorted defect point as a reference defect point of Chu because the inclusion of unsorted defect point as a reference defect point would yield predictable results of inclusion in the clustering process previously unsorted defect information, thereby including more information in the analysis.
Regarding claim 19, Zheng in view of Chen teaches The non-transitory computer-readable storage medium of claim 17.
Zheng further teaches the storage medium, further comprising:
based on determining there is at least one unsorted defect point not belonging to any one of the defect clusters from among the defect points included in the composite wafer map (Zheng: [0059] lines 3-8, “determining as a qualified region the predetermined region where the number of the predetermined defects is less than the set threshold, and determining as an unqualified region the predetermined region where the number of the predetermined defects is greater than or equal to the set threshold.”). The qualified region includes at least one unsorted defect point not belonging to any one of the defect clusters.,
Zheng does not teach the storage medium, comprising:
updating a second defect point selected from among the at least one unsorted defect point as a third reference defect point and adding the third reference defect point to a second defect cluster of the defect clusters; and
searching for a defect point of the defect points that is adjacent to the third reference defect point.
Chen further teaches the storage medium, further comprising:
searching for a defect point of the defect points that is adjacent to the third reference defect point. (Chen: [0047] lines 9-10, “The algorithm can then iterate until no more merging occurs, at which point all pattern clusters are formed.”). The iteration of the clustering algorithm utilizes the merged data points, including the extracted defect point, as a second reference defect point, in searching for other adjacent points, and therefore searches for a defect point that is adjacent to the second reference defect point.
Zheng in view of Chen does not teach the instructions, comprising:
updating a second defect point selected from among the at least one unsorted defect point as a third reference defect point and adding the third reference defect point to a second defect cluster of the defect clusters.
Chu teaches an analogous method of determining defects on a wafer (Abstract; Fig. 16, S200 “obtaining inspection data of a wafer”), comprising:
updating a second defect point (original data 30) selected from among the at least one unsorted defect point as a third reference defect point (col 9 lines 30-36, “data processing device 100 gathers the original data by a batch size, updates an existing clustering model using the original data gathered by the batch size, and clusters the original data included in a new batch. In this regard, it may be understood that the clustering model learning unit 150 simultaneously serves as a training stage and an inferring stage of the machine learning.”; lines 43-50, “The cluster manager 170 generates and updates information on each cluster formed by each original data input as the training data. The information on each cluster may include, for example, a score for each cluster or a grade based thereon, a hierarchical structure for each cluster, a result of automatic labeling for each cluster, and a score for each cluster according to user input for a result of clustering or a result of post-adjustment of a grade based thereon.”; Fig. 8, steps S210-S212). One of ordinary skill in the art would recognize that the clustering manager, updating the clustering information (by user or iteratively as step S210) and then merging clusters (step S212), the method of Chu is using an unsorted defect point as a reference point.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the instructions of Zheng in view of Chen to include the selection of an unsorted defect point as a reference defect point of Chu because the inclusion of unsorted defect point as a reference defect point would yield predictable results of inclusion in the clustering process previously unsorted defect information, thereby including more information in the analysis.
Claim(s) 8, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zheng in view of Chen as applied to claim 1 above, and further in view of He et al. (US 10436720 B2, provided by applicant).
Regarding claim 8, Zheng in view of Chen teaches The method of claim 1.
Zheng in view of Chen does not teach the method, further comprising extracting a defect point of the defect points having a greatest height based on the detected initial process operation for each of the defect clusters.
He teaches an analogous method for detecting defects (Abstract), further comprising extracting a defect point of the defect points having a greatest height (col 28 lines 5-9, “a user may indicate that the defects have a significant height, e.g., higher than other defect types. Then, a decision tree based on height attributes can be added to filter out defects with relatively large height.”) based on the detected initial process operation for each of the defect clusters (col 1 lines 27-29, “Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers.”; Fig. 3, step 302). The filtering out defects of significant height (higher than other defect types) is the extraction of defect points having the greatest height.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Zheng in view of Chen to include the extraction of the highest defect points of He, because it would yield predictable and advantageous results, of removing defect points that are dissimilar to clustered defect points. This may result in advantageously removing defects (such as scratches in the wafer) from the defect cluster which are high enough to not represent a significant defect.
Regarding claim 14, Zheng in view of Chen teaches The apparatus of claim 9.
Zheng in view of Chen does not teach the apparatus, wherein the processor is further configured to extract a defect point of the defect points having a greatest height, based on the detected initial process operation for each of the defect clusters .
He teaches an analogous method for detecting defects (Abstract; Fig. 1), wherein the processor (computer subsystems 36, 102) is further configured to extract a defect point of the defect points having a greatest height (col 28 lines 5-9, “a user may indicate that the defects have a significant height, e.g., higher than other defect types. Then, a decision tree based on height attributes can be added to filter out defects with relatively large height.”), based on the detected initial process operation for each of the defect clusters (col 1 lines 27-29, “Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers.”; Fig. 3, step 302). The filtering out defects of significant height (higher than other defect types) is the extraction of defect points having the greatest height.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Zheng in view of Chen to include the extraction of the highest defect points of He, because it would yield predictable and advantageous results, of removing defect points that are dissimilar to clustered defect points. This may result in advantageously removing defects (such as scratches in the wafer) from the defect cluster which are high enough to not represent a significant defect.
Regarding claim 20, Zheng in view of Chen teaches The non-transitory computer-readable storage medium of claim 15.
Zheng in view of Chen does not teach the non-transitory computer-readable storage medium further comprising extracting a defect point of the defect points having a greatest height, using the detected initial process operation, according to each of the defect clusters
He teaches analogous non-transitory computer-readable storage medium (col 3 lines 26-30, “An additional embodiment relates to a non-transitory computer-readable medium storing program instructions executable on a computer system for performing a computer-implemented method for classifying defects on a specimen with an adaptive automatic defect classifier.”), further comprising extracting a defect point of the defect points having a greatest height (col 28 lines 5-9, “a user may indicate that the defects have a significant height, e.g., higher than other defect types. Then, a decision tree based on height attributes can be added to filter out defects with relatively large height.”), using the detected initial process operation (col 1 lines 27-29, “Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers.”; Fig. 3, step 302), according to each of the defect clusters (defect clustering 302).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the instructions of Zheng in view of Chen to include the extraction of the highest defect points of He, because it would yield predictable and advantageous results, of removing defect points that are dissimilar to clustered defect points. This may result in advantageously removing defects (such as scratches in the wafer) from the defect cluster which are high enough to not represent a significant defect.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Knoch et al. (US 20050065739 A1) teaches an analogous method, apparatus, and instructions for detecting defects of a wafer wherein the wafer map is generated after each of the process operations is performed (Fig. 2, steps 204-212; Fig. 3).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.B.G./Examiner, Art Unit
2857
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2857