DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/24/2026 has been entered.
Response to Amendment
Applicant has submitted the following:
Claims 1-20 are pending examination; and
Claims 1, 9, 15 are newly amended.
Response to Arguments
Applicant's arguments filed 05/26/2026 have been fully considered but they are not fully persuasive.
Applicant argues that none of the prior art, alone or in combination, teaches the limitations of the newly amended independent claims 1, 9, and 15.
Examiner find the argument persuasive. Specifically, none of the prior art, alone or in combination, teaches the method, apparatus, and instructions comprising:
a plurality of wafer level maps of the wafer, wherein the plurality of wafer level maps are generated by a photo level measuring device measuring the wafer after each respective one of a plurality of process operations is performed on the wafer, wherein each of the plurality of wafer level maps corresponds to a respective one of the plurality of process operations, wherein the plurality of process operations comprises at least one photolithography process; and
a composite wafer map of the wafer, the composite wafer map comprising defect points by combining the plurality of wafer level maps of the wafer
Therefore, the rejection of claims 1-20 under 35 USC 103 is withdrawn.
Applicant argues that the newly amended claims 1, 9, and 15 overcome the rejection under 35 USC 101 because the limitations cannot be performed practically in the human mind. Applicant further argues that the claims integrate the abstract idea into a practical application.
Examiner respectfully disagrees. The receiving of the plurality of wafer level maps of the wafer is collecting of information, which may be performed as mental processes. Further, the receiving of said wafer level maps does not integrate the abstract idea into a practical application. Even if said wafer level maps have hot spots and defocus problems (which are not recited as claim limitations), said problems are part of the received wafer level maps, and therefore are the collected information. None of the additional elements integrate the judicial exception into a practical application. (see detailed action under 35 USC 101, below).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention in each of these claims is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Specifically, representative Claim 1 recites:
“A method of detecting defects of a wafer, the method comprising:
receiving, by at least one processor, a plurality of wafer level maps of the wafer, wherein the plurality of wafer level maps are generated by a photo level measuring device measuring the wafer after each respective one of a plurality of process operations is performed on the wafer, wherein each of the plurality of wafer level maps corresponds to a respective one of the plurality of process operations, wherein the plurality of process operations comprises at least one photolithography process, and wherein each one of the plurality of wafer level maps is configured to be stored in a memory;
generating, by the at least one processor, a composite wafer map of the wafer, the composite wafer map comprising defect points by combining the plurality of wafer level of the wafer;
sorting, by the at least one processor, the defect points according to defect clusters based on positions of the defect points included in the composite wafer map; and
detecting, by the at least one processor, for each of the defect clusters, an initial process operation in which a defect occurred, from among the plurality of process operations, based on operation information indicating an earliest one of the plurality of process operations in time after which the defect occurred.”
The claim limitations considered to fall within in the abstract idea are highlighted in bold font above; the remaining features are “additional elements.”
Step 1 of the subject matter eligibility analysis entails determining whether the claimed subject matter falls within one of the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: process, machine, manufacture, or composition of matter. Claim 1 recites a process and is therefore falls within a statutory category.
Step 2A, Prong One of the analysis entails determining whether the claim recites a judicial exception such as an abstract idea. Under a broadest reasonable interpretation, the highlighted portion of claim 1 comprises process steps that fall within the abstract idea judicial exception. Specifically, under the 2019 Revised Patent Subject matter Eligibility Guidance, the highlighted subject matter falls within the mental processes category.
Individually and collectively, the steps:
“receiving […] a plurality of wafer level maps of the wafer, wherein the plurality of wafer level maps are generated by a photo level measuring device measuring the wafer after each respective one of a plurality of process operations is performed on the wafer, wherein each of the plurality of wafer level maps corresponds to a respective one of the plurality of process operations, wherein the plurality of process operations comprises at least one photolithography process, and wherein each one of the plurality of wafer level maps is configured to be stored in a memory”;
“generating […] a composite wafer map of the wafer, the composite wafer map comprising defect points by combining the plurality of wafer level maps of the wafer”;
“sorting […] the defect points according to defect cluster”; and
“detecting […] an initial process operation in which a defect occurred, from among the plurality of process operations, based on operation information indicating an earliest one of the plurality of process operations in time after which the defect occurred.”
may be performed as mental processes. Receiving a plurality of wafer level maps of the wafer is the collecting of information, which may be performed as mental processes. Generating a composite wafer map is the output of analysis, which may be performed as mental processes. Sorting the defect points is an analysis of information, and may be performed as mental processes. Detecting an initial process operation is an identification step, which may be performed as mental processes. The type of high-level information collecting and analyzing data recited in these elements has been found by the Federal Circuit to constitute patent ineligible matter (see Electric Power Group v. Alstom, S.A., 830 F.3d 1350, 1353-54, 119 USPQ2d 1739, 1741-42 (Fed. Cir. 2016), a claim to "collecting information, analyzing it, and displaying certain results of the collection and analysis," where the data analysis steps are recited at a high level of generality such that they could practically be performed in the human mind).
Similar limitations comprise the mental processes type abstract idea recited by independent claims 9 and 15.
Step 2A, Prong Two of the analysis entails determining whether a claim includes additional elements that integrate the recited judicial exception (e.g., abstract idea) into a practical application. In view of the various considerations encompassed by the Step 2A, Prong Two analysis, claim 1 does not include additional elements that integrate the recited abstract idea into a practical application. Based on the individual and collective limitations of claim 1, applying a broadest reasonable interpretation, the most significant of such considerations appear to include: improvements to the functioning of a computer, or to any other technology or technical field (MPEP 2106.05(a)); applying the judicial exception with, or by use of, a particular machine (MPEP 2106.05(b)); and effecting a transformation or reduction of a particular article to a different state or thing (MPEP 2106.05(c)).
Regarding improvements to the functioning of a computer or other technology, none of the “additional elements” in any combination appear to integrate the abstract idea to technologically improve any aspect of a system that may be used to implement the highlighted steps such a generic computer. Any alleged improvement would be an improvement in the abstract idea, and thus not an improvement in technology (MPEP 2106.05(a).II “However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology.”.). The additional element of “at least one processor” is a generic computer, and the claim amounts to mere instructions to implement the abstract idea in a generic computer (MPEP 2106.05(f)).
Regarding application of the judicial exception with, or by use of, a particular machine, none of the “additional elements” in any combination appear to integrate the abstract idea in a particularized manner of implementing the abstract idea process steps. Instead the claim as a whole amounts to analyzing information (“generating”, “sorting”, and “detecting” steps).
Regarding effectuation of a transformation or reduction of a particular article to a different state or thing, the claim includes no such transformation or reduction. Instead the claim as a whole amounts to analyzing information (“generating”, “sorting”, and “detecting” steps). The composite wafer map generated is a representation of information and not a particular article that is transformed.
Independent claim 9 recites additional elements, including “an apparatus for detecting defects of a wafer”, “a memory storing a program”, and “a processor”. The additional elements are recited generically and not utilized in a particular manner. The additional elements amount to mere instructions to implement the process steps on a generic computer (see MPEP 2106.05(f)), and therefore is not an improvement in technology. None of the additional elements, alone or in combination, amount to a transformation of a particular article. Therefore, independent claim 9 does not integrate the judicial exception into a practical application.
Independent claim 15 recites additional elements, including “a non-transitory computer-readable storage medium” and “a processor”. The additional elements are recited generically and not utilized in a particular manner. The additional elements amount to mere instructions to implement the process steps on a generic computer (see MPEP 2106.05(f)), and therefore is not an improvement in technology. None of the additional elements, alone or in combination, amount to a transformation of a particular article. Therefore, independent claim 15 does not integrate the judicial exception into a practical application.
The above additional elements, considered individually and in combination with the claim elements reciting an abstract idea do not reflect an improvement to other technology or technical field, and, therefore, do not integrate the judicial exception into a practical application. Therefore, the claims are directed to a judicial exception and require further analysis under Step 2B.
Regarding Step 2B, independent claims 1, 9 and 16, do not include additional elements that are sufficient to amount to significantly more than the judicial exception. Instead, the independent claims amount to collecting information, analyzing information, and outputting certain results of the analysis. Even if independent claims 1, 9, and 16 recite an inventive concept, said alleged inventive concept would be in the abstract idea, and therefore not patent eligible (MPEP 2106.05: “As made clear by the courts, the "‘novelty’ of any element or steps in a process, or even of the process itself, is of no relevance in determining whether the subject matter of a claim falls within the § 101 categories of possibly patentable subject matter." Intellectual Ventures I v. Symantec Corp., 838 F.3d 1307, 1315, 120 USPQ2d 1353, 1358 (Fed. Cir. 2016) (quoting Diamond v. Diehr, 450 U.S. at 188–89, 209 USPQ at 9). See also Synopsys, Inc. v. Mentor Graphics Corp., 839 F.3d 1138, 1151, 120 USPQ2d 1473, 1483 (Fed. Cir. 2016) ("a claim for a new abstract idea is still an abstract idea. The search for a § 101 inventive concept is thus distinct from demonstrating § 102 novelty.")).
Independent claims 1, 9, and 15 are therefore not patent eligible.
Dependent claim 2-8, 10-14, and 16-20 provide additional features/steps which are part of the process steps that includes the abstract idea of the independent claims (Step 2A, Prong One). None of dependent claims 2-8, 10-14, and 16-20 recite additional elements that integrate the abstract idea into practical application (Step 2A, Prong Two).
Claims 2, 10, and 16 recite additional details on the sorting step, including setting a first defect point as a reference point, adding the reference point to a cluster, searching for an adjacent point, and adding the adjacent point to the cluster, which may be performed as mental processes. Claims 3-7, 11-13, and 17-19 recite further details on the sorting and searching steps, which may be performed as mental processes. Claims 8, 14, and 20 further recite extracting a defect point, which is an analysis which may be performed as mental processes.
Claims 2-8, 10-14, and 16-20 all fail the “significantly more” test under the step 2B for the same reasons as discussed with regards to the independent claims.
Therefore, dependent claims 2-8, 10-14, and 16-20 are also ineligible subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN GEISS whose telephone number is (571)270-1248. The examiner can normally be reached Monday - Friday 7:30 am - 4:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Rastovski can be reached at (571) 270-0349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.B.G./Examiner, Art Unit 2857
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2857