DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Barner et al. US Patent Application Publication No. 2021/0374057 (originally cited in IDS filed 2/27/2024, herein after referred to as Barner) in view of Kayiran et al. US Patent Application Publication No. 2022/0091980 (originally cited in IDS filed 2/27/2024, herein after referred to as Kayiran).
Regarding claims 1,8, 9, and 14, Barner describes an apparatus [a method] comprising: a semiconductor package (Fig. 1 illustrates the configuration of an exemplary multi-chip processing system where two columns of clusters in different chips are communicatively coupled by means of column-specific inter-chip interconnect interfaces in accordance with an embodiment of the present disclosure… (page 3, paragraph [0026])) comprising: a plurality of cores and a fabric to provide the plurality of cores with access to at least one cache device (…each cluster in the chips 100 and 150 includes multiple processing cores and one or more shared cache controllers… (page 3, paragraph [0027]). The cluster also includes a shared cache 230 accessible to all the core processors 201-206 through a switch 210 (page 4, paragraph [0038])), wherein: a cache controller is to: based on data associated with a memory access request stored in the at least one cache device, service a forwarded memory access request at the selected cache device of the at least one cache device (At 801, a memory request is generated in a cluster (cluster 1) of a first chip (chip I) and the memory request may be initiated by a core processor in chip I… At 802, based on the memory address and a set of bits (e.g., by hashing the bits in the memory request, the core processor selects a local shared cache controller in chip I and sends the request to this cache controller. If the local shared cache controller determines (at 803) that a cache hit results from the local shared cache, the requested data is access from the cache and returned to the requesting core processor at 804 (page 6, paragraphs [0052] – 0053])) and based on data associated with the memory access request managed by a second cache controller, forward the forwarded memory access request to the second cache controller in the selected group (If the local shared cache controller determines (at 803) that a cache miss results from the local shared cache, the cache controller further determines whether is a local DRAM request at 805. If not, at 806, the request is forwarded to the corresponding remote shared cache controller (e.g., located in cluster 2 chip II) via the inter-chip interconnect interface of this column. The remote cache controller (on chip II) may process the request according to process 840 as shown in Fig. 8B. At 807, the local cache controller receives a response from the remote cache controller. AT 808, the local cache controller response to the requesting core processor based on the response (page 6, paragraph [0054])). Barner does not explicitly disclose that the fabric comprises a group of routers and a plurality of groups of cache controllers, the fabric comprises a group of connections between the group of routers and the plurality of groups of cache controllers, the fabric comprises a second group of connections between cache controllers in a group of cache controllers, based on receipt of a memory access request from a core of the plurality of cores: a router of the group of routers is to select a group from among the plurality of groups of cache controllers based on the memory access request and forward the memory access request to the selected group.
Kayiran describes a system for efficiently processing memory requests. Specifically, communication fabric 150 (or the fabric 150) transfers data back and forth between the clusters 110-130 and the memory controller 130 and includes interfaces for supporting respective communication protocols. The protocols determine values used for information transfer, such as a number of data transfers per clock cycle, signal voltage levels, signal timings, signal and clock phases and clock frequencies. Examples of the data transferred across the communication fabric 150 are commands, messages, probes, interrupts, response commands, response data, and payload data corresponding to the commands and messages. The fabric 150 includes queues for storing requests and responses. The fabric 150 also includes selection logic, such as circuitry, for arbitrating between received requests or received responses before sending requests (or responses) across an internal network between intermediate queues. Additional logic in the fabric 150 builds and decodes packets as well as selects routes for the packets. Fabric 150 uses one or more of point-to-point connections, buses and multi-port routers to transfer information (page 2, paragraph [0023]). The cache controller 200 is a cache controller of a cache located across a communication fabric from multiple compute units that generate memory access requests. In one embodiment, the cache controller 200 is used with a cache at a level of a memory hierarchy lower than a level-one (L1) cache that is located relatively near a compute unit. For example, the cache controller 200 is used with a shared L2 cache, a shared L3 cache or other lower level cache located across a communication fabric from the multiple compute units. In the illustrated embodiment, cache controller 200 includes an interface 210 to higher level cache via a communication fabric, queues 220 for storing received memory access requests and received memory access responses, control unit 250 and an interface 280 to lower level memory. Examples of the lower level memory are lower level caches, system memory and main memory (page 4, paragraph [0031]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Kayiran teachings in the Barner system. Skilled artisan would have been motivated to incorporate the method of correctly routing memory requests as taught by Kayiran in the Barner system for efficiently processing memory requests. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as cache access across an interconnect. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 2, Barner in view of Kayiran describes the apparatus of claim 1 [the method of claim 8] (see above), wherein the group of connections and the second group of connections are physically arranged in different directions (…Fabric 150 uses one or more point-to-point connections, buses and multi-port routers to transfer information (Kayiran, page 3, paragraph [0023])).
Regarding claims 3 and 10, Barner in view of Kayiran describes the apparatus of claim 1 [the method of claim 8] (see above), wherein the memory access request comprises a memory address and identifier of a group of cache controllers of the plurality of groups of cache controllers to which to forward the memory access request (If a cache miss results, the shared cache controller 220 can identify the corresponding cache controller in the other chip and forward the memory request to it. According to embodiments of the present disclosure, one or more indications are used to indicating the relative cluster locations between the chips with reference to the mesh design… Based on the indication(s) and the memory address contained in the memory request, the corresponding remote cache controller can be selected or identified (Barner, page 4, paragraph [0040])).
Regarding claim 4, Barner in view of Kayiran describes the apparatus of claim 1 (see above), comprising the at least one cache device communicatively coupled to the fabric (The cluster also includes a shared cache 230 accessible to all the core processors 201-206 through a switch 210… The switch 210 has switching circuits and logic configured to conduct communication traffic to and from the cluster 200… (Barner, page 4, paragraph [0038]). Communication fabric 150… transfers data back and forth between clusters 110-130 and the memory controller 130… (Kayiran, page 2, paragraph [0023]). As shown, fabric 150 is partitioned into interconnect 152 for servicing memory access requests from cluster 110 and interconnect 154 for servicing memory access requests from cluster 130. Interconnect 156 communicates with the caches 160-166 in addition to the interconnect 152 and interconnect 154… (Kayiran, page 3, paragraph [0024])).
Regarding claims 5 and 11, Barner in view of Kayiran describe the apparatus of claim 1 [the method of claim 8] (see above), wherein based on a cache miss in the at least one cache device, the second cache controller is to request data associated with the memory access request from a memory device (If a cache miss results, the shared cache controller 220 can identify the corresponding cache controller in the other chip and forward the memory request to it. According to embodiments of the present disclosure, one or more indications are used to indicating the relative cluster locations between the chips with reference to the mesh design… Based on the indication(s) and the memory address contained in the memory request, the corresponding remote cache controller can be selected or identified (Barner, page 4, paragraph [0040])).
Regarding claim 6, Barner in view of Kayiran describe the apparatus of claim 1 (see above), wherein the at least one cache device comprises one or more of: level 1 cache (L1), level 2 cache (L2), level 3 cache (L3), or last level cache (LLC) (The core processors are each coupled to level-one (L1) caches… The cluster also includes a shared cache 230 accessible to all the core processors 201-206 through a switch 210, e.g., a level-two (L2) cache or last-level cache (LLC) (Barner, page 4, paragraph [0038])).
Regarding claim 7, Barner in view of Kayiran describe the apparatus of claim 1 (see above), comprising a server, wherein the server comprises the plurality of cores and the fabric (…the computing system 100 is used in… a server… (Kayiran, page 2, paragraph [0017])).
Regarding claim 12, Barner in view of Kayiran describe the method of claim 8 (see above), comprising: performing cache coherency to retrieve updated data associated with the memory access request (The intra-chip interconnect interface may include logic and paths to implement memory coherence within the chip (Barner, page 4, paragraph [0037])).
Regarding claim 13, Barner in view of Kayiran describe the method of claim 8 (see above), wherein a package is to enclose the plurality of cores and the fabric (…each cluster in the chips 100 and 150 includes multiple processing cores and one or more shared cache controllers… The group-specific interconnect interface serves to route traffic between the clusters in the instant group and the clusters in a specific group residing in the other chip (Barner, page X, paragraphs [0027] – [0028])).
Regarding claim 15, Barner in view of Kayiran describe the method of claim 8 (see above), wherein the selecting a group from among a plurality of groups of cache controllers based on the memory access request comprises selecting an output line to the selected group (…One or more caches as well as the associated cache controllers (e.g., a pair of shared cache controllers that manage one last-level cache) are selected using a set of particular bits in the address. In an embodiment, one or more particular bits are hashed (e.g., XORed) with selected other bits in the address to select the group of caches and cache lines …the memory request is processed at the selected cache (Barner, page 2, paragraph [0025])).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Mathew Abraham et al. US Patent Application Publication No. 2020/0301830 describes a core can be coupled to a combined caching agent and home agent, referred to herein as a caching home agent (CHA) 120 or caching agent (CA) 122 and home agent (HA) 124. In general, CHA 120 can serve as a local coherence and cache controller (via cache controller 122, also referred to herein as a caching agent), and also serve (via home agent 124) as a global coherence and memory controller interface. In some embodiments, CHA 120 may be of a distributed design, including one or more of the distributed CHAs 120-0 to 120-N associated with one of the cores. A CHA 120 can include a caching agent 122 and a home agent 124 (page 1, paragraph [0012]). A core can send requests to its CA 122. CA 122 can provide data from its cache slice or obtain a copy of data from another core's cache. In case of a cache miss, CA 122 can forward the request to a home agent 124 which provides the data from memory or sends snoop requests to other caching agents 122 and to a home agent 124. If another caching agent 122 maintains a copy of the cache line in state modified, exclusive, or forward, a copy of the cache line can be provided to the requester (page 1, paragraph [0014]). Browne et al. US Patent Application Publication NO. 2022/0060391 describes in various embodiments, a cache agent 412 may receive a memory request and route the request towards an entity that facilitates performance of the request. For example, if cache agent 412 of a processor receives a memory request specifying a memory address of a memory device (e.g., system memory 434) coupled to the processor, the cache agent 412 may route the request to a memory controller 430 that manages the particular memory device (e.g., in response to a determination that the data is not cached at processor 400. As another example, if the memory request specifies a memory address of a memory device that is on a different processor (but on the same computing node), the cache agent 412 may route the request to an inter-processor communication controller which communicates with the other processors of the node. As yet another example, if the memory request specifies a memory address of a memory device that is located on a different computing node, the cache agent 412 may route the request to a fabric controller (which communicates with other computing nodes via a network fabric such as an Ethernet fabric, an Intel Omni-Path Fabric, an Intel True Scale Fabric, an InfiniBand-based fabric (e.g., Infiniband Enhanced Data Rate fabric), a RapidIO fabric, or other suitable board-to-board or chassis-to-chassis interconnect) (page 7, paragraph [0073]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RALPH A VERDERAMO III whose telephone number is (571)270-1174. The examiner can normally be reached Monday through Friday 8:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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August 21, 2026
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