DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claim 2, in the reply filed on 02/02/2026 is acknowledged.
Claim Objections
Claims 2 and 7–8 are objected to because of the following informalities: claim 2 recites “a digitial-to-analog converter”; claim 7 recites “a single flag register that enables writes…”; claim 8 recites “at least four flag registers that each enables writes…” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2, and 4–19 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Vogelsang (U.S. 10,136,090 B2).
Regarding claim 2, Vogelsang discloses an in-pixel analog image processing device comprising:
an array of analog in-pixel processing elements, each in-pixel processing element including: a photodetector; (Fig. 24, an eclipse detector 615)
photodetector control circuitry; (Fig. 2, an array circuitry)
analog computing circuitry including:
a plurality of register banks having write operations to each register within a register bank enabled by a flag register; and (Per Fig. 1, Vogelsang’s image sensor comprises registers. Vogelsang col. 5 lines 9–24. [t]he image sensor may include amplifiers, analog-to-digital converters (“ADCs”), comparators, controllers, counters, accumulators, registers,)
an analog bus configured to selectively perform math and logic operations in response to instruction bit values; (Per Fig. 4, Vogelsang’s read circuitry array 130 reads bus signal. Id. col. 12 lines 27–51. A pixel signal bus couples the IPs in each IP column in the IP array to the read circuit associated with the IP column within the read circuit array.)
a set of analog connection registers, each connection register connected to the analog bus and interconnected between a unique pair of neighboring in-pixel processing elements to transfer analog information between the pair of neighboring in-pixel processing elements; and (Fig. 2, IP column 50)
a plurality of digital memory components operably interconnected to the analog bus through an analog-to-digital converter and a digital-to-analog converter; and (Fig. 6b, memory group)
a compute system operably connected to each in-pixel processing element and configured to: (Fig. 2, an ADC 85)
present instruction bit values used to convert a photodetector current into analog sub-frame data; and (Per Fig. 3, Vogelsang’s adder 114 conducts digital conversions for image data. Id. col. 10 lines 37–44. [t]he accumulator stores all zeros to the selected IP memory location 116 the accumulation of received digital conversions as image data.)
present instruction bit values used to provide register transfer, math and logic operations to manipulate the analog sub-frame data. (Fig. 3, Vogelsang’s adder 114 programs resolved bits of the ADC conversion. Id. col. 10 lines 45–59. [o]ther ADC conversions are output as “1xxxxxx,” where an x represents one of the resolved bits of the ADC conversion and the number of x positions is equal to the bit depth of the ADC.)
Regarding claim 4, Vogelsang discloses the device, wherein the photodetector control circuitry comprises at least three analog memory components. (Per Fig. 2, Vogelsang discloses multiple transistors to consist of a circuitry. Vogelsang col. 17 line 47 – col. 18 line 2. [o]nly seven transistors are required to implement a set of four “4T” pixels having a shared source follower, reset transistor and access transistor (i.e., four transfer-gates plus the three shared transistors), thus effecting an average of 1.75 transistors per pixel (1.75T).)
Regarding claim 5, it has been rejected in the same manner as claim 4.
Regarding claim 6, Vogelsang discloses the device, wherein the analog computing circuitry comprises at least four register banks. (Per Fig. 20, Vogelsang discloses four photodiodes. Vogelsang col. 28 lines 22–43. [r]ead-out of the aggregated (binned) charge within all four photodiodes may be effected by performing additional partial-read operations in phase 3 (i.e., repeating the TGr1, TGr2 partial-on pulses,)
Regarding claim 7, it has been rejected in the same manner as claim 6.
Regarding claim 8, it has been rejected in the same manner as claim 6.
Regarding claim 9, it has been rejected in the same manner as claim 4.
Regarding claim 10, Vogelsang discloses the device, wherein the digital compute-in-memory processor is an Associative Processing Unit. (Per Fig. 8, Vogelsang discloses a post processing module 208. Vogelsang col. 16 line 64 – col. 17 line 8. A post processing module 208 receives the image data 206 and performs one or more processing operations on the image data to produce the processed data 210.)
Regarding claim 11, it has been rejected in the same manner as claim 10.
Regarding claim 12, Vogelsang discloses the device, wherein the compute system is configured to overlap the conversion of the photodetector current into the analog sub-frame data with the manipulation of a previous set of analog sub-frame data. (Per Fig. 30, Vogelsang’s circuitry receives subframe data to oversample the other frame. Vogelsang col. 35 lines 16–56. [t]he subframe data generated by temporal oversampling within image sensor 801 are, in effect, piped through the ISP directly to memory IC (e.g., a DRAM) where they may be accessed by the application processor.)
Regarding claim 13, Vogelsang discloses the device, wherein the compute system comprises a first instruction bus for the photodetector control circuitry and a second, separate instruction bus for the analog computing circuitry. (Per Fig. 32, Vogelsang discloses a first subexposure and a second subexposure. Vogelsang col. 37 line 61 – col. 38 line 7. [t]he first subexposure can be captured at ISO 100, the second subexposure can be captured at ISO 200,)
Regarding claim 14, it has been rejected in the same manner as claim 13.
Regarding claim 15, it has been rejected in the same manner as claim 6.
Regarding claim 16, it has been rejected in the same manner as claim 13.
Regarding claim 17, it has been rejected in the same manner as claim 13.
Regarding claim 18, it has been rejected in the same manner as claim 13.
Regarding claim 19, Vogelsang discloses the device, wherein the analog computing circuitry is configured to process both neighbor-in-space and neighbor-in-time functions for the analog sub-frame data, and wherein the set of analog connection registers comprises a set of NEWS registers, each NEWS register interconnected between a unique pair of neighboring in- pixel processing elements to transfer analog data between the pair of neighboring in-pixel processing elements. (Per Fig. 35, Vogelsang discloses two neighboring frames are merged. Vogelsang col. 39 lines 33–51. [e]ach group of two neighboring frames can be merged using traditional HDR frame merging to create previews with simulated HDR capture.)
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hammer et al. (U.S. 11,729,345 B2) discloses a detector for imaging and digitizing a spatial distribution of photon flux.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENEDICT LEE whose telephone number is (571)270-0390. The examiner can normally be reached 10:00-16:00 (EST).
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/BENEDICT E LEE/Examiner, Art Unit 2665
/Stephen R Koziol/Supervisory Patent Examiner, Art Unit 2665