Prosecution Insights
Last updated: October 04, 2026
Application No. 18/208,432

LASER PROCESSING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND LASER PROCESSING DEVICE

Non-Final OA §102§103
Filed
Jun 12, 2023
Priority
Jun 15, 2022 — JP 2022-096476
Examiner
LAZO, THOMAS E
Art Unit
3745
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
National University Corporation Tokai National Higher Education and Research System
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1199 granted / 1382 resolved
+16.8% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
30 currently pending
Career history
1407
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
40.7%
+0.7% vs TC avg
§102
42.0%
+2.0% vs TC avg
§112
10.0%
-30.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1382 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 4, 6, 7, 9-11, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita et al. (20170355041). Regarding claims 1 and 17, Yamashita et al. discloses a laser processing method for cutting a work piece (SiC material 210) along an imaginary plane facing a surface of the work piece inside the work piece, the method comprising a forming step of forming a plurality of modified spots (altered region groups 13 and 22) along the imaginary plane by irradiating an inside of the work piece with laser light from the surface (paragraph [0030] and [0037]), wherein the work piece includes a first region (surrounded by altered region groups 13 and 22, Fig. 5) and a second region (surround by 2 main altered regions 13 and 2 auxiliary altered regions 22) when viewed in a direction perpendicular to the surface, and in the forming step, a plurality of modified spot rows formed of the plurality of modified spots arranged along a boundary between the first region and the second region are formed in the second region (Fig. 5, paragraphs [0037]-[0040]), the plurality of modified spot rows being arranged along a direction intersecting an arrangement direction of the plurality of modified spots, and a crack extending from the second region to the first region is formed by forming the plurality of modified spot rows (paragraphs [0006], [0038],[0041],[0043]). Regarding claim 2, Yamashita et al. discloses that in the forming step, the plurality of modified spot rows are formed in the second region such that the crack is formed over an entirety of the first region (paragraphs [0006], [0038],[0041],[0043]). Regarding claim 4, Yamashita et al. discloses that the second region includes a portion surrounding the first region when viewed in the direction perpendicular to the surface (Fig. 5, paragraphs [0037]-[0040]). Regarding claim 6, Yamashita et al. discloses that the second region includes a grid-shaped portion including a plurality of linear portions, and the first region includes a plurality of rectangular portions surrounded by the plurality of linear portions (Fig. 5, paragraphs [0037]-[0040]). Regarding claim 7, Yamashita et al. discloses that when one linear portion included in the plurality of linear portions is defined as a reference linear portion, and a region on one side of the reference linear portion with respect to a center line of the reference linear portion extending along an extending direction of the reference linear portion when viewed in the direction perpendicular to the surface is defined as a first portion, and a region on the other side of the reference linear portion with respect to the center line is defined as a second portion, in the forming step, at least one modified spot row included in the plurality of modified spot rows is formed in the first portion, and at least one modified spot row included in the plurality of modified spot rows is formed in the second portion (Fig. 5, paragraphs [0037]-[0040]). Regarding claim 9, Yamashita et al. discloses that a material of the work piece includes gallium nitride, silicon carbide, sapphire, silicon, gallium arsenide, magnesium oxide, magnesium fluoride, calcium fluoride, or mica. See Yamashita et al. paragraph [0041]. Regarding claim 10, Yamashita et al. discloses that the work piece has a chip shape, a wafer shape, or an ingot shape (Fig. 5, chip shape (square with different pitches P1-P3)). Regarding claim 11, Yamashita et al. discloses that the work piece is made of a semiconductor material (SiC). See Yamashita et al. paragraph [0041]. Regarding claim 15, Yamashita et al. discloses a step of separating the work piece with the imaginary plane as a boundary after the forming step. See Yamashita et al. paragraph [0032]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3, 5, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al., as applied to claim 1 above, in view of Donofrio et al. (20200316724). Yamashita et al. discloses all of the claimed subject matter except for the plurality of modified spot rows include a first modified spot row, and a second modified spot row disposed closer to the first region than the first modified spot row, and in the forming step, after the first modified spot row is formed, the second modified spot row is formed, that in the forming step, at least two modified spot rows included in the plurality of modified spot rows are simultaneously formed by branching the laser light and by performing an irradiation with the branched laser light, and a semiconductor device manufacturing method wherein the work piece is made of a semiconductor material, the method comprising: the forming step; and a step of forming a device portion in the first region. Donofrio et al. teaches for a laser processing method for cutting a work piece along an imaginary plane facing a surface of the work piece inside the work piece, the method comprising a forming step of forming a plurality of modified spots along the imaginary plane by irradiating an inside of the work piece with laser light from the surface and that (claim 3) the plurality of modified spot rows include a first modified spot row, and a second modified spot row disposed closer to the first region than the first modified spot row, and in the forming step, after the first modified spot row is formed, the second modified spot row is formed (Fig. 11A, paragraphs [0220]-[0221]), (claim 5) that in the forming step, at least two modified spot rows included in the plurality of modified spot rows are simultaneously formed by branching the laser light and by performing an irradiation with the branched laser light (Fig. 22A, paragraph [0244]), and (claim 16) a semiconductor device manufacturing method wherein the work piece is made of a semiconductor material, the method comprising: the forming step; and a step of forming a device portion in the first region (Figs. 37A, 37L,37I, paragraphs [0271], [0272], [0274]) for the purposes of parting thin crystalline layers from the substrate with lower loss and better manufacturability. See Donofrio et al. paragraphs [0015] and [00293]. Since Yamashita et al. and Donofrio et al. are both in the same field of endeavor the purpose disclosed by Donofrio et al. would have been recognized in the pertinent art of Yamashita et al. It would have been obvious at a time before the invention was effectively filed to a person having ordinary skill in the art to modify the laser processing method of Yamashita et al. to include the plurality of modified spot rows include a first modified spot row, and a second modified spot row disposed closer to the first region than the first modified spot row, and in the forming step, after the first modified spot row is formed, the second modified spot row is formed, that in the forming step, at least two modified spot rows included in the plurality of modified spot rows are simultaneously formed by branching the laser light and by performing an irradiation with the branched laser light, and a semiconductor device manufacturing method wherein the work piece is made of a semiconductor material, the method comprising: the forming step; and a step of forming a device portion in the first region for the purposes of parting thin crystalline layers from the substrate with lower loss and better manufacturability. Prior Art Prior art made of record but not relied upon is considered pertinent to Applicant's disclosure for showing other laser processing devices that cut work pieces. Allowable Subject Matter Claims 8 and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The improvements comprise that (claim 8) the plurality of first modified spot rows are formed in the first portion in order of proximity to the center line, and the plurality of second modified spot rows are formed in the second portion in order of proximity to the center line and (claim 12) the first region is a region for forming a device portion, and the second region is a region in which the device portion is not formed. Contact Information Any inquiry concerning this communication or earlier communication from the examiner should be directed to Thomas Lazo whose telephone number is (571) 272-4818. The examiner can normally be reached on Monday-Friday from 8:00 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor Nathaniel Wiehe, can be reached on (571) 272-8648. The fax phone number for this Group is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS E LAZO/Primary Examiner, Art Unit 3745 August 8, 2026
Read full office action

Prosecution Timeline

Jun 12, 2023
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+8.9%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1382 resolved cases by this examiner. Grant probability derived from career allowance rate.

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