DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
With respect to claim 1, the recitation of “transistors;” on line 20 should be changed to -- transistors. --.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mercer (USPN 6,198,266).
With respect to claim 1, Mercer discloses, in Fig. 2(b), a circuit (Fig. 2(b)), comprising:
a current source (M11) having a control input (gate) and an output (drain);
a bandgap circuit coupled to the output of the current source (R1-R7, Q6 and Q7); and
an error amplifier circuit (Q1-Q5B, M1-M10 and I1-I5) having a first input (one of the base terminals of Q1 and Q4, i.e., the Q4 of Fig. 2(b) having a collector in common with Q1) and a second input (other one of the base terminals of Q1 and Q4) coupled to the bandgap circuit and output coupled to the control input of the current source (terminal at the drains of M6 and M10), the error amplifier circuit including:
a gain stage circuit (Q3-Q5b, M3-M10 and I5. Note the “gain” stage includes the other Q4 current mirror connected with Q3 and not the Q4 having a common emitter with Q1) having an output coupled to the output of the error amplifier circuit (drains of M6 and M10), and first (one of the sources of M3 and M4) and second inputs (other one of the sources of M3 and M4); and
an input stage circuit (Q1, Q4, i.e., the Q4 of Fig. 2(b) having a collector in common with Q1, I1 and I3-I4) having a first output (one of the collector terminals of Q1 and Q4) and a second output (other one of the collector terminals of Q1 and Q4) coupled to, respectively, the first input and the second input of the gain stage circuit (outputs connected as claimed), the input stage circuit including:
a first transistor (one of Q1 and Q4, i.e., the Q4 of Fig. 2(b) having a collector in common with Q1) including a control terminal coupled to a first input of the error amplifier circuit (base), a first terminal coupled to the first output (collector), and a second terminal (emitter); and
a second transistor (other one of Q1 and Q4) including a control terminal coupled to a second input of the error amplifier circuit (base), a first terminal coupled to the second output (collector), and a second terminal (emitter), wherein the second terminal of the second transistor is coupled to the second terminal of the first transistor (emitters of Q1 and Q4 are connected together), wherein the first transistor and the second transistor are bipolar transistors (Q1 and Q4 are bipolar transistors).
With respect to claim 21, the circuit of claim 1, wherein the first and second transistors are PNP bipolar transistors (the first and second transistors are PNP).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (USPN 9,564,805) in view of Miki et al. (USPN 6,137,363).
With respect to claim 1, Sano et al. discloses, in Fig. 2, circuit (Fig. 2), comprising:
a current source (MP1) having a control input (gate) and an output (drain);
a bandgap circuit coupled to the output of the current source (R1-R3 and R5, Q1 and Q2); and
an error amplifier circuit (A1) having a first input (one of the inverting and noninverting inputs) and a second input (other one of the inverting and noninverting inputs) coupled to the bandgap circuit (at one of VA and VB) and output coupled to the control input of the current source (output of A1 connected to the gate of MP1).
Sano et al. fails to disclose the details of how the amplifier (A1) is constructed. Thus, Sano et al. fails to disclose “the error amplifier circuit including:
a gain stage circuit having an output coupled to the output of the error amplifier circuit, and first and second inputs; and
an input stage circuit having a first output and a second output coupled to, respectively, the first input and the second input of the gain stage circuit, the input stage circuit including:
a first transistor including a control terminal coupled to a first input of the error amplifier circuit, a first terminal coupled to the first output, and a second terminal; and
a second transistor including a control terminal coupled to a second input of the error amplifier circuit, a first terminal coupled to the second output, and a second terminal, wherein the second terminal of the second transistor is coupled to the second terminal of the first transistor, wherein the first transistor and the second transistor are bipolar transistors.”
However, Miki et al. discloses, in Fig. 2, the specific construction of an amplifier circuit including:
a gain stage circuit (30) having an output coupled (To) to the output of the error amplifier circuit (To is the output of the amplifier), and first (one of the gate terminals of Tr30 and Tr33) and second inputs (other one of the gate terminals of Tr30 and Tr33); and
an input stage (50) circuit having a first output (one of drain terminals of Tr53 and Tr54) and a second output (other one of the collector terminals of Tr53 and Tr54) coupled to, respectively, the first input and the second input of the gain stage circuit (outputs connected as claimed), the input stage circuit including:
a first transistor (one of Tr55 and Tr56) including a control terminal (base) coupled to a first input of the error amplifier circuit (one of TIP and TIM, e.g., one of the inverting and noninverting terminals of the amplifier of Miki et al.), a first terminal coupled to the first output (emitter connected to the output via the source to drain path of one of Tr53 and Tr54), and a second terminal (collector); and
a second transistor (other one of Tr55 and Tr56) including a control terminal (base) coupled to a second input of the error amplifier circuit (other one of TIP and TIM, e.g., other one of the inverting and noninverting terminals of the amplifier of Miki et al.), a first terminal coupled to the second output (emitter coupled to the output via the source to drain path of one of Tr53 and Tr54), and a second terminal (collector), wherein the second terminal of the second transistor is coupled to the second terminal of the first transistor (collectors are connected at Vcc node), wherein the first transistor and the second transistor are bipolar transistors (Tr55 and Tr56 are bipolar transistors).
It would have been obvious to replace the generic amplifier A1 of Sano et al. with the specific amplifier of Fig. 2 of Li et al. for the purpose of having a specific amplifier with a high through rate and higher withstand voltage with a reduced amount of circuit components (see Col. 8 line 58 to Col. 9 line 3 of Miki et al.).
With respect to claim 2, the circuit of claim 1, wherein the bandgap circuit (bandgap circuit of Sano et al.) includes:
a third transistor (e.g., Q2) having a control terminal (base), a first terminal (e.g., emitter), and a second terminal (e.g., collector), the control terminal of the third transistor coupled to the first input (e.g., inverting terminal) of the error amplifier circuit (base of Q2 is connected to the inverting terminal of A1 at the VB node Via R2. Note base of Q2 is directly connected to V3, wherein V3 is connected to the inverting terminal via R2), the first terminal of the third transistor coupled to the output of the current source or a reference terminal (emitter connected to ground via R5), and the second terminal of the third transistor coupled to the second input (e.g., noninverting terminal) of the error amplifier circuit (collector connected to the noninverting terminal of A1 via R2 being connected to V3 and V3 being connected to the noninverting terminal via R1); and
a resistor (R2) coupled between the control terminal and the second terminal of the third transistor (R2 connected between base of Q2/V3 and the collector of Q2).
With respect to claim 3, the circuit of claim 2, wherein the resistor is a first resistor (R2 is a first resistor), and bandgap circuit includes:
a fourth transistor (Q1) having a control terminal (base), a first terminal (emitter), and a second terminal (collector), the control terminal of the fourth transistor coupled to the second terminal of the third transistor (the base of Q1 is directly connected to the collector of Q2), the first terminal of the fourth transistor coupled to the output of the current source or the reference terminal (emitter connected to ground via R5), and the second terminal of the fourth transistor coupled to the second input of the error amplifier circuit (collector of Q1 is connected to noninverting terminal of A1); and
a second resistor (R1) coupled between the second terminal of the fourth transistor (collector) and the first input of the error amplifier circuit (noninverting terminal. The collector of Q1 is connected to V3 via R1 and V3 is connected to the inverting terminal via R2. Thus, the collector of Q1 is connected to the first terminal, e.g., the inverting terminal, by at least R1).
With respect to claim 25, the circuit of claim 2, wherein the third transistor is an NPN bipolar transistor (the third transistor is an NPN bipolar transistor).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sano et al. (USPN 9,564,805) in view of Miki et al. (USPN 6,137,363) and in further view of Pietrobon (USPAPN 2009/0039949).
With respect 24, Sano et al. discloses that the bandgap circuit uses NPN transistors. Thus, Sano et al. fails to disclose, “wherein the third transistor is a PNP bipolar transistor”.
However, it is old and well-known to replace NPN bipolar transistors with PNP bipolar transistors in a bandgap circuit since such devices are art recognized equivalents as is evident to one of ordinary skill in the art. This is further evidenced in paragraph 0020 of Pietrobon which discloses: “The invention is not limited to implementation using NPN transistors. Embodiments of a bandgap reference in accordance with the present invention may be implemented using PNP transistors, as would be evident to one skilled in the art” (Examiner’s emphasis). As can be seen it is well-known and within the skill of one of ordinary skill in the art to replace NPN transistors with PNP transistors and that such devices are art recognized equivalents.
It would have been obvious to one of ordinary skill in the art to replace the NPN transistors of the bandgap circuit of Sano et al. with PNP transistors, since it is known to replace such NPN transistors with PNP transistors and within the skill of one of ordinary skill in the art as evidenced by Pietrobon. One would have been motivated to do so depending on the transistor types available at the time of construction of the circuit.
Allowable Subject Matter
Claims 4-7, 22-23 and 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10-16 and 18-19 are allowed.
Conclusion
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849