DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 18/209,801 has a total of 20 preliminary amended claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statements 09/14/2023, 09/28/2023, 10/13/2023, 10/26/2023, 11/09/2023, 11/16/2023, 12/13/2023, 12/21/2023, 02/28/2024, 04/23/2024 and 06/13/2024 are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
OBJECTIONS TO THE CLAIMS
Claims 22-25, 28, 29 33, 34, 38 and 39, are objected to as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
As per claim 22, claim language such as “IOMMU (Input Output Memory Management Unit)” should be rewritten as ‘input output memory management unit (IOMMU)’. Claims 23-25, 33, 34, 38 and 39 have similar/same problem. Correction is needed.
As per claim 28, the phrase ‘read-write’ can be confusing. Claim 29 has similar problem. Correction is needed.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed, approved immediately upon submission, and reduces waiting time for Terminal Disclaimer to be manually approved. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21-40 are rejected on the ground of nonstatutory double patenting over the claims of 1-20 of U.S. Pat. No. 11,720,290; claims of 1-17 of U.S. Pat. No. 11,526,304 and claims of 1-19 of U.S. Pat. No. 10,877,695, since the claims, if allowed, would improperly extend the “right to exclude” already granted in patents. Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is at least fully disclosed in the reference patents and application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 21-40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US pub. # 2013/0326158), hereinafter, “Chen”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claim 21, Chen discloses a method for use in a first computerized device (GPU 114 and memory unit 108B of fig. 1A combined; see paragraphs 0024 and 0025), the first computerized device comprising a memory (memory unit 108B) and communicative with a second computerized device (processing unit 102 and memory unit 108A combined) via a data fabric (MIF 104) (see paragraph 0022, which discloses “Processing unit 102 and GPU 114 may store data in and retrieve data from memory 107 via MIF 104, MMU 105, and memory controllers 106A and 106B”), the method comprising: receiving a first data communication (a write instruction, request, as described below) requiring at least one mapping between a physical address in the memory and an address space (a virtual, logical address) of the second computerized device [see paragraph 0041, which discloses “for instance, referring back to FIG. 1, GPU driver 116 may transmit instructions that cause GPU 114 to store pixel values, and may transmit the virtual addresses for where the pixel value are to be stored” and paragraph 0184, which discloses “FIG. 9 is a flowchart illustrating an example method for determining a memory channel to write data according to some aspects of the present disclosure. As shown in FIG. 9, the MIF 104 may receive a request to write data to a logical memory address of a memory system in a computing device, the logical memory address including a logical page number and a page offset, wherein the logical page number maps to a physical page number and the logical memory address maps to a physical memory address (902)”]; responsive to at least the first data communication, mapping the physical address in the memory to the address space of the second computerized device [see paragraph 0041, which discloses “GPU 114, in turn, may request MIF 104 to store the pixel values in accordance with the virtual addresses” and paragraph 0184, which discloses “MIF 104, MMU 105, processing unit 102, and/or GPU 114 may determine a memory unit out of a plurality of memory units in the memory system by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number (904). Memory controller 106A or 106B may write the data to a physical memory address in the determined memory unit 108A or 108B in memory system 107 (906)”]; and receiving a request (a read request, instruction, from processing unit 102, as discloses in fig. 10) from the second computerized device to access data stored in the physical address in the memory using the mapping [see paragraph 0186, which discloses “MIF 104, MMU 105, processing unit 102, and/or GPU 114 may determine a memory unit out of a plurality of memory units in the memory system by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number (1004). Memory controller 106A or 106B may read the data from a physical memory address in the determined memory unit 108A or 108B in memory system 107 (1006)”].
3. As per claim 22, Chen discloses “The method of Claim 21” [See rejection to claim 1 above], wherein the mapping of the physical address in the memory to the address space of the second computerized device comprises creating the mapping within an IOMMU (Input Output Memory Management Unit) (MMU 105) of the first computerized device (see paragraph 0032, which discloses “MIF 104 may include MMU 105, which may handle requests for access to memory system 107 from processing unit 102, including performing translations of logical memory addresses to physical memory addresses in memory system 107 as well as performing other tasks”).
4. As per claim 23, Chen discloses wherein the creating the mapping within an IOMMU (Input Output Memory Management Unit) of the first computerized device comprises mapping at least one address window to the physical address (see paragraph 0105).
5. As per claim 24, Chen discloses, further comprising generating at least one base physical address associated with the window (see paragraph 0105).
6. As per claim 25, Chen discloses, further comprising causing provision of the at least one base physical address associated with the window to the second computerized device (see paragraph 0139).
7. As per claim 26, Chen discloses, wherein the mapping the physical address in the memory to the address space of the second computerized device comprises mapping at least one address window to the physical address (see paragraph 0139).
8. As per claim 27, Chen discloses wherein the mapping the physical address in the memory to the address space of the second computerized device further comprises enabling access to the at least one address window by the second computerized device (see paragraph 0186).
9. As per claim 28, Chen discloses wherein the enabling access to the at least one address window by the second computerized device comprises enabling read-write access by the second computerized device (see paragraph 0186).
10. As per claim 29, Chen discloses wherein the enabling access to the at least one address window by the second computerized device comprises enabling read-only access by the second computerized device (see paragraph 0184).
11. As per claim 30, Chen discloses wherein the receiving the first data communication comprises receiving a mapping request issued by the second computerized device, the mapping request issued by the second computerized device and transmitted to the first computerized device via at least the data fabric(see paragraph 0041).
12. As per claim 31, Chen discloses, further comprising receiving a second data communication issued by the second computerized device, the second data communication configured to determine whether the first computerized device has data corresponding to a prescribed identifier stored in the memory (see paragraph 0186).
13. As per claim 32, Chen discloses a computerized device (processing unit 102, MIF 104 and memory unit 108A combined), the computerized device comprising: a data memory (memory unit 108A); a processor (processing unit 102) in data communication with the data memory (see paragraph 0184, which discloses “MIF 104, MMU 105, processing unit 102, and/or GPU 114 may determine a memory unit out of a plurality of memory units in the memory system by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number (904). Memory controller 106A or 106B may write the data to a physical memory address in the determined memory unit 108A or 108B in memory system 107 (906)”]); a data interface (MIF 104) enabling data communication with at least one other computerized device (GPU 114 and memory unit 108B of fig. 1A combined; see paragraphs 0022 and 0024); and computerized logic configured to: generate a first data communication (a first write instruction, request, as described below) configured to request at least one mapping between a physical address in a memory of a second computerized device (GPU 114 and memory unit 108B of fig. 1A combined) and an address space of the computerized device (see paragraph 0041, which discloses “for instance, referring back to FIG. 1, GPU driver 116 may transmit instructions that cause GPU 114 to store pixel values, and may transmit the virtual addresses for where the pixel value are to be stored” and paragraph 0184, which discloses “FIG. 9 is a flowchart illustrating an example method for determining a memory channel to write data according to some aspects of the present disclosure. As shown in FIG. 9, the MIF 104 may receive a request to write data to a logical memory address of a memory system in a computing device, the logical memory address including a logical page number and a page offset, wherein the logical page number maps to a physical page number and the logical memory address maps to a physical memory address (902)”]; cause transmission of the first data communication to the second computerized device via at least a data fabric in data communication with the data interface [see paragraph 0041, which discloses “GPU 114, in turn, may request MIF 104 to store the pixel values in accordance with the virtual addresses” and paragraph 0184, which discloses “MIF 104, MMU 105, processing unit 102, and/or GPU 114 may determine a memory unit out of a plurality of memory units in the memory system by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number (904). Memory controller 106A or 106B may write the data to a physical memory address in the determined memory unit 108A or 108B in memory system 107 (906)”]; receive via the data interface a second data communication (a read data, from processing unit 102, as discloses in fig. 10), the second data communication configured to provide data to the computerized device relating to the mapping of the physical address in the memory of the second computerized device to the address space of the computerized device [see paragraph 0186, which discloses “MIF 104, MMU 105, processing unit 102, and/or GPU 114 may determine a memory unit out of a plurality of memory units in the memory system by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number (1004). Memory controller 106A or 106B may read the data from a physical memory address in the determined memory unit 108A or 108B in memory system 107 (1006)”]; and generate a third data communication (a second write instruction, request) configured to request access to data stored in the physical address using at least a portion of the provided data relating to the mapping (see paragraph 0041 and 0184).
14. As per claim 33, Chen discloses wherein at least the computerized device and the data fabric reside on a single SoC (system on chip) semiconductor die (integrated circuit 101; see paragraph 0024).
15. As per claim 34, Chen discloses wherein at least the second computerized device and the data fabric reside on a single SoC (system on chip) semiconductor die (integrated circuit 101; see paragraph 0024).
16. As per claim 35, Chen discloses wherein at least the computerized device, the second computerized device, and the data fabric reside on a common substrate (see paragraph 0024).
17. As per claim 36, Chen discloses, wherein the generation of the first data communication configured to request at least one mapping between a physical address in a memory of a second computerized device and an address space of the computerized device is responsive to a data access request from at least one of (i) the processor, or (ii) a second processor in data communication with the computerized device (see paragraphs 0041 and 0184).
18. As per claim 37, Chen discloses wherein the provided data relating to the mapping of the physical address in the memory of the second computerized device to the address space of the computerized device comprises at least one base address relating to an address window (see paragraph 0105).
19. As per claim 38, Chen discloses further comprising an IOMMU (Input Output Memory Management Unit), and wherein the computerized logic is further configured to utilize the provided data relating to the mapping of the physical address in the memory of the second computerized device to the address space of the computerized device to modify at least one aspect of the IOMMU to support access to the physical address (see paragraph 0105).
20. As per claim 39, Chen discloses wherein the modification of the at least one aspect of the IOMMU to support access to the physical address comprises producing a mapping of at least one address within the data memory to the physical address (see paragraph 0105).
21. As per claim 40, Chen discloses a method for use in a first computerized node (IC 101 of fig. 1A, as disclose in paragraphs 0024 and 0025), the first computerized node comprising a memory (memory system 107), a data interface (MIF 104), a host processor (processing unit 102), and a second processor (GPU 114, the first computerized node configured for communication with a computerized device (another device, as discloses in paragraph 0191) via a data fabric (transceiver module 1106 of fig. 11, as discloses in paragraphs 0189 and 0191) via at least the data interface (see paragraphs 0189 and 0191), the method comprising: receiving, at the second processor (GPU 114), a first data communication (a first write instruction, request, as discloses below) issued by the host processor (processing unit 102); based at least on the received first data communication, generating a second data communication (a request from GPU 114 as a result of receiving the write instruction, as discloses below) configured to request at least one mapping between at least one address in a memory (memory of the ‘another device’) of the computerized device (the another device, as discloses in paragraph 0191) and an address space of the first computerized node (IC 101) (see fig. 11 and see paragraph 0041, which discloses “for instance, referring back to FIG. 1, GPU driver 116 may transmit instructions that cause GPU 114 to store pixel values, and may transmit the virtual addresses for where the pixel value are to be stored” and paragraph 0184, which discloses “FIG. 9 is a flowchart illustrating an example method for determining a memory channel to write data according to some aspects of the present disclosure. As shown in FIG. 9, the MIF 104 may receive a request to write data to a logical memory address of a memory system in a computing device, the logical memory address including a logical page number and a page offset, wherein the logical page number maps to a physical page number and the logical memory address maps to a physical memory address (902)”]; causing transmission of the second data communication to the computerized device via at least a data fabric in data communication with the data interface [see paragraph 0041, which discloses “GPU 114, in turn, may request MIF 104 to store the pixel values in accordance with the virtual addresses”, paragraph 0184, which discloses “MIF 104, MMU 105, processing unit 102, and/or GPU 114 may determine a memory unit out of a plurality of memory units in the memory system by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number (904). Memory controller 106A or 106B may write the data to a physical memory address in the determined memory unit 108A or 108B in memory system 107 (906)” and paragraph 0191, which discloses “Transceiver module 1106 may include circuitry to allow wireless or wired communication between device 100 and another device or a network”]; receiving via the data interface a third data communication (a second write instruction/request/data from ‘another device’ to processing unit 102; see fig. 11 and paragraph 0191), the third data communication configured to provide data to the first computerized node relating to the mapping of the at least one address in the memory of the computerized device to the address space of the first computerized node (see paragraphs 0041, 0184 and 0191); and generate a fourth data communication (a read data to processing unit 102) configured to provide at least a portion of the provided data relating to the mapping to the host processor (see paragraph 0186).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as
recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 21-40 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The
Examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the
Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number:
Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217- 91 97 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181