DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 3/5/2026 have been fully considered but they are not persuasive.
Applicant’s assertion that prior art document US 20170278916 A1 (Maruyama) does not disclose the limitation “a conductive pattern directly above at least one of the first semiconductor pattern and the second semiconductor pattern” (Applicant’s remarks page 9) is acknowledged. However, it is unpersuasive for the following reasons:
As was described in the Office action mailed 12/29/2025, the unlabeled conductive pattern in Maruyama FIG. 4 is configured such that it overlaps the CH2 semiconductor pattern of the leftmost illustrated transistor along a vertical direction. The overlap is found to satisfy the “directly above” provision of the limitation as direct contact is not required for one object to be directly above another (e.g. a helicopter may be hovering directly above a person while not being in direct contact with said person). Therefore, the disclosure of Maruyama is found to anticipate the claimed invention as it is currently presented.
Claim 22 now depends on claim 2, remedying the issue that led to that claim’s rejection under 35 U.S.C. 112(b), which is hereby withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4-5, 19, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20170278916 A1 (Maruyama).
Regarding claim 1, Maruyama discloses an organic light emitting display device (the device illustrated in FIG. 4 ¶ [0003, 0014]) comprising: a substrate (FIG. 4, first substrate 10 ¶ [0019]) including a display area (FIG. 4, display region DR ¶ [0023]) and a non-display area (FIG. 4, peripheral region PR ¶ [0023]) in a vicinity of the display area; an upper buffer layer (FIG. 4, unlabeled buffer layers directly below second channel layers CH2 and directly on first gate electrode GE1, on first substrate 10 ¶ [0026]) on the substrate;
a first thin film transistor (FIG. 4, first thin film transistor TFT1 ¶ [0025]) including a first semiconductor pattern (FIG. 4, first channel layer CH1 ¶ [0025]) and a first gate electrode (FIG. 4, first gate electrode GE1 ¶ [0025]), the first semiconductor pattern under the upper buffer layer (FIG. 4, channel layer CH1 is below the unlabeled buffer layers below second channel layers CH2 and above first gate electrode GE1); a second thin film transistor (FIG. 4, second thin film transistor TFT2 shown on the left ¶ [0026]) including a second semiconductor pattern (FIG. 4, second channel layer CH2 ¶ [0026]) and a second gate electrode (FIG. 4, second gate electrode GE2 ¶ [0026]), the second semiconductor pattern above the upper buffer layer (FIG. 4, channel layer CH2 is above the unlabeled buffer layer directly below second channel layers CH2);
a conductive pattern (FIG. 4, unlabeled conductive pattern directly above left second source electrode SE2 and under pixel electrode 18 ¶ [0026]) directly above at least one of the first semiconductor pattern and the second semiconductor pattern (FIG. 4, the unlabeled conductive pattern in question is above both semiconductor patterns, and overlaps the second semiconductor pattern; the overlap is found to satisfy the ‘directly above’ limitation, as direct contact is not required to be directly above an object, e.g. a helicopter may be hovering directly above a person without directly contacting said person); and a storage capacitor (FIGS. 3-4, capacitor C, which is connected to TFT2 through source electrode SE2 ¶ [0023]) connected to the second thin film transistor.
Regarding claim 4, Maruyama discloses the limitations of claim 1 as detailed above, and further discloses that the first thin film transistor is in one of the display area and the non-display area (FIG. 4, TFT1 is in the non-display peripheral region PR), and wherein the second thin film transistor is in the display area (FIG. 4, TFT2 is in display region DR).
Regarding claim 5, Maruyama discloses the limitations of claim 4 as detailed above, and further discloses that the first semiconductor pattern comprises a polycrystalline semiconductor pattern (first channel layer CH1 is low temperature polysilicon ¶ [0025]), and the second semiconductor pattern comprises an oxide semiconductor pattern (second channel layer CH2 is an oxide semiconductor ¶ [0026]).
Regarding claim 19, Maruyama discloses the limitations of claim 1 as detailed above, and further discloses that the first thin film transistor comprises a first source electrode and a first drain electrode (FIG. 4, TFT1 includes first source electrode SE1 and first drain electrode DE1 ¶ [0025]), wherein the second thin film transistor comprises a second source electrode and a second drain electrode (FIG. 4, TFT2 includes second source electrode SE2 and second drain electrode DE2 ¶ [0026]), wherein the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the second gate electrode are disposed in a same layer (FIG. 4, the unlabeled layer that surrounds sidewalls and the upper surface of second gate electrode GE2 also has each of the source electrodes SE1 and SE2 and the drain electrodes DE1 and DE2 running through it).
Regarding claim 21, Maruyama discloses the limitations of claim 1 as detailed above, and further discloses that the second thin film transistor is configured to drive a unit pixel in the display area (FIG. 3-4, TFT2, which can be seen to drive the pixel based on the circuit diagram view of FIG. 3, since each of switching transistors SW1 and SW2 have the structure of TFT2 ¶ [0028], TFT2 is configured to drive the unit pixel display element DE ¶ [0023]).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20170278916 A1 (Maruyama) as applied to claim 1 above, and further in view of US patent publication US 20180012947 A1 (Lee et al hereinafter Lee).
Maruyama discloses the limitations of claim 1 as detailed above, and further discloses that the second thin film transistor comprises a second source electrode (FIG. 4, second source electrode SE2 ¶ [0026]) and a second drain electrode (FIG. 4, second drain electrode DE2 ¶ [0026]) disposed above the upper buffer layer (FIG. 4, electrodes SE2 and DE2 extend to positions above the unlabeled buffer layers). Maruyama does not further disclose a second light blocking pattern is below the second semiconductor pattern and is connected to one of the second source electrode and the second drain electrode.
However, Lee discloses an organic light emitting display device (the device of FIG. 6C ¶ [0040]) comprising a second light blocking pattern (FIG. 6C, BSM 617 ¶ [0137]) below a second semiconductor pattern (FIG. 6C, active layer 131 ¶ [0068]) and is connected to one of a second source electrode and a second drain electrode (FIG. 6C, BSM 617 connects to a source electrode 632 of transistor 630 ¶ [0136]). Lee also teaches that the second light blocking pattern may block laser irradiation as well as hydrogen or moisture, protecting the transistor from certain types of defects.
Maruyama and Lee both pertain to the field of OLED display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Maruyama in view of Lee to further include a second light blocking pattern is below the second semiconductor pattern and is connected to one of the second source electrode and the second drain electrode, in order to protect the second thin film transistor from certain types of defects as taught by Lee.
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama in view of Lee as applied to claim 2 above, and further in view of US patent publication US 20210320162 A1 (Jeon et al hereinafter Jeon).
Regarding claim 3, Maruyama in view of Lee discloses the limitations of claim 2 as detailed above, and further discloses that the second light blocking pattern is in the upper buffer layer (incorporating the light blocking pattern of Lee FIG. 6C into the device of Maruyama FIG. 4 may be done by disposing the light blocking pattern in the unlabeled buffer layer directly under second channel layer CH2, which is part of the claimed upper buffer layer), wherein the second gate electrode is above the second semiconductor pattern with a second gate insulating layer interposed therebetween (Maruyama FIG. 4, the unlabeled space between second channel layer CH2 and second gate electrode GE2 is a second gate insulating layer). Maruyama in view of Lee does not further disclose that a parasitic capacitance between the second light blocking pattern and the second semiconductor pattern is greater than a parasitic capacitance between the second gate electrode and the second semiconductor pattern, such a comparison of parasitic capacitances not being a feature of particular pertinence to the disclosure of their invention.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to have such a configuration in view of Jeon, which discloses a display device (Title, Abstract) wherein parasitic capacitance is determined by the thickness of gate dielectrics/insulation layers (¶ [0090-0091]). The thicknesses of the gate dielectrics and insulation layers are therefore result-effective variables. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of the second gate insulating layer and the portion of the upper buffer layer separating the second light blocking pattern from the second semiconductor pattern, since Jeon has demonstrated those thicknesses to be result-effective variables. A person of ordinary skill in the art would further have had a reasonable expectation of success to arrive at a thickness relationship wherein a parasitic capacitance between the second light blocking pattern and the second semiconductor pattern is greater than a parasitic capacitance between the second gate electrode and the second semiconductor pattern, in order to balance the performance characteristics of the transistor of Maruyama having included the light blocking pattern of Lee (MPEP 2144.05).
Furthermore, the applicant has not presented persuasive evidence that the claimed relationship of parasitic capacitances is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed relationship).
Regarding claim 6, Maruyama in view of Lee and Jeon discloses the limitations of claim 3 as detailed above, and they further disclose that a first sub-upper buffer layer constituting a part of the upper buffer layer is under the second light blocking pattern (Maruyama FIG. 4, the unlabeled buffer layer directly on second conductive layer CL2 is a first sub-buffer layer which is under the second light blocking pattern when the light blocking pattern of Lee FIG. 6C is incorporated and disposed in the unlabeled buffer layer directly under second channel layer CH2), and a second sub-upper buffer layer constituting a part of the upper buffer layer is above the second light blocking pattern (Maruyama FIG. 4, the unlabeled buffer layer directly under second channel layer CH2 is a second sub-upper buffer layer which is located above the second light blocking pattern when the light blocking pattern of Lee FIG. 6C is incorporated and disposed under that layer).
Claims 7, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama in view of Lee as applied to claim 2 above, and further in view of US patent publication US 20250024711 A1 (Kim et al hereinafter Kim).
Regarding claim 7, Maruyama in view of Lee discloses the limitations of claim 2 as detailed above, and they further disclose that the storage capacitor comprises: a first electrode (Maruyama FIG. 4, second conductive layer CL2 ¶ [0030]) of the storage capacitor in a same layer as the first gate electrode (Maruyama FIG. 4, second conductive layer CL2 and first gate electrode GE1 are in the same unlabeled buffer layer). Maruyama in view of Lee does not further disclose that a second electrode of the storage capacitor in a same layer as the second light blocking pattern; and a third electrode of the storage capacitor in a same layer as the conductive pattern.
However, Kim discloses a display device (the device of FIGS. 5-6 ¶ [0035-0036]) which comprises a storage capacitor (FIGS. 5-6, capacitors C1, C2, and C3 configured in parallel form a storage capacitor ¶ [0076]) and a second light blocking pattern (FIG. 5, second base metal layer 132 ¶ [0048]), wherein the storage capacitor comprises: a first electrode (FIG. 5, first conductive layer 133 is an electrode of capacitors C1 and C2 ¶ [0048, 0075]) of the storage capacitor in a same layer as the first gate electrode (FIG. 5, gate electrode 122 and first conductive layer 133 are in the same interlayer insulating layer 101c ¶ [0052]); a second electrode (FIG. 5, first base metal layer 131 is an electrode of capacitor C1 ¶ [0048, 0075]) of the storage capacitor in a same layer as the second light blocking pattern (FIG. 5, first and second base metal layers 131 and 132 are formed in the same buffer layer 101a ¶ [0052]); and a third electrode (FIG. 5, fourth conductive layer 135 is an electrode of capacitor C3, ¶ [0074-0075]) of the storage capacitor in a same layer as a conductive pattern (FIG. 5, ITO layer 115 ¶ [0054], which is in via layer 101e with fourth conductive layer 135 ¶ [0056]). Kim also teaches that their parallel capacitor configuration allows for a stable voltage to be provided to the driving transistor (¶ [0076]).
Maruyama, Lee, and Kim all pertain to the field of OLED display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Maruyama in view of Lee further in view of Kim such that the capacitor structure of Kim is employed, resulting in a configuration wherein the storage capacitor comprises: a first electrode of the storage capacitor in a same layer as the first gate electrode; a second electrode of the storage capacitor in a same layer as the second light blocking pattern; and a third electrode of the storage capacitor in a same layer as the conductive pattern, in order to achieve a stable voltage to be provided to the driving transistor by using the parallel capacitor structure as taught by Kim.
Regarding claim 14, Maruyama in view of Lee and Kim discloses the limitations of claim 7 as detailed above, and they further disclose that the second gate electrode and the second source electrode are disposed in a same layer as each other (Maruyama FIG. 4, second gate electrode GE2 and second source electrode SE2 are disposed in the same unlabeled buffer layer since SE2 extends through it).
Regarding claim 18, Maruyama in view of Lee and Kim discloses the limitations of claim 7 as detailed above, and they further disclose that the third electrode of the storage capacitor is connected to another electrode of the storage capacitor through a contact hole (Kim FIG. 5, fourth conductive layer 135 of capacitor C3, being the third electrode, is connected to first conductive layer 133 of capacitors C1 and C2 through an unlabeled contact hole that penetrates through passivation layer 101d ¶ [0056]), and the third electrode of the storage capacitor is in contact with a side of the contact hole (Kim FIG. 5, fourth conductive layer 135 contacts sidewalls of the unlabeled contact hole).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Maruyama as applied to claim 1 above, and further in view of Kim.
Maruyama discloses the limitations of claim 1 as detailed above, and further discloses that the storage capacitor comprises a first electrode (FIG. 4, second conductive layer CL2 ¶ [0030]) of the storage capacitor in a same layer as the first gate electrode (FIG. 4, layer CL2 and first gate electrode GE1 are in the same unlabeled buffer layer). Maruyama does not disclose that a second electrode of the storage capacitor is in a same layer as a second light blocking pattern.
However, Kim discloses a display device (the device of FIGS. 5-6 ¶ [0035-0036]) which comprises a storage capacitor (FIGS. 5-6, capacitors C1, C2, and C3 configured in parallel form a storage capacitor ¶ [0076]) and a second light blocking pattern (FIG. 5, second base metal layer 132 ¶ [0048]), wherein a second electrode of the storage capacitor is in a same layer as the second light blocking pattern (FIG. 5, first base metal layer 131 which is part of capacitor C1 and second base metal layer 132 are formed in the same buffer layer 101a ¶ [0052]). Kim also discloses that their light blocking pattern blocks light from entering or exiting the substrate which prevents or reduces intermixing of external light with the light emitted by the device, as well as that their parallel capacitor configuration allows for a stable voltage to be provided to the driving transistor (¶ [0048, 0053, 0076]).
Maruyama and Kim both pertain to the field of OLED display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Maruyama in view of Kim such that a second electrode of the storage capacitor is in a same layer as a second light blocking pattern, in order to make use of the parallel capacitor and light blocking structures of Kim to achieve a reduced intermixing of external light with the light emitted by the device, as well as a stable voltage to be provided to the driving transistor as taught by Kim.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent US 12514064 B2 and US patent publication US 20210399142 A1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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