Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: claims 1-20 are directed to either a process, machine, manufacture or composition of matter.
With respect to claims 1, 8, 15:
2A Prong 1:
constructing a hardware model of the neural network structure based on the obtained type information, wherein the hardware model comprises one or more paths for performing arithmetic operations (mental process of modeling with assistance of pen and paper; a hardware model can fundamentally amount to algorithms, software, or designs drawn on paper by a human);
formulating an optimization problem “to reduce the quantization errors” (intended use) based on the constructed hardware model (reads on model drawn on paper), wherein the optimization problem is defined by an objective function and a set of constraints (mental process – user can manually perform raw thinking in their head as a first stage and then using paper and pen to perform mathematical operation);
solving, by a computer, the optimization problem(mental process – user can manually perform raw thinking in their head as a first stage and then using paper and pen to perform mathematical operation);
and configuring the hardware device based on a solution to the optimization problem, thereby reducing the quantization errors at the output of the hardware device (mental process of modeling with assistance of pen and paper; a hardware model can fundamentally amount to algorithms, software, or designs drawn on paper by a human).
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
computer-implemented method for reducing quantization errors at an output of a hardware device functioning as a neural network structure, the method comprising, processor, storage device (computer component is recited at a high level of generality and amounts to no more than mere instructions to apply the exception using a generic computer component; the mere recitation of a generic computer cannot transform a patent-ineligible abstract idea into a patent-eligible invention." Alice, 134 S. Ct. at 2358);
Claim 8 computer readable medium for storing instructions (Adding insignificant extra-solution activity to the judicial exception - see MPEP 2106.05(g));
obtaining type information associated with the [neural network] structure (mere data gathering and output recited at a high level of generality - insignificant extra-solution activity to the judicial exception - see MPEP 2106.05(g));
Neural network (provides nothing more than mere instructions to implement an abstract idea on a generic computer; the NN is used to generally apply the abstract idea without limiting how the trained NN functions).
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
computer-implemented method for reducing quantization errors at an output of a hardware device functioning as a neural network structure, the method comprising, processor, storage device (computer component is recited at a high level of generality and amounts to no more than mere instructions to apply the exception using a generic computer component; the mere recitation of a generic computer cannot transform a patent-ineligible abstract idea into a patent-eligible invention." Alice, 134 S. Ct. at 2358);
Claim 8 computer readable medium for storing instructions (Adding insignificant extra-solution activity to the judicial exception - see MPEP 2106.05(g));
obtaining type information associated with the neural network structure (mere data gathering and output recited at a high level of generality - insignificant extra-solution activity to the judicial exception - see MPEP 2106.05(g));
Neural network (provides nothing more than mere instructions to implement an abstract idea on a generic computer; the NN is used to generally apply the abstract idea without limiting how the trained NN functions).
Further, the obtaining steps were considered to be extra-solution activity in Step 2A Prong 2, and thus it is re-evaluated in Step 2B to determine if it is more than what is well-understood, routine, conventional activity in the field. The receiving and/or transmitting limitations constitute extra-solution activity. See buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355 (Fed. Cir. 2014) ("That a computer receives and sends the information over a network-with no further specification-is not even arguably inventive."). The court decisions cited in MPEP 2106.05(d)(II) indicate that merely Receiving and/or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information). Thereby, a conclusion that the claimed receiving/transmitting steps are well-understood, routine, conventional activity is supported under Berkheimer. The claim is not patent eligible.
2, 8, 16. The computer-implemented method of claim 1, wherein the hardware device (computer component is recited at a high level of generality and amounts to no more than mere instructions to apply the exception using a generic computer component; the mere recitation of a generic computer cannot transform a patent-ineligible abstract idea into a patent-eligible invention." Alice, 134 S. Ct. at 2358) comprises at least a multiplier or an accumulator, an adder, and a number of bit- shifting units (further defining mental process – user can manually perform raw thinking in their head as a first stage and then using paper and pen to perform mathematical operation for the purposes of modeling).
3, 10, 17. The computer-implemented method of claim 2, wherein the bit-shifting units comprise a set of right bit-shifting units and a set of left bit-shifting units, and wherein the objective function is to minimize a weighted sum of bit shifts of the set of right bit-shifting units (further defining mental process – user can manually perform raw thinking in their head as a first stage and then using paper and pen to perform mathematical operation for the purposes of modeling).
4, 11, 18. The computer-implemented method of claim 3, wherein a weight factor associated with a right bit-shifting unit is inversely correlated with a distance between the right bit-shifting unit and an input stage of the hardware device(further defining mental process – user can manually perform raw thinking in their head as a first stage and then using paper and pen to perform mathematical operation for the purposes of modeling).
5, 12, 19. The computer-implemented method of claim 2, wherein the set of constraints comprises at least: a set of hardware constraints based on sizes of the bit-shifting units; and a set of operation-specific constraints comprising at least a first equality constraint between quantization scales of inputs of an adder and a second equality constraint between quantization scales of input and output of a path for performing arithmetic operations(further defining mental process – user can manually perform raw thinking in their head as a first stage and then using paper and pen to perform mathematical operation for the purposes of modeling).
6, 13, 20. The computer-implemented method of claim 5, wherein solving the optimization problem comprises performing a brute-force search in a search space defined by the hardware constraints(further defining mental process – user can manually perform raw thinking in their head as a first stage and then using paper and pen to perform mathematical operation for the purposes of modeling).
7, 14. The computer-implemented method of claim 1, wherein the neural network structure comprises one of: a single-path residual block; a multi-path-with-concatenation residual block; and a residual block with multiple pruning channels(further defining mental process – user can manually perform raw thinking in their head as a first stage and then using paper and pen to perform mathematical operation for the purposes of modeling).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chai (US 2021/0241108) teaches neural network models (0005), hardware modules and platforms (0046, 0067, 0118-9), optimizations (0053), bit-shifting (0092, 0120), quantization errors (0113).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID R VINCENT whose telephone number is (571)272-3080. The examiner can normally be reached ~Mon-Fri 12-8:30.
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/DAVID R VINCENT/Primary Examiner, Art Unit 2123
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