DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 18 July 2023, 01 July 2024, 17 July 2024, and 24 October 2024 were filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings are objected to because the Drawings are presented with missing numbering pattern. Fig. 3 starts with Fig. 3C; Fig. 4 starts with Fig. 4G; and Fig. 5 starts with Fig. 5I . See MPEP § 1606 , “(t) Numbering of sheets of drawings. The sheets of drawings should be numbered in consecutive Arabic numerals, starting with 1, within the sight as defined in paragraph (g) of this section ” . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: See the Drawing Objections . Appropriate correction is required in the Specification corresponding to the Figure number descriptions in the Specification. Claim Objections Claim 3 and 14 are objected to because of the following informalities : In claim 3, line 3 : “ assembly storing step include: ” should read: -- assembly storing step include s : -- In claim 14, lines 2-5 : “w herein in at least one linear body group, arrangement pitches, each of which is a distance between separately arranged two adjacent linear bodies, partly differ from each other. ” should read: -- wherein in at least one linear body group arrangement pitch, a distance between separately arranged two adjacent linear bodies, is differ ent from the other linear body group arrangement pitch . -- Note: the term “part l y differ” is not a standard term. The recited pitch es would be either “ same ” or “ different ” unless otherwise defined. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1- 2, 4, 7, 10-11, 15-1 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki (US 20120297608) in view of Hideki (JP 2000269102). 4694555 1220013 jig 0 jig 4352519 1049350 0 997075 579020 0 0 -38049 664033 chip storing portion 0 chip storing portion Annotated Fig. 4, Miyazaki . Regarding claim 1, Miyazaki taches, a method for manufacturing a ceramic electronic component ( electronic components 1 , Figs. 1 to 19, para. [0002]), the method comprising: a ceramic chip element assembly production step of producing a plurality of ceramic chip element assemblies ( electronic components 1, first internal electrodes 2 and second internal electrodes 3 are arranged so as to be stacked on each other with ceramic layers disposed therebetween, within a ceramic body having a rectangular parallelepiped shape , para. [0047] ); a jig preparation step of preparing a jig (alignment jig 12 including guide plate 13 , see annotated Fig. 4 , aligning jig 12 … plate-shaped member is preferably formed by stacking a plurality of sheets , para. [0059] ) provided with a plurality of chip storing portions (a ccommodating recesses 15 , plurality of accommodating recesses 15 opening on the upper surface 12a are provided , para. [0059] ) including a bottom portion to support a ceramic chip element assembly from below (see Fig. 4 above) and an open-top side wall portion (see Fig s . 4 and 8, a plurality of electronic components 1 are aligned and held by the component aligning jig 12 , para. [0078]) ; a ceramic chip element assembly storing step of storing the ceramic chip element assemblies into the chip storing portions of the jig in a one-to-one correspondence ( see Fig. 8, vibration is applied to the feed-in jig 14, thereby accommodating the electronic components 1 into the individual recesses 14b …t he electronic components 1 to which vibration has been applied reach the inside of the above-mentioned accommodating recesses 15 of the component aligning jig 12 , para. [0071, 0075]) ; a ceramic chip element assembly working step of working the ceramic chip element assemblies stored in the chip storing portions of the jig ( conductive paste can be applied to the WT surface with high precision as shown in FIG. 10B … the conductive paste is dried, and further, conductive paste is also applied to the WT surface on the opposite side in the same manner as mentioned above. Thereafter, by heating the electronic components 1 applied with the conductive paste to fire the conductive paste, para. [0080-0081]) ; and a ceramic chip element assembly removal step of removing the ceramic chip element assemblies from the chip storing portions of the jig ( electronic components can be completed, and the precision of external electrodes can be enhanced , para. [0081] , in which it is obvious that the ceramic chip element s are removed from storing portions of the jig ) . Miyazaki does not explicitly teach a ceramic chip element assembly production step . However, Hideki teaches a method for manufacturing a ceramic electronic component including a jig preparation step, assembly storing step, assembly working step, and a ceramic chip element assembly production step of producing a plurality of ceramic chip element assemblies ( manufactur ing of multilayer capacitors, a large number of internal electrodes are formed on the surface of a dielectric green sheet, a plurality of these dielectric green sheets are laminated and pressed together, the laminate is then cut into a large number of chip pieces, para. [0002]). Therefore, in view of the teachings of Hideki , it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to include a step for producing the ceramic chip element from a laminated dielectric green sheet as Hideki disclosed in para. [0002] so that it enables forming large number of ceramic chip elements from a laminated ceramic green sheet while manufacturing a ceramic electronic component . Regarding claim 2, Miyazaki in view of Hideki taches the recited limitations with respect to claim 1. Miyazaki further teaches, t he method for manufacturing a ceramic electronic component according to Claim 1, wherein the ceramic chip element assembly working step includes a firing step ( heating the electronic components 1 applied with the conductive paste to fire the conductive paste , para. [0081]) . Regarding claim 4, Hideki further teaches, the method for manufacturing a ceramic electronic component according to Claim 1, wherein the ceramic chip element assembly production step includes: a mother ceramic green sheet production step of producing a mother ceramic green sheet including a plurality of ceramic green sheets; a mother ceramic green sheet multilayer body production step of producing a mother ceramic green sheet multilayer body by stacking and integrating a plurality of mother ceramic green sheets; and a mother ceramic green sheet multilayer body cutting step of cutting the mother ceramic green sheet multilayer body into individual ceramic chip element assemblies ( a large number of internal electrodes are formed on the surface of a dielectric green sheet, a plurality of these dielectric green sheets are laminated and pressed together, the laminate is then cut into a large number of chip pieces , para. [0002]) . Therefore, in view of the teachings of Hideki, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to include a step for producing the ceramic chip element from a laminated dielectric green sheet as Hideki disclosed in para. [0002] so that it enables forming large number of ceramic chip elements from a laminated ceramic green sheet. Regarding claim 7, Hideki further teaches, the method for manufacturing a ceramic electronic component according to Claim 1, wherein an outer electrode paste application step of coating an outer surface of the fired ceramic chip element assembly and an outer electrode paste baking step of baking the outer electrode paste onto the outer surface of the ceramic chip element assembly are included after the ceramic chip element assembly working step ( a plurality of these dielectric green sheets are laminated and pressed together, the laminate is then cut into a large number of chip pieces, and these chip pieces are pre-fired by heating them … followed by high-temperature firing , and then external electrodes are formed on both the left and right end faces of each chip piece … they are fired at a high temperature , para. [0002-0003 ] ) . Therefore, in view of the teachings of Hideki, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to include a step for producing the ceramic chip element from a laminated dielectric green sheet as Hideki disclosed in para. [0002] so that it enables sintering the mother ceramic green sheet and to cut into a number of chip element assembly pieces before applying an outer electrode . Regarding claim 10, Miyazaki in view of Hideki taches the recited limitations with respect to claim 1. Miyazaki further teaches, the method for manufacturing a ceramic electronic component according to Claim 1, wherein the jig includes ceramic as a raw material ( component aligning jig 12 mentioned above can be formed by ,… laminating sheets made of an appropriate material such as ceramic , para. [0069]) . Regarding claim 11, Miyazaki in view of Hideki taches the recited limitations with respect to claim 1. Miyazaki further teaches, the method for manufacturing a ceramic electronic component according to Claim 1, wherein the jig is produced from a plurality of linear bodies (see Fig. 4, component aligning jig 12 mentioned above can be formed by,…laminating sheets made of an appropriate material such as ceramic, para. [0069 ]) . Regarding claim 15, Miyazaki in view of Hideki taches the recited limitations with respect to claim 1. Miyazaki further teaches, the method for manufacturing a ceramic electronic component according to Claim 1, wherein in the jig, the chip storing portions are formed in a matrix on the main surface of the jig (see the array of recess 15 in aligning jig 12 in annotated Fig. 8) . 2710116 -486626 0 0 2599538 64871 matrix 0 matrix Annotated Fig. 8, Miyazaki . Regarding claim 16, Miyazaki in view of Hideki taches the recited limitations with respect to claim 1. Miyazaki further teaches, the method for manufacturing a ceramic electronic component according to Claim 1, wherein the jig is divisible into a plurality of portions in the height direction ( see the recess 15 in Fig. 8 ) . Regarding claim 1 7 , Miyazaki in view of Hideki taches the recited limitations with respect to claim 1. Miyazaki further teaches, the method for manufacturing a ceramic electronic component according to Claim 1, wherein an area surrounded by the side wall portion of the chip storing portion increases from a lower section toward an upper section of the jig (see annotated Fig. 5B below) . 3993185 879831 lower section 0 lower section 4029837 374929 upper section 0 upper section 3013075 1033780 0 3049905 536575 0 Annotated Fig. 5B, Miyazaki. Regarding claim 19, Miyazaki in view of Hideki taches the recited limitations with respect to claim 1. Miyazaki further teaches, the method for manufacturing a ceramic electronic component according to claim 1, wherein the ceramic electronic component is a multilayer ceramic capacitor ( electronic components 1 to be aligned … are multilayer capacitor chips , para. [0047]) . Claim(s) 5-6 and 8-9 a re rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Hideki as applied to claim 1 , and further in view of Saito ( US 20150187497 ) . Regarding claim 5, modified Miyazaki does not teach, an inner electrode paste application step. H owever, Saito teaches manufacturing method of a ceramic electronic component in which, the method for manufacturing a ceramic electronic component according to Claim 4, wherein the ceramic chip element assembly production step includes an inner electrode paste application step of coating a main surface of the predetermined ceramic green sheet with an inner electrode paste ( conductive paste for inner electrodes, … is applied to the ceramic green sheets defining inner layers by, for example, screen printing to form the inner electrodes 12 and 13 having predetermined pattern , para. [0040]). Therefore, in view of the teachings of Saito , it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to include an electrode paste application step as Saito taught in para. [0040] , so that it enables to controlling the thickness of the ceramic electronic component by stacking a predetermined number of ceramic green sheets d efining the inner electrodes and outer layers as Saito disclosed in para. [0040-0041] . Regarding claim 6 , modified Miyazaki does not teach , outer electrode paste application step of coating an outer surface of the unfired ceramic chip element assembly . However Saito further teaches, t he method for manufacturing a ceramic electronic component according to Claim 1, wherein an outer electrode paste application step of coating an outer surface of the unfired ceramic chip element assembly with an outer electrode paste is included before the ceramic chip element assembly working step (conductive paste mainly containing Cu is applied to both end surfaces of each of the ceramic bodies 10 and baked at about 940 0 C to form the outer electrodes 20 and 22 , para. [0045] ). From the teachings of Saito para. [0043-0045], the green ceramic bodies 10 are f iring at a temperature preferably in the range of about 900 0 C and about 1300 0 C and the conductive paste is baked at about 940 0 C to form the outer electrodes 20 and 22 , one of ordinary skill in the art would have known that , unless otherwise defined, firing or sintering the unfired ceramic chip at 940 0 C after applying the outer electrode paste would improve the process step by reducing a baking step. Therefore, in view of the teachings of Saito , it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to sinter the unfired ceramic chip element after applying the outer electrode paste so that it enables eliminating additional baking step . Regarding claim 8 , Saito further teaches, the method for manufacturing a ceramic electronic component according to Claim 6, wherein a plating step of forming at least one plating electrode layer ( Ni--Sn plating layers are formed, para. [0045] ) on an outer surface of the outer electrode formed on the outer surface of the ceramic chip element assembly is included. Therefore, in view of the teachings of Saito , it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and include a plating step as taught by Saito so that it enables forming the outer electrodes having a desired conductivity . Regarding claim 9 , Saito further teaches, the method for manufacturing a ceramic electronic component according to Claim 7, wherein a plating step of forming at least one plating electrode layer (Ni--Sn plating layers are formed, para. [0045] ) on an outer surface of the outer electrode formed on the outer surface of the ceramic chip element assembly is included. Please also refer to the rationale for combination regarding claim 8 , as it is applicable to claim 9 in the same manner. Claim(s) 3 and 1 2 - 13 a re rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Hideki as applied to claim 1, and further in view of Yoshinobu ( JP 2008177188). Regarding claim 3, Miyazaki in view of Hideki taches the recited limitations with respect to claim 1. Miyazaki further teaches, the method for manufacturing a ceramic electronic component according to Claim 1, wherein the ceramic chip element assembly storing step include: storing the plurality of ceramic chip element assemblies placed on the jig into the chip storing portions by vibrating the jig and/or inclining the jig ( a large number of electronic components 1 are supplied from above and, for example, vibration is applied to the feed-in jig 14, para. [0071]). Modified Hideki does not teach, placing the plurality of ceramic chip element assemblies at random positions and in random states on the jig . However, Yoshinobu teaches a method for manufacturing a ceramic electronic component including a ceramic chip element assembly 4 in Fig. 4, a jig preparation step in Fig. 2, in which, placing the plurality of ceramic chip element assemblies at random positions and in random states on the jig ( chip-shaped electronic components coated with electrode paste are randomly stacked in bulk in a jig made of a mesh of stainless steel wire , para. [0003]). Therefore, in view of the teachings of Yoshinobu , it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to include a step of placing the ceramic chip element assemblies at random positions as Yoshinobu taught in para. [0004] so that it enables preventing the ceramic chip pieces stacked each other. Regarding claim 12, modified Miyazaki does not teach, the recited limitations. However, Yoshinobu further teaches, the method for manufacturing a ceramic electronic component according to Claim 11, wherein the jig has a longitudinal direction, a lateral direction orthogonal to the longitudinal direction, and a height direction orthogonal to the longitudinal direction and the lateral direction (see annotated Fig. 2 below) ; the plurality of linear bodies (meridian 11 and 21, latitudes 12 and 22 see annotated Fig. 2) belong to any one of a plurality of linear body groups (meridian 11 and 21 or latitudes 12 and 22) ; the plurality of linear body groups are stacked in the height direction ( height of the chip insertion hole 14 is determined primarily by the diameter of the meridians 11 and latitudes 12 , see Fig. 5, para. [0025]) ; the plurality of linear bodies belonging to a linear body group are arranged parallel or substantially parallel to and separately from each other (see meridian 11 and 21 or latitude 12 and 22 in Figs. 2 and 4) ; and the linear body belonging to a linear body group stacked as a layer mutually intersects with the linear body belonging to another linear body group stacked as another adjacent layer when viewed in the height direction (see meridian 11 and latitude 12; or meridian 21 and latitude 22 in Fig. 2) . 3089681 3548380 linear bodies 0 linear bodies 2421001 3187725 0 0 4062095 2048510 linear bodies 0 linear bodies 3843020 1551305 0 0 3865729 2194459 0 0 Annotated Fig. 2, Yoshinobu. Therefore, in view of the teachings of Yoshinobu , it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to include a mesh ed jig as Yoshinobu taught in Fig s. 2 to 5 having metal meridians and metal latitudes are woven, and joined to one surface of the support member, so that it enables preventing the chip electronic components to contact each other while baking the electrode paste . Regarding claim 13, Miyazaki in view of Hideki and Yoshinobu teaches the recited limitations with respect to claim 12. Yoshinobu further teaches, the method for manufacturing a ceramic electronic component according to Claim 12, wherein, in the jig: the bottom portion includes at least one linear body belonging to a linear body group (meridian 21 or latitude 22, see annotated Fig. 2 above ); the side wall portion includes a linear body belonging to a linear body group (meridian 11 or latitude 12) or at least two linear bodies belonging to at least two linear body groups, respectively; the bottom portion includes a bottom portion through hole (see annotated Fig. 2 below ) in communication with a back surface of the bottom portion (see Figs. 2 and 3); the side wall portion includes a side wall portion through hole (see annotated Fig. 3) in communication with another adjacent chip storing portion; the bottom portion through hole includes a gap (see the gap between two meridians 21 or latitudes 22, Fig. 3) between two linear bodies adjacent to each other in the linear body group of the bottom portion; and the side wall portion through hole includes a gap (see the chip insertion hole 14 between two latitudes 12, Fig. 3 below ) between linear bodies of the side wall portion. Please also refer to the rationale for combination regarding claim 12 , as it is applicable to claim 13 in the same manner. 4388714 2522093 bottom portion through hole 0 0 bottom portion through hole 3413303 2348179 0 0 4461942 2055038 bottom portion 0 bottom portion 4032148 1706982 0 4530802 1283640 side wall portion through hole 0 0 side wall portion through hole 3749803 1115746 0 0 Annotated Fig s . 2 and 3 , Yoshinobu. Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Hideki as applied to claim 1 1 , and further in view of Kuromura (WO 2016117207). Regarding claim 14, modified Miyazaki does not teach arrangement pitch. However, Kuromura teaches a meshed jig for firing ceramic electronic parts including a linear body group, in which, t he method for manufacturing a ceramic electronic component according to Claim 11, wherein in at least one linear body group, arrangement pitches, each of which is a distance between separately arranged two adjacent linear bodies, partly differ from each other (width W2 may change along the direction in which the second linear portion 20 extends. The width W2 may be the same as or different from the width W1 of the first linear portion 10, para. 2, Page 3) . Therefore, in view of the teachings of Kuromura , it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to replace the jig 14 with wire mesh jig as taught by Kuromura , so that it enables controlling the firing and cooling time while manufacturing a ceramic electronic component . Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in order to arrange the pitches or arranging distance between two adjacent linear bodies . Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success. Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki in view of Hideki as applied to claim 1, and further in view of Obana (US 20020017240) . Regarding claim 20, modified Miyazaki does not teach , the recited limitations. However, Obana teaches a method of manufacturing a ceramic electronic component including a jig 2a in Fig. 5A and randomly aligning the ceramic electronic components in which, t he method for manufacturing a ceramic electronic component according to claim 1, wherein the ceramic electronic component is a multilayer ceramic inductor (c omponent chip P means an electronic component … , such as a chip capacitor, a chip inductor or a chip resistor , para. [0105]) , a multilayer ceramic thermistor, a multilayer ceramic LC component, a multilayer ceramic substrate, a ceramic resonator, a ceramic filter, a ceramic resistor, a ceramic thermistor, or a ceramic substrate. Therefore, in view of the teachings of Obana , it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing the ceramic electronic component of Miyazaki and to replace the ceramic electronic component of Miyazaki with a chip inductor or a chip resistor as Obana taught in para. [0105] , so that it enables forming electronic component s such as chip inductor or chip resistor having external electrodes to connect with a printed circuit board . Allowable Subject Matter Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for indicating allowable subject matter: Claim 1 8 would be allowable for disclosing a method for manufacturing a ceramic electronic component, wherein Formula (1) is satisfied, where a diameter of an inscribed circle of the side wall portion of the chip storing portion when viewed from above is denoted by P, and a depth of the chip storing portion is denoted by Q: (P/2) < Q < ( 3 √2/2 ) P (1). Though, prior art of record Miyazaki and Hideki teach a jig an open-top side wall portion, Miyazaki or Hideki does not teach a diameter of an inscribed circle of the side wall portion of the chip storing portion when viewed from above is denoted by P, and a depth of the chip storing portion is denoted by Q: (P/2) < Q < (3 √2/2 ) P (1). P rior art of record Yoshinobu or Kuromura does not teach a diameter of an inscribed circle of the side wall portion of the chip storing portion when viewed from above is denoted by P, and a depth of the chip storing portion is denoted by Q: (P/2) < Q < (3 √2/2 ) P (1). Therefore, claim 18 would be allowable. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Prior art Goto ( US 20160212895 ) teaches a method for manufacturing a ceramic electronic component including a jig preparation step of preparing a jig , a ceramic chip element assembly storing step , a ceramic chip element assembly working step , and ceramic chip element assembly removal step . Prior art Chance ( US 4430690 ) teaches a method for manufacturing a ceramic electronic component including a ceramic chip element assembly production step , a jig preparation step of preparing a jig, a ceramic chip element assembly storing step, a ceramic chip element assembly working step, and ceramic chip element assembly removal step. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JOSE K. ABRAHAM whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1087 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 8:30-4:30 EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT THOMAS J. HONG can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-0993 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSE K ABRAHAM/ Examiner, Art Unit 3729