DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiraga et al. (US2016/0188992) in view of Noyama et al. (JPH09259252).
To claim 1, Hiraga teach an image synthesis device comprising:
processing circuitry to acquire a plurality of images captured from different viewpoints and to select images adjoining each other from the plurality of images (paragraphs 0075, 0099);
to calculate an overlap region as a region where the adjoining images overlap with each other (paragraph 0136);
to determine a boundary line between images in the overlap region (paragraph 0170); and
to execute blending of images in the overlap region (paragraphs 0170-0173),
wherein in response to at least one of the adjoining images including a priority region (e.g., priority for blending), the processing circuitry determines the boundary line that does not overlap with a blend region in a vicinity of the priority region as a region determined depending on a blending method used (obviously interpreted since taught disclosure is a blending process) for blending of an image of the priority region, and the processing circuitry executes the blending of the images in the overlap region based on the boundary line (paragraphs 0157-0166, boundary restraint area),
wherein in response to a region division process of dividing an overlap region of the plurality of images at the boundary line being executed successively for different overlap regions, processing circuitry executes the region division regarding an image that is more desired to exist as an image among the plurality of images as a layer over other images after the region division regarding other images among the plurality of images (Fig. 8; paragraphs 0104, 0113, 0196, sequentially composited).
But, Hiraga do not expressly disclose processing circuitry set an order of the region division such that the processing circuitry executes the region division regarding an image that is more desired to exist as an image among the plurality of images as a layer over other images.
Noyama teach combining images captured from different viewpoints (abstract, Figs. 4-6; paragraphs 0034-0035), wherein division of regions is processed on each image (paragraph 0031), and sets an order of the region division (paragraphs 0030-0031) regarding an image that is more desired to exist as an image among the plurality of images as a layer over other images (paragraphs 0057, 0062, 0073).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Noyama into the apparatus of Hiraga, in order to set an order of superimposing images.
To claim 8, Hiraga and Noyama teach an image synthesis method executed by an image synthesis device (as explained in response to claim 1 above).
To claim 9, Hiraga and Noyama teach a non-transitory computer readable medium with instructions thereon that when executed by a computer causes the computer to execute a process (as explained in response to claim 1 above).
To claim 2, Hiraga and Noyama teach claim 1.
Hiraga teach wherein the processing circuitry generates a weight map of pixel values in the overlap region based on the blend region, and determines the boundary line based on the weight map (paragraphs 0171-0173).
To claim 3, Hiraga and Noyama teach claim 2.
Hiraga teach wherein the weight map has a weight at a predetermined large numerical value in the blend region, and the weight decreases with an increase in distance from the blend region (paragraph 0173).
To claim 5, Hiraga and Noyama teach claim 2.
Though Hiraga do not expressly disclose wherein the weight map has a weight of 0 in the blend region, and the weight increases with an increase in distance from the blend region, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize as possible scenario characterizing blending region for implementation by design preference, hence Official Notice is taken.
To claim 6, Hiraga and Noyama teach claim 1.
Hiraga teach wherein when the plurality of images acquired by the processing circuitry include two or more images each including a priority region, the overlap region calculation unit, the processing circuitry executes an integration process of transforming the images each including the priority region into an integrated image and generates a synthetic image from the integrated image and images not undergone the integration process among the plurality of images acquired by the processing circuitry (paragraphs 0087-0129, transformation can be omitted when relevant distance is close).
To claim 7, Hiraga and Noyama teach claim 1.
Hiraga teach wherein when priority regions in two or more images each including the priority region overlap with each other, the processing circuitry combines two of the priority regions together into one integrated priority region (paragraphs 0171-0173).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiraga et al. (US2016/0188992) in view of Noyama et al. (JPH09259252) and Jacobs (US2021/0026508).
To claim 4, Hiraga and Noyama teach claim 1.
But, Hiraga and Noyama do not expressly disclose wherein when the image of the priority region is a semitransparent image and the processing circuitry employs a blending, an α value at a boundary of the priority region is set at a value smaller than 100%.
Jacobs teach when the image of the priority region is a semitransparent image and the processing circuitry employs a blending, an α value at a boundary of the priority region is set at a value smaller than 100% (paragraphs 0306, 0340), which would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate into the apparatus of Hiraga and Noyama, in order to further blending implementation by design preference.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIYU LU whose telephone number is (571)272-2837. The examiner can normally be reached Weekdays: 8:30AM - 5:00PM.
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ZHIYU . LU
Primary Examiner
Art Unit 2669
/ZHIYU LU/Primary Examiner, Art Unit 2665 November 19, 2025
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