DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
[0053, 0074, 0080, 0086, 0096, 00120, 00130, 00136, 00139, 00157, 00275, 00286, 00291, 00295]: Replace “not all zeroes or all ones” to “not all zeroes and not all ones” to be consistent with the disclosure.
[0074, 0080, 0086, 0096]: In the (e.g., …) segments, replace “or” with “and not” to be consistent with the changes above and with the disclosure.
[0076]: The paragraph indicates, with respect to Figure 4, that an exponent of -2 will shift out bit E. However, Figure 4 shows that an exponent of -2 only shifts out a 0, not bit E. Applicant is advised to address this inconsistency.
[0081]: The word “ft” seems to be a typo and should be corrected to read as “shift”.
[0087]: The word “ft” seems to be a typo and should be corrected to read as “shift”.
[0095]: Replace all instances of “zeros” with “zeroes” for consistency.
[0098]: The phrase “may means” is grammatically incorrect and should be corrected to read as “may mean”.
[00142]: Replace all instances of “zeros” with “zeroes” for consistency.
[00158]: Replace all instances of “zeros” with “zeroes” for consistency.
[00186]: Insert “computing” after second instance of “(throughput)”.
[00196]: “a register maps” is grammatically incorrect.
[00231]: “a SSE” is grammatically incorrect and should be changed to read as “an SSE”.
[00275]: The example embodiments include language used in the claims. For similar reasoning set forth in the objections/rejections below, these paragraphs should be updated as the claims are updated, particularly where incorrect or unclear.
Appropriate correction is required.
Drawings
The drawings are objected for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawings are pixelated because Applicant did not use black (RGB = 000), despite the drawings appearing black to the naked eye. The dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may try the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the process has only been tested in Adobe Acrobat Pro DC);
2. Click "File" and then click "Print";
3. Select "Adobe PDF" as the printer. If not available, "Microsoft Print to PDF" may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck "Print in grayscale (black and white)";
5. Uncheck "Save ink/toner";
6. Click "Advanced";
7. Under "Color Management", for the "Color Profile" field, select "Black & White" near the bottom of the list. The examiner also had "Treat grays as K-only grays" checked, and "Preserve Black" checked.
8. Click "OK" and then click "Print". The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
The drawings are further objected for failing to comply with 37 CFR 1.84(t), which requires the drawing sheet numbering to be clear and larger than the numbers used as reference characters to avoid confusion.
The drawings are objected to because of the following informalities:
Fig. 1: “EXPLICIT SIGNAFICAND BITS” contains a typo and should be corrected to read as “EXPLICIT SIGNIFICAND BITS”.
Fig. 2: Change “N-BIT FIRST EXPONENT VALUE IS NOT ALL ZEROS OR ALL ONES 216” to “N-BIT FIRST EXPONENT VALUE IS NOT ALL ZEROES AND NOT ALL ONES 216” to be consistent with the disclosure.
Fig. 2: Replace “ZEROS” in 218 to “ZEROES” to be consistent with the disclosure.
Fig. 4: On the table located at the bottom left of the figure, Applicant should extend the table so that the -11 exponent is aligned with the other exponents in the table for consistency.
Fig. 12: insert “at least one” before second instance of “source” on line 2 of 1243.
Fig. 12: In 1246, replace “NOT ALL ZEROES OR ALL ONES” to “NOT ALL ZEROES AND NOT ALL ONES” to be consistent with the disclosure.
Fig. 13: insert “at least one” before second instance of “source” on line 2 of 1349.
Fig. 13: In 1353, replace “NOT ALL ZEROES OR ALL ONES” to “NOT ALL ZEROES AND NOT ALL ONES” to be consistent with the disclosure.
Examiner makes the following recommendations to the drawings:
Figs. 12 and 13: Insert articles (a, an, the, etc.) prior to each noun to improve readability of the drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1, lines 8-9: Applicant should change the phrase “not all zeroes or all ones” to “not all zeroes and not all ones”, since this seems to be what Applicant intended based on, at least, figure 4, figure 8, and paragraph [0053].
Claim 1, lines 13-14: Change “said at least the source floating-point operand” to “at least said floating-point operand” to clarity/readability.
Claim 7, line 1 and 13: Delete “one of” and replace “and” at the end of line 13 with “or” to improve clarity/readability.
Claim 9, line 1 and 13: Delete “one of” and replace “and” at the end of line 13 with “or” to improve clarity/readability.
Claim 12, lines 7-8: Applicant should change the phrase “not all zeroes or all ones” to “not all zeroes and not all ones”, since this seems to be what Applicant intended based on, at least, figure 4, figure 8, and paragraph [0053].
Claim 12, lines 12-13: Change “said at least the source floating-point operand” to “at least said floating-point operand” to improve clarity/readability.
Claim 17, lines 9-10: Applicant should change the phrase “not all zeroes or all ones” to “not all zeroes and not all ones”, since this seems to be what Applicant intended based on, at least, figure 4, figure 8, and paragraph [0053].
Claim 17, lines 14-15: Change “said at least the source floating-point operand” to “at least said floating-point operand” to improve clarity/readability.
Claims 2-11, 13-16, and 18-20 are objected to for inheriting the objection of the claims in which they depend on.
Examiner makes the following recommendation(s):
Claim 17: Replace “an instruction” with “a single instruction” and replace all instances of “the instruction” with “the single instruction”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of MPEP 2111.04(II):
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.
The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.
Claim 12 recites the contingent limitation “interpreting the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes [and not] all ones” in lines 7-8. The limitation suggests, under BRI, that if the N-bit first exponent value is all zeroes or all ones, this particular “interpret” step does not occur. The claim also recites the contingent limitation “interpreting the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N- bit first exponent value is either all zeroes or all ones” in lines 9-11. The limitation suggests, under BRI, that if the N-bit first exponent is not either all zeroes or all ones, this particular “interpret” step does not occur. Only one “interpret” step can be true at a time as there is no exponent value that can satisfy both contingent limitations at the same time.
Claim 13 is contingent on the limitation “when the N- bit first exponent value is either all zeroes or all ones” is satisfied with the N-bit exponent value being all zeroes or all ones.
Claims 14 and 15 are contingent on the limitation “when the N- bit first exponent value is either all zeroes or all ones” is satisfied with the N-bit exponent value being all zeroes.
Claim 16 is contingent on the limitation “when the N- bit first exponent value is either all zeroes or all ones” is satisfied with the N-bit exponent value being all ones.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11 and 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the floating-point data" in line 2. There is insufficient antecedent basis for this limitation in the claim. There was no prior recitation of “floating-point data” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this limitation to be “the floating-point data element”.
Claim 11 recites the limitation "the value" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to “a value” in claim 11, line 1, “N-bit first exponent value” in claim 1, lines 4-5, or “a second exponent value” in claim 1, line 10. For the sake of examination, Examiner will interpret this limitation to be referring to ”a value” in claim 11, lines 2-3.
Claim 14 recites the limitation "the execution circuitry" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. There was no prior recitation of “execution circuitry” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this claim to read as “[t]he method of claim 12, wherein, when the N-bit first exponent value is all zeroes, using the second exponent value to identify a position of a binary point relative to the less than M-bit significand.”
Claim 15 is rejected for inheriting the rejection of claim 14.
Claim 15 recites the limitation "the execution circuitry" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. There was no prior recitation of “execution circuitry” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this claim to read as “[t]he method of claim 14, wherein, when the second exponent has a given value, setting a sticky bit equal to an implicit most significant significand bit for the floating-point data element.”
Claim 16 recites the limitation "the execution circuitry" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. There was no prior recitation of “execution circuitry” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this claim to read as “[t]he method of claim 12, wherein, when the N-bit first exponent value is all ones, combining the second exponent value with the N-bit first exponent value.”
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1, 12, and 17 are an apparatus claim, a method claim, and a system claim, respectively. Therefore, the claims are directed to a process, machine, manufacture, or composition of matter.
Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), claim 1 recites “the source floating-point operand to have at least a floating-point data element, the floating-point data element to have a sign bit, an N-bit first exponent value, and M bits”, “interpret the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes or all ones”, “interpret the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N-bit first exponent value is either all zeroes or all ones”, and “perform an operation… on said at least the source floating-point operand to generate a result floating-point operand” Such limitations cover mathematical concepts such as mathematical relationships, mathematical formulas/equations, or mathematical calculations and/or mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). Regarding the “perform” step, the operation may be conversion, arithmetic, logical, or other types of operations which require the use of floating-point data to generate a result (see [0063]), in which these operations fall under mathematical concepts and/or mental processes. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The elements “decoder circuitry to decode an instruction, the instruction to indicate at least a source floating-point operand and a destination register” and “execution circuitry coupled with the decoder circuitry, the execution circuitry to perform operations corresponding to the instruction” are recited at a high level of generality, i.e., generic computer elements, which amount to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)) and does not integrate the judicial exception into a practical application (See MPEP 2106.04(d)(I)). The element “store the result floating-point operand in the destination register” is considered to be an insignificant step of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory)), which does not integrate the judicial exception into a practical application (See MPEP 2106.04(d)(I)). Thus, the elements fail to integrate the judicial exception into a practical application.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously, with respect to Step 2A Prong Two, the elements “decoder circuitry to decode an instruction, the instruction to indicate at least a source floating-point operand and a destination register” and “execution circuitry coupled with the decoder circuitry, the execution circuitry to perform operations corresponding to the instruction” amount to no more than mere instructions to apply the exception (MPEP 2106.05(f)). The element “store the result floating-point operand in the destination register” is considered to be an insignificant step of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory), and is deemed to be considered well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). Accordingly, this claim is not patent-eligible under 35 U.S.C. 101.
Regarding claim 2, the claim recites “the second exponent value comprises a plurality of least significant bits of the M bits, and wherein the less than M-bit significand comprises a plurality of bits more significant than the plurality of least significant bits”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 3, the claim recites “the second exponent value, and the less than M-bit significand, together include M bits”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 4, the claim recites “when the N-bit first exponent value is all zeroes… use the second exponent value to identify a position of a binary point relative to the less than M-bit significand”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 5, the claim recites “the second exponent value has enough bits to be able to encode any one of at least M different values”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 6, the claim recites “when the second exponent value has a given value… set a sticky bit equal to an implicit most significant significand bit for the floating-point data element”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 7, the claim recites “the floating-point data element is a 64-bit floating-point data element, the N-bit first exponent value is an 11-bit value, the M-bit significand is a 52-bit significand, the second exponent value includes from two to six of the M bits, and the less than M-bit significand includes from forty-six to fifty of the M bits”, “the floating-point data element is a 32-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 23-bit significand, the second exponent value includes from two to five of the M bits, and the less than M-bit significand includes from eighteen to twenty-one of the M bits”, “the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes from two to four of the M bits, and the less than M-bit significand includes from six to eight of the M bits”, and “the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 7-bit significand, the second exponent value includes from two to four of the M bits, and the less than M-bit significand includes from three to five of the M bits”. The limitations further cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 8, the claim recites “when the N-bit first exponent value is all ones… combine the second exponent value with the N-bit first exponent value”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 9, the claim recites “the floating-point data element is a 64-bit floating-point data element, the N-bit first exponent value is an 11-bit value, the M-bit significand is a 52-bit significand, the second exponent value includes from three to eleven of the M bits, and the less than M-bit significant includes from forty-one to forty-nine of the M bits”, “the floating-point data element is a 32-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 23-bit significand, the second exponent value includes from three to eight of the M bits, and the less than M-bit significant includes from fifteen to twenty of the M bits”, “the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes from two to five of the M bits, and the less than M-bit significant includes from five to eight of the M bits”, and “the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is an 8-bit value, the M-bit significand is a 7-bit significand, the second exponent value includes from two to six of the M bits, and the less than M-bit significant includes from one to five of the M bits”. The limitations further cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 10, the claim recites “when the N-bit first exponent value is all ones… not to interpret the floating-point data as a Not a Number (NaN) or as infinity”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 11, the claim recites “use a value to determine a number of bits of the second exponent value”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim also recites “read the value from a register”, which is considered to be an insignificant step of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory), which does not integrate the judicial exception into a practical application (See MPEP 2106.04(d)(I)) and is deemed to be considered well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim also recites “obtain the value from either a prefix or an immediate of the instruction”, which is recited at a high level of generality, i.e., generic computer elements, which amount to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)) and does not integrate the judicial exception into a practical application (See MPEP 2106.04(d)(I)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claims 12-16, the claims recite a method similar to the apparatus of claims 1, 2, 4, 6, and 8, respectively. Therefore, the claims are rejected on the same premises.
Regarding claim 17, the claim is mostly rejected for the same reasons as claim 1. The claim also recites “instructions”, “processor”, and “dynamic random access memory”, which are elements recited at a high level of generality, i.e., generic computer elements, which amount to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)) and do not integrate the judicial exception into a practical application (See MPEP 2106.04(d)(I)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claims 18-20, the claims recite a system similar to the apparatus of claims 4, 8, and 2, respectively. Therefore, the claims are rejected on the same premises.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over Valentine et al. (US 20220129264 A1) in view of Kim et al. (US 20160085507 A1).
Intel “Intel AVX512-FP16 Architecture Specification” is cited as extrinsic evidence to explain the details of the VADDPH instruction.
Regarding claim 1, Valentine teaches An apparatus (Fig. 6: Processor 600) comprising:
decoder circuitry to decode an instruction (Figs. 6 and 4B, [0124, 0128]: Each core 602A-N, which may correspond to core 490, comprise of a decode unit 440 that may execute instructions fetched from cache unit 434. The instructions may be from the x86 instruction set, which may also support the packed data instruction set extensions. VADDPH is part of the AVX-512 extension (See Intel, page 22)), the instruction to indicate at least a source floating-point operand and a destination register (The VADDPH instruction uses two source operands to perform an FP16 add operation and a destination register (i.e., XMM1) to store the result of the operation (See Intel, page 22)), the source floating-point operand to have at least a floating-point data element (The VADDPH refers to packed data sources comprising of FP16 data elements (See Intel, page 22)); and
execution circuitry coupled with the decoder circuitry (Fig. 4B: Decode unit 440 is coupled to execution engine unit 450. Execution engine unit 450 as the execution circuitry), the execution circuitry to perform operations corresponding to the instruction (Fig. 4B, [0124-0125]: The execution engine 450 receives the instruction and would perform operation(s) based on the instruction), including to:
perform an operation specified by the instruction on said at least the source floating-point operand to generate a result floating-point operand (Fig. 4B, [0124-0125]: The execution engine 450 would execute and perform the VADDPH instruction using the source operands indicated by the instruction, which would generate a result floating-point operand); and
store the result floating-point operand in the destination register (Fig. 4B, [0124-0125]: The generated result would be stored in the destination register, as defined in the VADDPH instruction).
Valentine does not explicitly teach floating-point data elements to have a sign bit, an N-bit first exponent value, and M bits;
interpret the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes or all ones; and
interpret the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N-bit first exponent value is either all zeroes or all ones.
Kim teaches floating-point data elements to each have a sign bit, an N-bit first exponent value, and M bits (Fig. 6, [0050]: Referring to 600, a floating-point data element can have a sign bit 612, bits 615, 618, and exponent bits 621 as the first exponent value, and mantissa 624 as the M bits. For an FP16 data element, the mantissa is ten bits, exponent is five bits, and sign is one bit);
interpret the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes or all ones (Figs. 6 and 8, [0074]: With respect to step S810 and referring to 600, when the MSBs of exponent 621 (615 and 618) are both set to zeroes (i.e., all bits are not ones), the mantissa 624 is to be the M-bit significand of the floating-point data element); and
interpret the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N-bit first exponent value is either all zeroes or all ones (Fig. 6 and 8, [0077]: With respect to step S810 and referring to 609, when the exponent bits 666 (which includes 660 and 663) are all set to ones, the exponent 666 takes the three MSBs of the mantissa 669 and becomes part of the exponent. The taken MSBs of the mantissa as the second exponent value and the mantissa with the three MSBs taken as the less than M-bit significand);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Valentine with the teachings of Kim to have interpreted the 16-bit floating-point elements based on an exponent value of the floating-point elements. One of ordinary skill would recognize that by interpreting the exponent bits to inherit a bit of the mantissa, the floating-point element would be able to expand its number range without adding bits to the floating-point number (Kim, see [0077]).
Regarding claim 2, Valentine, in view of Kim, teaches the apparatus of claim 1, wherein the second exponent value comprises a plurality of most significant bits of the M bits, and wherein the less than M-bit significand comprises a plurality of bits less significant than the plurality of most significant bits (Fig. 6 and [0077]: The MSBs of the mantissa are the most significant bits of the mantissa bits (i.e., the M bits) and the mantissa with its MSBs taken by the exponent (i.e., the less than M-bit significand) is a plurality of bits less significant than the plurality of most significant bits).
Valentine, in view of Kim, does not teach that the wherein the second exponent value comprises a plurality of least significant bits of the M bits, and wherein the less than M-bit significand comprises a plurality of bits more significant than the plurality of least significant bits.
However, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to have modified the teachings of Valentine, in view of Kim, to have the exponent to take the least significant bits of the mantissa instead of the most significant bits of the mantissa. By taking the least significant bits of the mantissa, there would be no need to shift the mantissa over compared to needing to shift the mantissa when taking the most significant bits of the mantissa. Additionally, rearrangement of parts, i.e., rearranging where the second exponent value is located, is considered to be a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(C)).
Regarding claim 3, Valentine, as modified and in view of Kim, teaches the apparatus of claim 2, wherein the second exponent value, and the less than M-bit significand, together include M bits (Kim, Fig. 6: In the current combination, the three MSBs of the mantissa and what’s left of the mantissa (i.e., the less than M-bit significand) makes up the original size of the mantissa).
Regarding claim 4, Valentine, in view of Kim, teaches the apparatus of claim 1, wherein the execution circuitry is to use the second exponent value to identify a position of a binary point relative to the less than M-bit significand (Fig. 6 and [0050, 0077]: The three MSBs of the mantissa (i.e., the second exponent value) indicates that the floating-point data element is less than 2^(N+3)-1 (where N is the original exponent value, which may be 5-bits for an FP16 data element), which is a position of a binary point relative to the mantissa without its three MSBs (i.e., the less than M-bit significand)).
Valentine, in view of Kim, does not teach that when the N-bit first exponent value is all zeroes, the execution circuitry is to use the second exponent value to identify a position of a binary point relative to the less than M-bit significand.
However, note that Kim teaches an embodiment that when the MSB of the exponent is ‘0’, the MSB of the mantissa is used as a second exponent value (see Fig. 4, [0067]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the teachings of Valentine, in view of Kim, with the teachings of Kim to have it so that when the exponent is all zeroes (including the MSBs of the exponent), the three MSBs of the mantissa becomes the second exponent value (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding claim 7, Valentine, in view of Kim, teaches the apparatus of claim 4, wherein the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes from two to four of the M bits, and the less than M-bit significand includes from six to eight of the M bits (Figs. 6 and 8, [0050, 0074]: In the current combination, with respect to step S810 and referring to 600, and given that the FP data elements are FP16, when the exponent bits 621 (which includes 615 and 618) are all set to ones (i.e., the exponent bits are not all zeroes), the mantissa 624 is to be the 10-bit significand of the floating-point data element and the first exponent value is a 5-bit value. Referring to 609, when the exponent bits are all set to zero, the second value will include 3 bits from the MSBs of the mantissa and the mantissa without its MSBs will be 7 bits).
Regarding claim 8, Valentine, in view of Kim, teaches the apparatus of claim 1, wherein, when the N-bit first exponent value is all ones, the execution circuitry is to combine the second exponent value with the N-bit first exponent value (Fig. 6: When the exponent is all ones (including the two MSBs of the exponent), the exponent bits plus the three MSBs of the mantissa are combined to make up the exponent of the floating-point element).
Regarding claim 9, Valentine, in view of Kim, teaches the apparatus of claim 8, wherein the floating-point data element is a 16-bit floating-point data element, the N-bit first exponent value is a 5-bit value, the M-bit significand is a 10-bit significand, the second exponent value includes from two to five of the M bits, and the less than M-bit significant includes from five to eight of the M bits (Figs. 6 and 8, [0050, 0074]: In the current combination, with respect to step S810 and referring to 600, and given that the FP data elements are FP16, when the exponent bits 621 (which includes 615 and 618) are all set to zeroes (i.e., the exponent bits are not all ones), the mantissa 624 is to be the 10-bit significand of the floating-point data element and the first exponent value is a 5-bit value. Referring to 609, when the exponent bits are all set to ones (which includes 660 and 663), the second value will include 3 bits from the MSBs of the mantissa and the mantissa without its MSBs will be 7 bits).
Regarding claim 10, Valentine, in view of Kim, teaches the apparatus of claim 1, wherein, when the N-bit first exponent value is all ones, the execution circuitry is not to interpret the floating-point data as a Not a Number (NaN) or as infinity (Figs. 6 and 8, [0077]: When the exponent is all ones (including the MSBs of the exponent), the exponent will use the three MSBs of the mantissa and then shift the data around based on this change (Steps S810 and S820). Therefore, the floating-point data will not be interpreted as infinity).
Regarding claim 11, Valentine, in view of Kim, teaches the apparatus of claim 1, wherein the apparatus is to use a value to determine a number of bits of the second exponent value (Kim, Fig. 6 and [0077]: In the current combination, when the MSBs of the exponent (660 and 663) are set, it indicates taking three bits (with respect to 606) from the mantissa. The MSBs of an exponent as the value to determine a number of bits of the second exponent value), and wherein the apparatus is either to read the value from a register or obtain the value from either a prefix or an immediate of the instruction (Kim, Fig. 6: In the current combination, the floating-point data elements are stored in the vector registers indicated by the VADDPH instruction, Therefore, the processor would have to read the MSBs of each exponent of each value to determine the number of bits the exponent will take from the mantissa).
Regarding claim 12, the claims recites a method similar to the apparatus of claim 1. Therefore, the claim is rejected on the same premises.
Regarding claims 13-16, the claims are rejected for the same reasons as claim 12 because, as discussed in the “Claim Interpretation” section, the limitations are contingent and not required.
Regarding claims 13-14 and 16 (which includes the contingent limitations), the claims recite a method similar to the apparatus of claims 2, 4, and 8, respectively. Therefore, the claims are rejected on the same premises.
Regarding claim 17, the claim is mostly rejected for the same reasons as claim 1. Valentine, in view of Kim, also teaches a system to process instructions (Valentine, Fig. 7, [0144]: System 700) comprising:
a processor (Valentine, Figs. 6-7, [0144]: Processor 710 (which may refer to processor 600 in Fig. 6)); and
a dynamic random access memory (DRAM) coupled with the processor (Valentine, Fig. 7 and [0144-0146]: Memory 740 is coupled to processor 710, in which memory may be DRAM).
Regarding claims 18-20, the claims recite a system similar to the apparatus of claims 4, 8, and 2, respectively. Therefore, the claims are rejected on the same premises.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Valentine et al. (US 20220129264 A1) in view of Kim et al. (US 20160085507 A1) and Sapunov (FP64, FP32, FP16, BFLOAT16, TF32, and other members of the ZOO).
Regarding claim 5, Valentine, in view of Kim, teaches the apparatus of claim 4, wherein the second exponent value has enough bits to be able to encode any one of at least eight different values (Fig. 6 and [0050, 0077]: The three MSBs of the mantissa can represent up to 8 types of values (000-111). For an FP16 data element comprising of 7 mantissa bits after having three MSBs of the mantissa be the second exponent value, the second exponent value has enough bits to encode eight different values).
Valentine, in view of Kim, does not teach that the second exponent value has enough bits to be able to encode any one of at least M different values.
Sapunov teaches bfloat16 (a type of FP16 data element) that uses less bits for the mantissa (Pages 7-9, Under “BFLOAT16”: The fraction (i.e., the mantissa) uses 7 bits and the exponent uses 8 bits)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Valentine, in view of Kim, with the teachings of Sapunov to have the FP16 data be bfloat16, which would have resulted in a smaller mantissa and would allow the second exponent value to be able to encode at least M different values. One of ordinary skill may wish to use bfloat16 to represent an even bigger number range compared to standard FP16.
Allowable Subject Matter
Claim 6 is allowed, over the prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 recites, among other things, when the second exponent value has a given value, the execution circuitry is to set a sticky bit equal to an implicit most significant significand bit for the floating-point data element. The closest prior art, Kim et al. (US 20160085507 A1), teaches to change the size of the exponent based on the value of the exponent, and to shift the data if the exponent was extended. Kim does not teach to set a sticky bit equal to an implicit MSB of the significand based on a given value of the second exponent value. Examiner has found no additional prior art that would motivate one or ordinary skill in the art before the effective filing date to modify Valentine, in view of Kim, to set a sticky bit equal to an implicit MSB of the significand based on a given value of the second exponent value.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20100023568 A1: Hickey et al. teaches to extend the exponent range based on an threshold (see Fig. 9).
WO 2020059074 A1: Yasuhiro teaches to use a part of the mantissa as an extended exponent when the first exponent becomes a predetermined value.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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