Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on 10/15/2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Warnes (US Patent Application Publication US 2020/0177087 A1) in view of Kemp et al. (US Patent Application Publication US 2015/0098158 A1, hereinafter “Kemp”).
Regarding claim 1, Warnes discloses (see Fig. 4) an adjustable three output DC voltage supply for providing a positive (131), intermediate (132), and negative voltage supply (133), comprising: a positive DC voltage bus (rail comprising 123, 126) and a negative DC voltage bus (rail comprising 125, 128) that connect to a DC power source (comprising C2); a first voltage divider (comprising R4, U4) connected between the positive DC voltage bus and the negative DC voltage bus, wherein the first voltage divider includes a shunt regulator (U4) that is connected to one of the positive DC voltage bus or the negative DC voltage bus (U4 is connected to rail comprising 125, 128, i.e. negative bus, see [0072] “a fixed negative voltage is produced at nodes 125 and 128 and a fixed positive voltage is produced at nodes 123 and 126.”) and that includes a reference input (312 node of U4), and wherein an output of the first voltage divider (127) provides the intermediate voltage supply (127 provides 132); a second voltage divider (comprising R8, R6) connected between the intermediate voltage supply and the one of the positive DC voltage bus or the negative DC voltage bus (R8, R6 is connected between 132 and rail of 125, 128), wherein an output of the second voltage divider (314) is connected to the reference input of the shunt regulator (314 is connected to 312). Warnes does not disclose a short circuit protection component connected in series to a low voltage side of the shunt regulator to limit the current through the shunt regulator in case of a short circuit to the intermediate voltage supply. However, Kemp teaches (see Fig. 5) a short circuit protection component (510) connected in series to a low voltage side of the shunt regulator (502) to limit the current through the shunt regulator in case of a short circuit to the intermediate voltage supply (506) (see [0028 “Further, the power dissipated across the shunt regulator component 502 is limited by a power limiting resistor 510.”]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes to include a short circuit protection component connected in series to a low voltage side of the shunt regulator to limit the current through the shunt regulator in case of a short circuit to the intermediate voltage supply, as taught by Kemp, because it can help provide protection to the shunt regulator in unwanted overcurrent situations. Regarding claim 2, Warnes discloses (see Fig. 4) wherein the first voltage divider includes a resistor (R4). Regarding claim 3, Warnes discloses (see Fig. 4) wherein the shunt regulator is connected to the positive DC voltage bus via the resistor (U4 is connected to 123, 126, via R4). Regarding claim 4, Warnes discloses (see Fig. 4) wherein the shunt regulator is connected to the negative DC voltage bus via a resistor (U4 is connected to 125, 128 via R6). Regarding claim 5, Warnes does not disclose wherein the short circuit protection component is connected between the shunt regulator and the output of the first voltage divider. However, Kemp teaches (see Fig. 5) wherein the short circuit protection component (510) is connected between the shunt regulator (502) and the output of the first voltage divider (504). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes to include a short circuit protection component wherein the short circuit protection component is connected between the shunt regulator and the output of the first voltage divider, as taught by Kemp, because it can help provide protection to the shunt regulator in unwanted overcurrent situations. Regarding claim 6, Warnes does not disclose wherein the short circuit protection component is connected to the negative DC voltage bus. However, Kemp teaches (see Fig. 5) wherein the short circuit protection component (510) is connected to the negative DC voltage bus (510 is connected to 506 via 502). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes to include a short circuit protection component wherein the short circuit protection component is connected between the shunt regulator and the output of the first voltage divider, as taught by Kemp, because it can help provide protection to the shunt regulator in unwanted overcurrent situations. Regarding claim 7, Warnes does not disclose wherein the shunt regulator is connected between the short circuit protection component and the output of the first voltage divider. However, Kemp teaches (see Fig. 5) wherein the shunt regulator (502) is connected between the short circuit protection component (510) and the output of the first voltage divider (506). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes to include a short circuit protection component wherein the shunt regulator is connected between the short circuit protection component and the output of the first voltage divider, as taught by Kemp, because it can help provide protection to the shunt regulator in unwanted overcurrent situations. Regarding claim 14, Warnes does not disclose wherein the short circuit protection component includes a short circuit protection resistor. However, Kemp teaches (see Fig. 5) wherein the short circuit protection component (510) includes a short circuit protection resistor (see resistor of 510). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes to include a short circuit protection component wherein the short circuit protection component includes a short circuit protection resistor, as taught by Kemp, because it can help provide protection to the shunt regulator in unwanted overcurrent situations. Regarding claim 15, Warnes discloses (see Fig. 4 of Warnes) wherein the second voltage divider includes a first setting resistor (R8) and a second setting resistor (R6). Regarding claim 16, Warnes discloses (see Fig. 4 of Warnes) wherein the DC power source is provided by a rectified output (rectified by D2) from a transformer (TX1). Regarding claim 17, Warnes discloses (see Fig. 4 of Warnes) wherein the intermediate voltage supply defines a 0V voltage supply (see [0036] “The converter accepts an input voltage Vin relative to a ground voltage and is configured to provide three fixed voltages, for example +20 V, 0 V and −5 V, at output terminals 131, 132 and 133.”).
Claims 8-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Warnes in view of Kemp, as evidenced by TL431 (“TL431, A, B Series, NCV431A, B Programmable Precision References,” TL341 Datasheet, ON Semiconductor, Oct. 2011). Examiner’s Note: Regarding the use of secondary evidence to establish anticipation, it is noted that the circuit of the Figure 4 of Warnes incorporates the circuit component TL431 (see [0095] “Resistors R4, R8 and R6 define an adjustment circuit whereby the voltage at node 314 is held at a reference voltage provided by the integrated circuit at the Vref pin. In a specific preferred embodiment, the integrated circuit may be a shunt regulator. For example, shunt regulator TL431 may be used to hold output terminal 133 at −5 V. Since shunt regulator TL431 maintains a voltage drop of approximately 2.5 V between nodes 313 and 314, the value of external resistor R6 may be selected to determine the fixed voltages at output terminals 131 and 133. For example, if the resistance of R6 matches that of R8, the voltage drop across R6 will equal that of the voltage drop across R8. As node 314 is held at approximately −2.5 V by U4 the voltage at node 223, and hence at node 133, will be held at −5 V. The remaining voltage will be distributed across R4. For example, if a potential difference of 25 V is applied between intermediate terminals 121 and 122, holding output terminal 133 at −5 V will ensure output terminal 131 is held at +20 V.”). Accordingly, the TL431 datasheet is referenced as to provide the inherent features of the circuit component TL431. Therefore, TL431 is cited as evidence of the inherent, total disclosure of the anticipatory Warnes reference, and will be referred to where necessary in the explanations below. See MPEP 2131.01 and 2163.07(b).
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<Figure of p.2 of TL431>
Regarding claim 8, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the shunt regulator includes a transistor (see Figure of p.2 of TL431, where the Representative Block Diagram of TL431 includes a Bipolar Junction Transistor). Regarding claim 9, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the shunt regulator further includes a comparator (see comparator of Representative Block Diagram of Figure of p.2 of TL431) that operates the transistor when an input voltage (“-” of comparator) to the comparator is higher than the reference input of the shunt regulator (“+” of comparator) (when “-” is higher than “+” the BJT is operated to be off, and when “+” is higher than “-” the BJT is operated to be on). Regarding claim 10, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the transistor includes a Bipolar Junction Transistor (see Figure of p.1 of TL431, where the Representative Block Diagram of TL431 includes a Bipolar Junction Transistor). Regarding claim 11, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the transistor includes an intrinsic diode or a body diode (see Figure of p.2 of TL431, where the Representative Block Diagram of TL431 includes an NPN BJT which includes an intrinsic diode from the PN junction between the base and collector region of the BJT). Regarding claim 13, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the shunt regulator includes an adjustable reference diode (see Figure of p.2 of TL431, where the TL431 Symbol shows an adjustable reference Zener diode).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Warnes in view of Kemp, as evidenced by TL431, and further in view of Tech Web (“Shunt Regulator Circuit Section: Selection of Peripheral Circuit Components,” Tech Web, 03/25/2020, URL: https://techweb.rohm.com/product/power-ic/acdc/8603/).
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<Figure of p. 2 of Tech Web> Regarding claim 12, Warnes, as evidenced by TL431, does not disclose wherein the transistor includes a Field Effect Transistor. However, Tech Web teaches (see Figure of p. 2 of Tech Web) wherein the transistor (see transistor of “Internal shunt regulator section”) includes a Field Effect Transistor (the transistor connected to the comparator is a FET). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes, as evidenced by TL431, wherein the transistor includes a Field Effect Transistor, as taught by Tech Web, because it can help provide an alternative implementation of a shunt regulator having faster switching speed, higher input impedance, better thermal stability, and lower noise compared to a BJT.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838