Prosecution Insights
Last updated: July 17, 2026
Application No. 18/210,793

ADJUSTABLE THREE OUTPUT DC VOLTAGE SUPPLY WITH SHORT CIRCUIT PROTECTION

Non-Final OA §103
Filed
Jun 16, 2023
Priority
Dec 18, 2020 — GB 2020177.8 +1 more
Examiner
LEE, JYE-JUNE
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
387 granted / 456 resolved
+16.9% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
31 currently pending
Career history
483
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
72.6%
+32.6% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 456 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is in response to the RCE filed on 06/15/2026. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/15/2026 has been entered. Claim Objections Claim 1 is objected to because of the following informalities: Regarding claim 1, in line 1-2, “for providing a positive, intermediate, and negative voltage supply” appears that it should read as “for providing a positive voltage supply, an intermediate voltage supply, and a negative voltage supply” to provide proper antecedent basis for the subsequent recitations of “the intermediate voltage supply”; in line 13, “to limit the current through the shunt regulator” appears that it should read as “to limit a current through the shunt regulator”. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-7 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Warnes (US Patent Application Publication US 2020/0177087 A1) in view of Zhou et al. (US Patent Application Publication US 2009/0261894 A1, hereinafter “Zhou”). Regarding claim 1, Warnes discloses (see Fig. 4) an adjustable three output DC voltage supply (an adjustable power supply that provides +20 V, 0 V, and −5 V at output terminals 131, 132, and 133; see [0036] and [0092] of Warnes) for providing a positive, intermediate, and negative voltage supply (+20 V at output terminal 131, 0 V at output terminal 132, and −5 V at output terminal 133), comprising: a positive DC voltage bus (the high-voltage-side intermediate terminal 121) and a negative DC voltage bus (the low-voltage-side intermediate terminal 122) that connect to a DC power source (the rectified output of transformer secondary winding S1, rectified by diode D2 and smoothed by capacitor C2; see [0045]–[0046] of Warnes); a first voltage divider (resistor R4 and reference integrated circuit U4 connected in series across terminals 121 and 122; see [0093]–[0094] of Warnes) connected between the positive DC voltage bus and the negative DC voltage bus, wherein the first voltage divider includes a shunt regulator (the reference integrated circuit U4, a TL431 shunt regulator; see [0095] of Warnes) that is connected between the intermediate voltage supply (node 127 / output terminal 132, held at 0 V, to which the cathode of U4 is coupled) and one of the positive DC voltage bus or the negative DC voltage bus (the negative DC voltage bus, the anode of U4 being coupled to terminal 122 via node 128; see [0094] of Warnes) and that includes a reference input (the Vref pin of U4 at node 314), and wherein an output of the first voltage divider provides the intermediate voltage supply (node 127, between R4 and U4, provides the 0 V intermediate supply at output terminal 132; see [0093] of Warnes); a second voltage divider (resistors R8 and R6 connected in series between node 127 and node 128; see [0094] of Warnes) connected between the intermediate voltage supply and the one of the positive DC voltage bus or the negative DC voltage bus, wherein an output of the second voltage divider is connected to the reference input of the shunt regulator (node 314, the junction of R8 and R6, is connected to the Vref pin of U4; see [0094]–[0095] of Warnes). Warnes does not disclose a short circuit protection component connected in series with the shunt regulator to limit the current through the shunt regulator in case of a short circuit to the intermediate voltage supply; wherein either: if the shunt regulator is connected to the positive DC voltage bus, the short circuit protection component is connected between the shunt regulator and the intermediate voltage supply; or if the shunt regulator is connected to the negative DC voltage bus, the shunt regulator is connected to the negative DC voltage bus via the short circuit protection component. However, Zhou teaches (see Fig. 2) a short circuit protection component (resistor 323) connected in series with a shunt regulator (the voltage-stabilizing element 322, an adjustable shunting voltage regulator of the TLV431 type) to limit a current through the shunt regulator, wherein the shunt regulator is connected to a low-potential-side node (ground) via the short circuit protection component (the anode of the shunt regulator 322 is grounded via resistor 323, and resistor 323 limits the current through the shunt regulator 322). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes to include a short circuit protection component connected in series with the shunt regulator such that the shunt regulator is connected to the negative DC voltage bus via the short circuit protection component, as taught by Zhou, because it limits the current through the shunt regulator (see [0015] of Zhou) and thereby protects the shunt regulator from excessive current, including in the event of a short circuit to the intermediate voltage supply. Regarding claim 2, Warnes discloses (see Fig. 4) wherein the first voltage divider includes a resistor (R4). Regarding claim 3, Warnes discloses (see Fig. 4) wherein the shunt regulator is connected to the positive DC voltage bus via the resistor (U4 is connected to 123, 126, via R4). Regarding claim 4, Warnes does not disclose wherein the shunt regulator is connected to the negative DC voltage bus via a resistor. However, Zhou teaches (see [0015] of Zhou; Fig. 2) wherein a shunt regulator (the voltage-stabilizing element 322) is connected to a low-potential-side node (ground) via a resistor (the anode of element 322 is grounded via resistor 323). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes wherein the shunt regulator is connected to the negative DC voltage bus via a resistor, as taught by Zhou, because it limits the current through the shunt regulator (see [0015] of Zhou). Regarding claim 5, Warnes does not disclose wherein the short circuit protection component is connected between the shunt regulator and the output of the first voltage divider. However, Zhou teaches (see [0015] of Zhou; Fig. 2) a short circuit protection component (resistor 323) connected in series with the anode of a shunt regulator (the voltage-stabilizing element 322) to limit the current through the shunt regulator. Warnes further teaches (see [0072], [0085], and [0094]–[0095] of Warnes) that the adjustable three output DC voltage supply is symmetric about the intermediate voltage supply, producing a fixed positive voltage at output terminal 131 and a fixed negative voltage at output terminal 133, and that the shunt regulator together with its adjustment circuit sets both the first output voltage difference, applied between the positive DC voltage bus and the intermediate voltage supply, and the second output voltage difference, applied between the intermediate voltage supply and the negative DC voltage bus, from the single shared potential difference generated across intermediate terminals 121 and 122, the first and second output voltage differences being complementary portions of that shared potential difference such that adjusting one alters the other. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to connect the shunt regulator between the intermediate voltage supply and the positive DC voltage bus, with the cathode of the shunt regulator facing the positive DC voltage bus and the anode facing the intermediate voltage supply, and to connect the short circuit protection component of Zhou between the anode of the shunt regulator and the intermediate voltage supply, i.e., between the shunt regulator and the output of the first voltage divider, because 1) the first and second output voltage differences are complementary portions of the same shared potential difference (see [0085] of Warnes), referencing the shunt regulator to the positive DC voltage bus to regulate the first output voltage difference is functionally equivalent to referencing it to the negative DC voltage bus to regulate the second output voltage difference, as in the rejection of claim 1 above; 2) the short circuit protection resistor limits the current through the shunt regulator to the same degree in either arrangement, because the shunt regulator conducts current from its cathode to its anode regardless of which bus the cathode is referenced to, and a resistor connected in series in that single conduction path limits that current equally at every point along the path. The anode-side resistor of Zhou therefore performs the identical current-limiting function, and provides the identical protection of the shunt regulator against excessive current (see [0015] of Zhou), whether it is connected between the anode and the negative DC voltage bus (as recited in claim 1) or between the anode and the intermediate voltage supply (as recited in claim 5). Regarding claim 6, Warnes does not disclose wherein the short circuit protection component is connected to the negative DC voltage bus. However, Zhou teaches (see [0015] of Zhou; Fig. 2) wherein a short circuit protection component (resistor 323) is connected to a low-potential-side node (the anode of the shunt regulator 322 is grounded via resistor 323). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes wherein the short circuit protection component is connected to the negative DC voltage bus, as taught by Zhou, because it limits the current through the shunt regulator (see [0015] of Zhou). Regarding claim 7, Warnes does not disclose wherein the shunt regulator is connected between the short circuit protection component and the output of the first voltage divider. However, Zhou teaches (see [0015] of Zhou; Fig. 2) wherein a shunt regulator (the voltage-stabilizing element 322) is connected between a short circuit protection component (resistor 323, connected to the anode of element 322) and a node to which the cathode of the shunt regulator is connected. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes wherein the shunt regulator is connected between the short circuit protection component and the output of the first voltage divider, as taught by Zhou, because it limits the current through the shunt regulator (see [0015] of Zhou). Regarding claim 14, Warnes does not disclose wherein the short circuit protection component includes a short circuit protection resistor. However, Zhou teaches (see [0015] of Zhou; Fig. 2) wherein a short circuit protection component includes a resistor (resistor 323). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes wherein the short circuit protection component includes a short circuit protection resistor, as taught by Zhou, because it limits the current through the shunt regulator (see [0015] of Zhou). Regarding claim 15, Warnes discloses (see Fig. 4) wherein the second voltage divider includes a first setting resistor (R8) and a second setting resistor (R6). Regarding claim 16, Warnes discloses (see Fig. 4) wherein the DC power source is provided by a rectified output (rectified by D2) from a transformer (TX1). Regarding claim 17, Warnes discloses (see Fig. 4) wherein the intermediate voltage supply defines a 0V voltage supply (see [0036] “The converter accepts an input voltage Vin relative to a ground voltage and is configured to provide three fixed voltages, for example +20 V, 0 V and −5 V, at output terminals 131, 132 and 133.”). Claims 8-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Warnes in view of Zhou, as evidenced by TL431 (“TL431, A, B Series, NCV431A, B Programmable Precision References,” TL341 Datasheet, ON Semiconductor, Oct. 2011). Examiner’s Note: Regarding the use of secondary evidence to establish anticipation, it is noted that the circuit of the Figure 4 of Warnes incorporates the circuit component TL431 (see [0095] “Resistors R4, R8 and R6 define an adjustment circuit whereby the voltage at node 314 is held at a reference voltage provided by the integrated circuit at the Vref pin. In a specific preferred embodiment, the integrated circuit may be a shunt regulator. For example, shunt regulator TL431 may be used to hold output terminal 133 at −5 V. Since shunt regulator TL431 maintains a voltage drop of approximately 2.5 V between nodes 313 and 314, the value of external resistor R6 may be selected to determine the fixed voltages at output terminals 131 and 133. For example, if the resistance of R6 matches that of R8, the voltage drop across R6 will equal that of the voltage drop across R8. As node 314 is held at approximately −2.5 V by U4 the voltage at node 223, and hence at node 133, will be held at −5 V. The remaining voltage will be distributed across R4. For example, if a potential difference of 25 V is applied between intermediate terminals 121 and 122, holding output terminal 133 at −5 V will ensure output terminal 131 is held at +20 V.”). Accordingly, the TL431 datasheet is referenced as to provide the inherent features of the circuit component TL431. Therefore, TL431 is cited as evidence of the inherent, total disclosure of the anticipatory Warnes reference, and will be referred to where necessary in the explanations below. See MPEP 2131.01 and 2163.07(b). PNG media_image1.png 446 424 media_image1.png Greyscale <Figure of p.2 of TL431> Regarding claim 8, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the shunt regulator includes a transistor (see Figure of p.2 of TL431, where the Representative Block Diagram of TL431 includes a Bipolar Junction Transistor). Regarding claim 9, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the shunt regulator further includes a comparator (see comparator of Representative Block Diagram of Figure of p.2 of TL431) that operates the transistor when an input voltage (“-” of comparator) to the comparator is higher than the reference input of the shunt regulator (“+” of comparator) (when “-” is higher than “+” the BJT is operated to be off, and when “+” is higher than “-” the BJT is operated to be on). Regarding claim 10, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the transistor includes a Bipolar Junction Transistor (see Figure of p.1 of TL431, where the Representative Block Diagram of TL431 includes a Bipolar Junction Transistor). Regarding claim 11, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the transistor includes an intrinsic diode or a body diode (see Figure of p.2 of TL431, where the Representative Block Diagram of TL431 includes an NPN BJT which includes an intrinsic diode from the PN junction between the base and collector region of the BJT). Regarding claim 13, Warnes, as evidenced by TL431, discloses (see Fig. 4 of Warnes and Figure of p.2 of TL431) wherein the shunt regulator includes an adjustable reference diode (see Figure of p.2 of TL431, where the TL431 Symbol shows an adjustable reference Zener diode). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Warnes in view of Zhou, as evidenced by TL431, and further in view of Tech Web (“Shunt Regulator Circuit Section: Selection of Peripheral Circuit Components,” Tech Web, 03/25/2020, URL: https://techweb.rohm.com/product/power-ic/acdc/8603/). PNG media_image2.png 302 526 media_image2.png Greyscale <Figure of p. 2 of Tech Web> Regarding claim 12, Warnes, as evidenced by TL431, does not disclose wherein the transistor includes a Field Effect Transistor. However, Tech Web teaches (see Figure of p. 2 of Tech Web) wherein the transistor (see transistor of “Internal shunt regulator section”) includes a Field Effect Transistor (the transistor connected to the comparator is a FET). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adjustable three output DC voltage supply of Warnes, as evidenced by TL431, wherein the transistor includes a Field Effect Transistor, as taught by Tech Web, because it can help provide an alternative implementation of a shunt regulator having faster switching speed, higher input impedance, better thermal stability, and lower noise compared to a BJT. Response to Arguments Applicant’s arguments filed 06/15/2026 with respect to the rejection of claims 1-17 under 35 U.S.C. 103 have been fully considered but are not persuasive. Applicant argues that the cited prior art fails to teach or suggest the amended feature whereby, if the shunt regulator is connected to the negative DC voltage bus, the shunt regulator is connected to the negative DC voltage bus via the short circuit protection component—that is, that the short circuit protection component is located on the low voltage side (the anode side) of the shunt regulator. Applicant contends that the series resistor of the cited art is located on the high voltage side (cathode side) of the shunt regulator, and that, although Zhou’s resistor 323 is on the anode side, it limits current only during normal operation and is disclosed in a single-output configuration that provides no motivation to modify Warnes. Examiner respectfully disagrees. As set forth in the rejection above, the present rejection does not rely upon Kemp et al. for the short circuit protection component; the high-voltage-side/low-voltage-side dispute regarding Kemp et al.’s resistor 510 is therefore moot. Zhou expressly teaches a short circuit protection component (resistor 323) connected in series with the anode (low voltage side) of a shunt regulator, the adjustable shunting voltage regulator 322 of the TLV431 type, wherein the anode of the shunt regulator is grounded via resistor 323 and resistor 323 limits the current through the shunt regulator (see [0015] of Zhou; Fig. 2). Zhou therefore teaches the arrangement Applicant contends is absent from the prior art, namely a current-limiting resistor on the low voltage side (anode side) of the shunt regulator. With respect to Applicant’s argument that Zhou’s resistor 323 limits current only during normal operation and not in case of a short circuit, the recitation “to limit the current through the shunt regulator in case of a short circuit to the intermediate voltage supply” is a recitation of intended use. A series resistor that limits the current through the shunt regulator (resistor 323 of Zhou) remains in series with the shunt regulator regardless of the cause of the current and is therefore fully capable of limiting that current in the event of a short circuit. A prior art structure that is capable of performing a recited functional limitation meets the claim. See MPEP 2114. With respect to Applicant’s argument that Zhou discloses a single output and therefore provides no motivation to modify Warnes, the three-output configuration is provided by Warnes, the primary reference, and not by Zhou. Zhou is relied upon only for its teaching of a current-limiting resistor on the anode (low voltage) side of a shunt regulator. Nonobviousness cannot be established by attacking the references individually where the rejection is predicated upon a combination of references. See In re Keller, 642 F.2d 413 (CCPA 1981); In re Merck & Co., 800 F.2d 1091 (Fed. Cir. 1986). The motivation to combine—to limit, and thereby bound, the current through the shunt regulator in order to protect it—is expressly provided by Zhou (see [0015] of Zhou) and is independent of the number of output terminals. Accordingly, Applicant’s arguments are not persuasive. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure: US 2013/0187619 A1 discloses an adjustable shunt regulator circuit having a voltage divider that provides a reference voltage to an input of the shunt regulator and a resistor connected in series between the shunt regulator and a supply voltage. US 2016/0087538 A1 discloses a multipurpose power supply for power switch driver applications having a plurality of output terminals that provide a positive, intermediate, and negative voltage relative to a reference. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JYE-JUNE LEE/Examiner, Art Unit 2838 /JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Jun 16, 2023
Application Filed
Jul 15, 2025
Non-Final Rejection mailed — §103
Oct 15, 2025
Response Filed
Jan 13, 2026
Final Rejection mailed — §103
Apr 13, 2026
Response after Non-Final Action
Jun 15, 2026
Request for Continued Examination
Jun 17, 2026
Response after Non-Final Action
Jun 25, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
88%
With Interview (+3.3%)
2y 3m (~0m remaining)
Median Time to Grant
High
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