Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1, 10-11 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (Pub. No. US2010/0078790) in view of Mathuriya et al. (US Patent No. US11,836,102) and further in view of Harsh et al. (Swap: a server-scale communication-aware chiplet-Based Manycore PIM Accelerator” IEEE Transactions on computer-aided design of integrated circuits and system, vol.41, no. 11, 8 August 2022, pages 4145-4156) and further in view of Steely et al. (Pub. No. US 20190354146)
As per claim 1, Ito discloses a computing package (fig. 7, a stacked LSI system) comprising:
A package substrate (fig.7, a package board 400); and
A one or more computing clusters (one computing cluster made of 100, 200, 300) located on the package substrate (paragraph 72, lines 2-3, an interface LSI is stacked above the substrate, and a combination of a processor LSI and a memory LSI is further stacked thereabove.), the one or more computing clusters comprising:
A plurality of compute-memory stacks (fig. 7, memory, 200a-1, 200a-2, 200b-1, 200b-2), each compute-memory stack comprising a plurality of memory dies (fig. 7, memory 200a-1, 200a-2, 200b-1, 200b-2) stacked with a compute die (fig.7, processor LSI 100a, 100b); and
an input-output die in communication with each of the plurality of compute-memory stacks (fig. 4, interface LSI 300 and paragraph 80, interface LSI 300 includes: a high-speed I/O interface 301 for performing a high speed communication with components outside the stacked package”),
Ito discloses all the limitations as the above but does not explicitly disclose, the input-output die configured to transmit data for the plurality of compute-memory stacks via one or more peripheral component interconnect (PCI) interfaces. However, Mathuriya discloses this, (col.26, lines 30-35, The HBMs may communicate with the memory die 1701 and/or compute die 1702 via memory controller interface 1807/1809 and high-speed (HS) PCI(e) controller interfaces 1808/1810 through the interposer.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Mathuriya with the teaching of Ito to provide a system with a desire to reduce latency and to reduce the power consumption of systems so as to enhance system performance.
Ito in view of Mathyriya discloses all the limitations as the above but do not explicitly show that the plurality of compute-memory stacks each separately located on the package of substrate. However, Harsh discloses this. (Fig.2 & pages 4147, intergrates multiple chiplets fabricated on a silicon interposer, each of chiplet consists of 16 tiles along with peripheral circuits, the tiles are connected through a network-on-chip. the interchiplet communication is confined only between the neighboring chiplets executing two consecutive layers. The numbers of Pes required for mapping a DNN layer depends on the corresponding kernel size, the number of input and output features, along with the bit precision.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Harsh with the teaching of Ito in view of Mathyriya so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
Ito in view of Mathyriya and further in view of Harsh discloses all the limitations as the above but do not explicitly disclose “an input-output die separately located on the package substrate from the plurality of compute-memory stacks and in communication with each of the plurality of compute-memory stacks.” However, Steely discloses this, (paragraph 15, the physical network layer includes a first set of dies, the physical computing layer includes a second set of dies, and the physical memory layer includes a third set of dies, which are all physical objects made from silicon and the I/O layer 148 placed below memory layer 149 as further cited in paragraph 37-38)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Steely with the teaching of Ito in view of Mathyriya and further in view of Harsh so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 11, Ito discloses a method of computing comprising: receiving processing commands at one or more computing clusters (one computing cluster made of 100, 200, 300) located on a package substrate (fig.7, a package board 400);
performing computing operations based on the processing commands (paragraph 108, lines 16-19, The 3D stacked memory interface 202 controls the memory block 201 based on the command and the address), using a plurality of compute-memory stacks (fig. 7, memory, 200a-1, 200a-2, 200b-1, 200b-2), each of the plurality of compute-memory stacks in communication with an input-output die (fig. 4, interface LSI 300 and paragraph 80, interface LSI 300 includes: a high-speed I/O interface 301 for performing a high speed communication with components outside the stacked package”), wherein each compute- memory stack (fig. 7, memory, 200a-1, 200a-2, 200b-1, 200b-2) includes a plurality of memory dies (fig. 7, memory 200a-1, 200a-2, 200b-1, 200b-2) stacked with a compute die(fig.7, processor LSI 100a, 100b); and
Ito discloses all the limitations as the above but does not explicitly disclose transmitting data from the input-output die via one or more peripheral component interconnects (PCI) interfaces. However, Mathuriya discloses this, (col.26, lines 30-35, The HBMs communicate with the memory die 1701 and/or compute die 1702 via memory controller interface 1807/1809 and high-speed (HS) PCI(e) controller interfaces 1808/1810 through the interposer.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Mathuriya with the teaching of Ito to provide a system with a desire to reduce latency and to reduce the power consumption of systems so as to enhance system performance.
Ito in view of Mathyriya discloses all the limitations as the above but do not explicitly show that the plurality of compute-memory stacks each separately located on the package of substrate. However, Harsh discloses this. (Fig.2 & pages 4147, intergrates multiple chiplets fabricated on a silicon interposer, each of chiplet consists of 16 tiles along with peripheral circuits, the tiles are connected through a network-on-chip. the interchiplet communication is confined only between the neighboring chiplets executing two consecutive layers. The numbers of Pes required for mapping a DNN layer depends on the corresponding kernel size, the number of input and output features, along with the bit precision.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Harsh with the teaching of Ito in view of Mathyriya so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
Ito in view of Mathyriya and further in view of Harsh discloses all the limitations as the above but do not explicitly disclose “an input-output die separately located on the package substrate from the plurality of compute-memory stacks and in communication with each of the plurality of compute-memory stacks.” However, Steely discloses this, (paragraph 15, the physical network layer includes a first set of dies, the physical computing layer includes a second set of dies, and the physical memory layer includes a third set of dies, which are all physical objects made from silicon and the I/O layer 148 placed below memory layer 149 as further cited in paragraph 37-38)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Steely with the teaching of Ito in view of Mathyriya and further in view of Harsh so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claims 10 and 19, Ito discloses wherein the input-output die is further configured to communicate with at least one of an external DRAM or external Remote Direct Memory Access (RDMA) for interconnecting with other computing packages. (paragraph 30, lines 3-6, user space mapping enables the CPU 405 to directly read data of offloaded kernals 510 from the GPU 420 into a common buffer within the DRAM buffer 410. Then, the CPU 405 can copy data into the HBM+ stack 120 or redirect HBM logic to relevant addresses.)
As per claim 20, Ito disclose a model processing unit comprising one or more computing packages connected via peripheral component interconnect interfaces, each computing package comprising: (paragraph 11, a first LSI connected to the package board including: an external I/O interface for performing communication via the package board)
a package substrate (fig.7, a package board 400); and
one or more computing clusters (one computing cluster made of 100, 200, 300) located on the package substrate, the one or more computing clusters comprising (paragraph 72, lines 2-3, an interface LSI is stacked above the substrate, and a combination of a processor LSI and a memory LSI is further stacked thereabove.);
a plurality of compute- memory stacks (fig. 7, memory, 200a-1, 200a-2, 200b-1, 200b-2), each compute-memory stack comprising a plurality of memory dies (fig. 7, memory 200a-1, 200a-2, 200b-1, 200b-2) stacked with a compute die(fig.7, processor LSI 100a, 100b); and
an input-output die in communication with each of the plurality of compute memory stacks, (fig. 4, interface LSI 300 and paragraph 80, interface LSI 300 includes: a high-speed I/O interface 301 for performing a high speed communication with components outside the stacked package”);
Ito discloses all the limitations as the above but does not explicitly disclose, the input-output die configured to transmit data for the plurality of compute-memory stacks via one or more peripheral component interconnect (PCI) interfaces. However, Mathuriya discloses this, (col.26, lines 30-35, The HBMs may communicate with the memory die 1701 and/or compute die 1702 via memory controller interface 1807/1809 and high-speed (HS) PCI(e) controller interfaces 1808/1810 through the interposer.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Mathuriya with the teaching of Ito to provide a system with a desire to reduce latency and to reduce the power consumption of systems so as to enhance system performance.
Ito in view of Mathyriya discloses all the limitations as the above but do not explicitly show that the plurality of compute-memory stacks each separately located on the package of substrate. However, Harsh discloses this. (Fig.2 & pages 4147, intergrates multiple chiplets fabricated on a silicon interposer, each of chiplet consists of 16 tiles along with peripheral circuits, the tiles are connected through a network-on-chip. the interchiplet communication is confined only between the neighboring chiplets executing two consecutive layers. The numbers of Pes required for mapping a DNN layer depends on the corresponding kernel size, the number of input and output features, along with the bit precision.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Harsh with the teaching of Ito in view of Mathyriya so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
Ito in view of Mathyriya and further in view of Harsh discloses all the limitations as the above but do not explicitly disclose “an input-output die separately located on the package substrate from the plurality of compute-memory stacks and in communication with each of the plurality of compute-memory stacks.” However, Steely discloses this, (paragraph 15, the physical network layer includes a first set of dies, the physical computing layer includes a second set of dies, and the physical memory layer includes a third set of dies, which are all physical objects made from silicon and the I/O layer 148 placed below memory layer 149 as further cited in paragraph 37-38)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Steely with the teaching of Ito in view of Mathyriya and further in view of Harsh so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
3. Claims 2-6, 8-9 and 12-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (Pub. No. US2010/0078790) in view of Mathuriya et al. (US Patent No. US11,836,102) and further in view of Harsh et al. (Swap: a server-scale communication-aware chiplet-Based Manycore PIM Accelerator” IEEE Transactions on computer-aided design of integrated circuits and system, vol.41, no. 11, 8 August 2022, pages 4145-4156) and further in view of Steely et al. (Pub. No. US 20190354146) and further in view of Malladi et al. (Pub. No. US2019/0050325)
As per claims 2 and 12, Ito in view of Mathuriya and further in view of Harsh and further in view of Sleely disclose all the limitations as the above but does not explicitly disclose wherein each low-power compute die of the plurality of compute-memory stacks is configured to operate on a power supply of about 40W or less. However, Malladi discloses this. (paragraph 22, The HBM+ unit 100 can include multiple HBM+ stacks 120 of HBM2 modules 110 and a corresponding logic die 105 disposed beneath the HBM2 modules 110. The Machine learning algorithms benefit from this architecture, as they require intensive bandwidth for training and prediction and it has to be added that typical laptop processors are limited to power between 15-45W.”)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Malladi with the teaching of Ito in view of Mathuriya and further in view of Harsh and further in view of Sleely so as to leading to lower latency and better memory traffic, thus enhance the system performance.
As per claim 9, Malladi discloses wherein the computing package is configured to operate as a large model processing unit. (paragraph 19, lines 1-6, artificial neural network or machine learning)
As per claims 3 and 13, Malladi discloses wherein for a particular compute-memory stack from the plurality of compute-memory stacks, the low-power compute die has a footprint on the package substrate that is less than 30% larger than a footprint of the plurality of memory dies. (fig.2, footprint of 105 compared to 110)
As per claims 4 and 14, Malladi discloses the computing package further comprising a plurality of computing clusters located on the package substrate, and wherein the input-output die for each computing cluster is connected to one or more input-output dies of the other computing clusters located on the package substrate. (paragraph 23, the two HBM+ stacks 120 and part of 420-415 dealing with them as defining a computing cluster as show in figure 4)
As per claims 5 and 15, Ito discloses wherein the package substrate includes four computing clusters, and wherein each computing cluster contains four or more compute-memory stacks. (paragraph 81, lines 1-3, FIG. 1 is characterized in that at least two or more sets of combinations of processor LSIs 100 and memory LSIs 200 are stacked in a semiconductor package)
As per claims 6 and 16, Ito discloses wherein the package substrate includes two computing clusters, and wherein each computing cluster contains eight or more compute-memory stacks. (paragraph 81, lines 1-3, FIG. 1 is characterized in that at least two or more sets of combinations of processor LSIs 100 and memory LSIs 200 are stacked in a semiconductor package)
As per claims 8 and 18, Malladi discloses wherein the plurality of compute-memory stacks are stacked 3D-dynamic random access memory (DRAM) chiplets. (paragraph 4, stacking Dynamic Random Access Memory (DRAM) dies)
4. Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (Pub. No. US2010/0078790) in view of Mathuriya et al. (US Patent No. US11,836,102) and further in view of Harsh et al. (Swap: a server-scale communication-aware chiplet-Based Manycore PIM Accelerator” IEEE Transactions on computer-aided design of integrated circuits and system, vol.41, no. 11, 8 August 2022, pages 4145-4156) and further in view of Steely et al. (Pub. No. US 20190354146) and further in view of Chen (US Patent No. US9,147,672)
As per claims 7 and 17, Ito in view of Mathuriya discloses all the limitations as the above but does not explicitly disclose wherein each computing cluster contains at least one inactive spare compute-memory stack. However, Chen discloses this. (col.9, lines 59-67, The controller chip 190 can also activate or deactivate a particular chip stack or a particular chip in a chip stack. In addition, the controller chip 190 replaces it or them with the spare stacks (e.g., chip stacks "o" or "p" illustrated in FIG. 12) as further cited in col.10, lines 25-30)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Chen with the teaching of Ito in view of Mathuriya and further in view of Harsh and further in view of Sleely so as to provide the system with the multiple instances of the same chip stack can be configured to provide higher interconnection bandwidth and redundancy, thus enhance the system performance.
Response to Amendment
5. Applicant's amendment filed on 5/28/2026 have been fully considered but are moot in view of the new ground(s) of rejection.
6. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Thomas et al. [Pub. No. US2014/0201405] discloses the processor die and one or more memory or cache dice within a multi-chip package may support a short, length matched I/O interfaces that enables high bandwidth, low power transmission using a high-speed I/O interface.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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