DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 6 objected to because of the following informalities: typo; Claim 6 “wherein the at least one of the at least one processor” should read “wherein at least one of the at least one processor”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 11-12 and 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "wherein the based on execution of an instruction" in line 1. There is insufficient antecedent basis for this limitation in the claim. This is because it is unclear whether this is new instances or old instance(s) (first introduced in parent claim(s)) of “instruction”,
Claim 11 recites the limitation "specifies the number of registers to a thread and an identifier of a condition" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. This is because it is unclear whether these are new instances or old instances (first introduced in parent claim(s)) of “a thread” and “a condition”. Additionally, when claim 12 mentions “for the condition” in line 2, this further inherits and does not remedy the lack of clarity (due to unclear which potential instance of “condition” is being referred to).
Claim 17 recites the limitation "to the thread" in line 2. There is insufficient antecedent basis for this limitation in the claim. This is because it is unclear which instance of “thread is being referred to here, since parent claim 16 recites “a first thread” and “a second thread”, therefore it is not clearly stated which thread, “the thread” is referring to from the two threads.
Note. Most likely these claims depend on some dependent claim or are missing elements.
In order to fix this issue, dependency should be reviewed and any first instance of an element
should be made clear that it’s a first instance and should be referred to as “a” or “an” instead of
“the”, and if multiple instances exist, further instances should be further distinguished for example by saying “first”, “second”, and/or “third” etc.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-13 and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khorasani et al. (U.S. Patent Application Publication No. 2018/0275991), hereinafter referenced as Khorasani.
Regarding claim 1, Khorasani teaches An apparatus comprising: a graphics processing unit (GPU) comprising: (fig. 2 shows computing system/apparatus 200 with GPU 205); at least one processor and multiple registers, wherein: (fig. 2 shows GPU comprising processor 235, and compute units 255A-N and paragraph 29 teaches “compute units 255A-N (of FIG. 2). In one implementation, compute unit 300 includes single-instruction, multiple-data (SIMD) units 315A-N, control logic 320, and register file 330”); register file includes multiple registers as shown in fig. 3; based on execution of an instruction by at least one of the at least one processor to allocate a particular number of registers to a thread, (claim 1 teaches “processor comprising: one or more execution units comprising circuitry configured to execute instructions; a register file comprising a plurality of registers… allocate a first set of registers from the register file for exclusive use by a first thread executing on a first execution unit”); this shows allocating a particular number (first set) of registers to a thread based on execution of instructions by processor; assign the number of registers from the multiple registers to the thread (abstract teaches “processor assigns a base set of registers to each thread of a plurality of threads executing on the processor”); this shows assigning the number of registers (first/base set) from multiple registers to the thread.
Regarding claim 2, Khorasani teaches wherein: if the number of registers is not available in the multiple registers, wait for the number of registers to be available in the multiple registers to assign the number of registers to the thread (Khorasani, claim 7 teaches “make the first thread ineligible for execution when the first thread requires use of the additional number of registers but there are not enough unallocated registers in the pool of registers; and make the first thread eligible for execution again when enough registers become available in the pool of registers”); this shows when there’s not enough unallocated registers (if number of registers not available in the multiple registers), then wait for registers to be available (by making first thread ineligible for execution) until enough registers become available (thus to assign the number of registers to thread).
Regarding claim 3, Khorasani teaches wherein: based on execution of the instruction, release one or more registers assigned to the thread, (fig. 10, step 1060 teaches “insert a release instruction”); this shows release of one or more registers that are assigned to the thread; wait for clearing of at least one condition, (paragraph 22 teaches “When the given thread no longer needs additional registers, the given thread executes a release instruction to release the extended set of registers back into the shared register pool for other threads to use”); this shows clearing (with a wait until “when” the condition becomes false) the condition (of needing additional registers); and allocate the number of registers from the multiple registers to the thread (claim 1 teaches “allocate a first set of registers from the register file for exclusive use by a first thread executing on a first execution unit”); this shows allocating the number (first set) of registers from multiple registers to the thread.
Regarding claim 4, Khorasani teaches wherein the instruction is to specify the particular number of registers to assign to the thread and an identifier of a condition to be met prior to allocation of the particular number of registers (paragraph 24 teaches “When the register usage by the thread exceeds the number of registers in the base register set, the thread executes an acquire instruction to acquire the use of an extended register set”, paragraph 58 teaches “a method 1100 for executing an extended register set acquire instruction is shown. A processor, executing instructions of a given thread, detects an extended register set acquire instruction in the program instructions for the given thread (block 1105)… response to detecting the extended register set acquire instruction, the control logic determines if there is an available extended register set in the shared register pool (SRP) (conditional block 1110)…the control logic searches the SRP bitmask for an unset (i.e., zero) bit to determine if there is an available extended register set in the SRP)” and paragraph 59 teaches “If there is an available extended register set in the shared register pool (conditional block 1110, “yes” leg), then the control logic assigns a given extended register set to the given thread (block 1120).”); register usage by thread exceeding number of the registers in the base register set shows specifying particular number of registers to assign to the thread (alongside aforementioned first set of registers in claim 1 [of this action] above), it is based on identifier of a condition to be met (SRP bitmask for unset bit as identifier to determine condition of if there is an available extended register set), and this is prior to allocation/assignment of extended register set (which is acquired for the aforementioned particular number of registers) since the allocation/assignment depends on that aforementioned condition.
Regarding claim 5, Khorasani teaches wherein the based on execution of an instruction by at least one of the at least one processor to allocate the particular number of registers to the thread, (claim 1 teaches “processor comprising: one or more execution units comprising circuitry configured to execute instructions; a register file comprising a plurality of registers… allocate a first set of registers from the register file for exclusive use by a first thread executing on a first execution unit”); this shows allocating a particular number (first set) of registers to the thread based on execution of instructions by processor; assign the number of registers to the thread comprises waiting for the condition to be met prior to allocation of the particular number of registers from the multiple registers (fig. 11 shows step 1120 of assigning registers to the thread comprises previous steps of 1115 to stall given thread while waiting for extended register set to become available); extended register set becoming available would be the aforementioned condition being met and is checked in step 1110 which is prior to allocation of particular number of registers from the multiple registers.
Regarding claim 6, Khorasani teaches wherein the at least one of the at least one processor is to allocate use of a general register file to the thread based on less than the particular number of registers being available for allocation from the multiple registers (paragraph 30 teaches “Register file 330 includes any number of registers for use by threads executing on SIMD units 315A-N. In one implementation, register file 330 includes a plurality of base register sets 335A-N and a plurality of extended register sets 340A-N. In one implementation, each thread executing on one of SIMD units 315A-N is allocated a given base register set 335A-N for use by the thread. When the thread needs more registers than are available in the given base register set 335A-N, then the thread executes an acquire instruction to gain access to an extended register set 340A-N”); this shows processor allocating use of register file 330 to thread when thread needs more registers than are available in given set (thus is based on less than the particular number of registers being available for allocation from the multiple registers).
Regarding claim 8, the method claim 8 recites similar limitations as apparatus claim 1, and thus is rejected under similar rationale. In addition, Khorasani abstract teaches “the compiler inserts acquire and release instructions into the program code…during compilation”; this shows GPU would perform the instruction of claim 1 based on compiler-specified instruction with compiled code segment.
Regarding claim 9, the method claim 9 recites similar limitations as apparatus claim 2, and thus is rejected under similar rationale.
Regarding claim 10, the method claim 10 recites similar limitations as apparatus claim 3, and thus is rejected under similar rationale.
Regarding claim 11, the method claim 11 recites similar limitations as apparatus claim 4, and thus is rejected under similar rationale.
Regarding claim 12, the method claim 12 recites similar limitations as apparatus claim 5, and thus is rejected under similar rationale.
Regarding claim 13, the method claim 13 recites similar limitations as apparatus claim 6, and thus is rejected under similar rationale.
Regarding claim 15, Khorasani teaches A non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: (paragraph 63 teaches “non-transitory computer readable storage mediums. The storage medium is accessible by a computing system during use to provide the program instructions to the computing system for program execution. Generally speaking, such a computing system includes at least one or more memories and one or more processors configured to execute program instruction”); execute a compiler to compile an instruction set comprising a first code segment and a second code segment, (abstract teaches “the compiler inserts acquire and release instructions into the program code…during compilation” and paragraph 33 teaches “compiler performs register liveness analysis. The values in diagram 410 on the right-side of FIG. 4 illustrate the liveness of each register R0-R3 when the instructions within code blocks 405A-D are executed); this shows executing compiler (due to during compilation) and is to compile instructions within code blocks (first and second code segments); wherein: the compiler is to provide a first instruction associated with the first code segment to specify a first number of registers to allocate to the first code segment (claim 1 teaches “wherein the control logic is configured to: allocate a first set of registers from the register file for exclusive use by a first thread executing on a first execution unit”); first set of registers shows specifying a first number of registers and this is to allocate to the (for use by) first thread, the first thread which is associated with and executes first code segment (since threads, as one of ordinary skill in the art would understand, execute code segments); and the compiler is to provide a second instruction associated with the second code segment to specify a second number of registers to allocate to the second code segment (claim 4 last line teaches “allow a second thread to use the second set of registers”); second set of registers shows specifying a second number of registers and this is to allocate to the (for use by) second thread, the second thread which is associated with and executes second code segment (since threads, as one of ordinary skill in the art would understand, execute code segments).
Regarding claim 16, Khorasani teaches wherein the first instruction is to specify the first number of registers to a first thread associated with the first code segment and an identifier of a condition to be met prior to allocation of the first number of registers to the first thread (claim 1 teaches “wherein the control logic is configured to: allocate a first set of registers from the register file for exclusive use by a first thread executing on a first execution unit”, paragraph 24 teaches “When the register usage by the thread exceeds the number of registers in the base register set, the thread executes an acquire instruction to acquire the use of an extended register set”, paragraph 58 teaches “a method 1100 for executing an extended register set acquire instruction is shown. A processor, executing instructions of a given thread, detects an extended register set acquire instruction in the program instructions for the given thread (block 1105)… response to detecting the extended register set acquire instruction, the control logic determines if there is an available extended register set in the shared register pool (SRP) (conditional block 1110)…the control logic searches the SRP bitmask for an unset (i.e., zero) bit to determine if there is an available extended register set in the SRP)” and paragraph 59 teaches “If there is an available extended register set in the shared register pool (conditional block 1110, “yes” leg), then the control logic assigns a given extended register set to the given thread (block 1120).”); register usage by first thread (of first instruction and as aforementioned in claim 15 of this action above, associated with first code segment) exceeding number of the registers in the base register set shows specifying first number of registers to assign to the thread (alongside aforementioned first set of registers in citation of claim 1 of Khorasani above), it is based on identifier of a condition to be met (SRP bitmask for unset bit as identifier to determine condition of if there is an available extended register set), and this is prior to allocation/assignment of extended register set (which is acquired for the aforementioned first number of registers) since the allocation/assignment depends on that aforementioned condition; and the second instruction is to specify the second number of registers to a second thread associated with the second code segment and an identifier of a condition to be met prior to allocation of the second number of registers to the second thread (claim 4 last line teaches “allow a second thread to use the second set of registers”, paragraph 24 teaches “When the register usage by the thread exceeds the number of registers in the base register set, the thread executes an acquire instruction to acquire the use of an extended register set”, paragraph 58 teaches “a method 1100 for executing an extended register set acquire instruction is shown. A processor, executing instructions of a given thread, detects an extended register set acquire instruction in the program instructions for the given thread (block 1105)… response to detecting the extended register set acquire instruction, the control logic determines if there is an available extended register set in the shared register pool (SRP) (conditional block 1110)…the control logic searches the SRP bitmask for an unset (i.e., zero) bit to determine if there is an available extended register set in the SRP)” and paragraph 59 teaches “If there is an available extended register set in the shared register pool (conditional block 1110, “yes” leg), then the control logic assigns a given extended register set to the given thread (block 1120).”); register usage by second thread (of second instruction and as aforementioned in claim 15 of this action above, associated with second code segment) exceeding number of the registers in the base register set shows specifying second number of registers to assign to the second thread (alongside aforementioned second set of registers in citation of claim 4 of Khorasani above), it is based on identifier of a condition to be met (SRP bitmask for unset bit as identifier to determine condition of if there is an available extended register set), and this is prior to allocation/assignment of extended register set (which is acquired for the aforementioned second number of registers) since the allocation/assignment depends on that aforementioned condition.
Regarding claim 17, Khorasani teaches wherein if the first number of registers is not available, assignment of the first number of registers to the thread is to occur after the first number of registers is available (Khorasani, claim 7 teaches “make the first thread ineligible for execution when the first thread requires use of the additional number of registers but there are not enough unallocated registers in the pool of registers; and make the first thread eligible for execution again when enough registers become available in the pool of registers”); this shows when there’s not enough unallocated registers (if first number of registers not available), then wait for registers to be available (by making first thread ineligible for execution) until enough registers become available (thus assignment of first number of registers to thread occurs after the first number of registers is available).
Regarding claim 18, Khorasani teaches wherein execution of the first instruction by a graphics processor is to cause: release registers assigned to the first thread, (paragraph 4 teaches ““thread” is one of a collection of parallel executions of a kernel. A kernel is also referred to as a “GPU program” herein” and fig. 10, step 1060 teaches “insert a release instruction”); this shows, by GPU, release of one or more registers that are assigned to the thread; wait for clearing of at least one condition, (paragraph 22 teaches “When the given thread no longer needs additional registers, the given thread executes a release instruction to release the extended set of registers back into the shared register pool for other threads to use”); this shows clearing (with a wait until “when” the condition becomes false) the condition (of needing additional registers); and allocate the first number of registers to the first thread (claim 1 teaches “allocate a first set of registers from the register file for exclusive use by a first thread executing on a first execution unit”); this shows allocating the number (first set) of registers from multiple registers to the thread.
Regarding claim 19, Khorasani teaches wherein the release registers assigned to the first thread comprises permit re-allocation of the released registers to another thread (Khorasani, paragraph 22 teaches “When the given thread no longer needs additional registers, the given thread executes a release instruction to release the extended set of registers back into the shared register pool for other threads to use”); released for other threads to use shows this permits re-allocation of released registers to another thread.
Regarding claim 20, Khorasani teaches wherein execution of the first instruction by a graphics processor is to cause: allocate use of a general register file to the first thread based on less than the first number of registers being available for allocation to the first thread (paragraph 4 teaches ““thread” is one of a collection of parallel executions of a kernel. A kernel is also referred to as a “GPU program” herein” and paragraph 30 teaches “Register file 330 includes any number of registers for use by threads executing on SIMD units 315A-N. In one implementation, register file 330 includes a plurality of base register sets 335A-N and a plurality of extended register sets 340A-N. In one implementation, each thread executing on one of SIMD units 315A-N is allocated a given base register set 335A-N for use by the thread. When the thread needs more registers than are available in the given base register set 335A-N, then the thread executes an acquire instruction to gain access to an extended register set 340A-N”); this shows processor allocating use of register file 330 to first thread when thread needs more registers than are available in given set (thus is based on less than the first number of registers being available for allocation to the first thread).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khorasani in view of Berson (U.S. Patent Application Publication No. 2024/0378089), hereinafter referenced as Berson.
Regarding claim 7, Khorasani fails to explicitly teach comprising: a central processing unit (CPU), wherein the CPU is to execute a compiler to compile a code segment with the instruction and wherein the compiled code segment is associated with the thread.
However, Berson teaches comprising: a central processing unit (CPU), wherein the CPU is to execute a compiler (Berson, paragraph 42 teaches “system configured to compile and execute CUDA source code of FIG. 35A using a CPU”); compiling using CPU would require CPU to execute compiler; to compile a code segment with the instruction and wherein the compiled code segment is associated with the thread (Berson paragraph 3 teaches “one or more operations performed by a compiler to, at least in part, analyze potential transformations that compiler may implement in relation to register assignment and allocation” and paragraph 50 teaches “allocate and/or assign a thread to a register.”); this shows compiler to compile code segment (associated with thread) with instruction. Berson is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of having compiler for compiled code segment using specific processors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Khorasani's invention with the compiled code and compiler techniques of Berson to affect performance of a program, such as improving a program's execution speed (Berson, paragraph 53). This would be done by using specific processor(s) for compiling.
Regarding claim 14, the combination of Khorasani and Berson teaches comprising: the GPU accessing the compiler-specified instruction with the compiled code segment from a memory and executing the compiler-specified instruction with the compiled code segment (Berson, paragraph 41 teaches “system configured to compile and execute CUDA source code of FIG. 35A using a CPU and a CUDA-enabled GPU,”, paragraph 236 teaches “graphics processor 20 causes a compiler to assign registers” and paragraph 364 teaches “CUDA source code 3510 to HIP source code 3530 that is then stored in memory.”); this shows GPU executes (must first access) compiler-specified instruction with compiled code segment from memory. The same motivations used in claim 7 apply here in claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Vaidyanathan et al. (U.S. Patent Application Publication No. 2019/0087188) paragraph 166 teaches “while banks 1820 (e.g., 64 registers (64-128)) are implemented as shared registers that are temporarily assigned to a thread on demand. In such an embodiment, banks 1810 are initially assigned to a thread, and banks 1820 are dynamically assigned to a smaller number of threads”; this shows dynamic register allocation to threads.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAUMAN U AHMAD whose telephone number is (703)756-5306. The examiner can normally be reached Monday - Friday 9:00am - 5:00pm.
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/N.U.A./Examiner, Art Unit 2611
/KEE M TUNG/Supervisory Patent Examiner, Art Unit 2611
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