Prosecution Insights
Last updated: April 19, 2026
Application No. 18/211,685

GENERATING A TEST PROGRAM

Non-Final OA §102§103
Filed
Jun 20, 2023
Examiner
NGO, BRIAN
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Teradyne Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
851 granted / 967 resolved
+20.0% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
24 currently pending
Career history
991
Total Applications
across all art units

Statute-Specific Performance

§101
14.2%
-25.8% vs TC avg
§103
36.9%
-3.1% vs TC avg
§102
38.3%
-1.7% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 967 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This Non-Final office is a response to the papers filed on 06/20/2023 . Claims 1-35 are pending. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 -5, 10-14, 16, 18-22, 27-31, 33, and 35 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Han et al. (CN 113128147 A ) . Regarding claims 1 , 18, and 35 , Han discloses: A method comprising: receiving information about tests performed on a device (see page 2, par [6], obtaining the optimal configuration of the design requirement , [wherein design requirement is the information about tests performed ]) , wherein the tests are associated with one or more parameters (see page 3, par [4-6], machine learning of high efficiency integrated circuit design method of a preferred scheme, wherein: further comprising: the single parameter optimal value of each parameter is required to be inverted or arranged in positive sequence ….) ; performing an optimization process that includes varying the one or more parameters to optimize one or more criteria associated with the tests, wherein the optimization process comprises an artificial intelligence process or a machine learning process (see page 3-4, starting the predicted optimal configuration model; the prediction optimal configuration model performs normalization processing for the operation result obtained by different parameters of each parameter, calculating with the optimal value error ratio ….. [wherein value error ration is a criteria]….. , As the present invention based on machine learning of high efficiency integrated circuit design method …., see page 6-7) ; and outputting information that is based on which of the one or more parameters optimizes the one or more criteria (see page 2-3, outputting each operation result, sum of each operation result, obtaining the single target parameter optimal configuration prediction result …., [wherein outputting each operation result is outputting information], see page 7, par 7) . Regarding claims 2 , and 19 , Han discloses: wherein the one or more parameters comprises one or more of: a voltage level of a signal to test the device, a current level of the signal to test the device, a timing of the signal to test the device (see page 6-7, automatic test vector generating time, test time, area and power consumption …., [wherein power consumption is included the voltage and current level]) , a time it takes for the signal to test the device to settle, a pass/fail test result for the device, a sample rate for sampling a pin on the device during testing, or a number of samples sampled on the pin. Regarding claims 3 and 20 , Han discloses: wherein the tests produce results by testing the device using a first test platform that are not wholly correlated to results produced by testing the device using a second test platform, the first test platform being different from the second test platform (see page 9, the invention compared with the traditional test design process, for the circuit, test coverage ratio is higher than other four configuration, automatic test vector generating time; the power consumption is lower than other four configurations …., [wherein the traditional test design process is a second test platform] ) . Regarding claims 4 and 21 , Han discloses: wherein the one or more criteria comprise one or more of: repeatability of test results, a time it takes to test the device, a level of correlation between the tests performed on the first test platform and the tests performed on the second test platform, compliance with requirements, or safety for the device (see page 8. and target parameter (test coverage, test time, area overhead and power consumption) stored in the csv file …., using perl script to replace the value of the configuration parameter, repeating the flow n times …) . Regarding claims 5 and 22, Han discloses: wherein the artificial intelligence process or machine learning process comprises a cost function, the cost function to optimize the one or more criteria based on variations of the one or more parameters (see page 8, the set of the cost function value is the minimum, cost function in order to calculate the error …., the iteration process, each iteration calculating cost function value and output, referring to FIG. 4, it can see the cost function value is reduced …..) . Regarding claims 10 and 27 , Han discloses: wherein the information comprises a report identifying at least one of ( i ) which of the one or more parameters optimizes the one or more criteria, or (ii) how the one or more criteria are optimized (see page 6, setting scanning chain number to be predicted configuration according to requirement, … ., scanning chains of the configured to be predicted set according to the requirement ….) . Regarding claims 11 and 28 , Han discloses: wherein the report identifies one or more of the tests have not been optimized (see page 6, setting scanning chain number to be predicted configuration according to requirement, … ., scanning chains of the configured to be predicted set according to the requirement ….[wherein the requirement is set to identify one or more of the tests have and have not been optimized]). Regarding claims 12 and 29 , Han discloses: wherein the information comprises a test program comprising one or more of the tests that have been optimized (see page 6, setting scanning chain number to be predicted configuration according to requirement, … ., scanning chains of the configured to be predicted set according to the requirement ….[wherein the requirement is set to identify one or more of the tests have and have not been optimized]) . Regarding claims 13 and 30 , Han discloses: further comprising: generating a report containing information about tests that produce test results by testing the device using a first test platform that are not wholly correlated to test results produced by testing the device using a second test platform; and outputting the report (see page 9, the invention compared with the traditional test design process, for the circuit, test coverage ratio is higher than other four configuration, automatic test vector generating time; the power consumption is lower than other four configurations …., [wherein the traditional test design process is a second test platform]) . Regarding claims 14 and 31 , Han discloses: wherein the report identifies which of the tests produce results on the first test platform are not wholly correlated to test results produced by testing the device using the second test platform (see page 9, the invention compared with the traditional test design process, for the circuit, test coverage ratio is higher than other four configuration, automatic test vector generating time; the power consumption is lower than other four configurations …., [wherein the traditional test design process is a second test platform]) . Regarding claims 16 and 33 , Han discloses: further comprising: testing a device on a test platform using a test program comprised of tests having the one or more criteria optimized based on the one or more parameters (see page 6, the model is realized by python programming, wherein the learning rate is 0.01, the iteration times is 600; after executing the program, manually inputting the parameter to be predicted ….) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Han et al. (CN 113128147 A ) further in view of Feng et al. ( CN Pub. No. 102566299 A ) . Regarding claims 6 and 23 , Han fails to disclose: wherein the cost function comprises a non-linear function to optimize the one or more criteria. Thus, Feng discloses: wherein the cost function comprises a non-linear function to optimize the one or more criteria (see par [0 0 13], design variables in the optimization. the cost function is a non-linear function of the design variables ….) . It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified a high efficiency integrated circuit testability design method based on machine learning of Han to include cost function comprises a non-linear function in order to established in the cost function by choosing suitable design variables (see Feng par [00 23 ]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7 , 17, 24, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Han et al. (CN 113128147 A ) and Feng et al. (CN Pub. No. 102566299 A ) further in view of De et al. (Pub. No. 20230153597 A1) . Regarding claims 7 and 24 , Han and Feng fail to disclose: wherein the cost function comprises a linear function to optimize the one or more criteria based on weights associated with the one or more criteria. Thus, De discloses: wherein the cost function comprises a linear function to optimize the one or more criteria based on weights associated with the one or more criteria (see par [0138-0139], Linear and polynomial regression modeling returns an output equation with input variables and their coefficients as dependent parameters by reducing the cost function (also known as loss function) across different iterations …., t he final coefficients of the input-output relation or weights of the regression …) . It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified a high efficiency integrated circuit testability design method based on machine learning of Han to include cost function comprises a non-linear function in order to established in the cost function by choosing suitable design variables (see Feng par [0023]). Regarding claims 17 and 34 , De discloses: wherein the artificial intelligence process or machine learning process comprises a neural network, the neural network comprising a cost function that optimizes the one or more criteria based on variations of the one or more parameters. (see par [0016], there is on-chip analog neural network which can be trained to implement a non-linear regression function …., see par [0059]) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 8 -9, 15, 25-26, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Han et al. (CN 113128147 A ) further in view of Jo et al. (KR Pub. No. 102696205 B1 ) . Regarding claims 8 and 25 , Han fails to disclose: wherein the artificial intelligence process or machine learning process comprises a genetic algorithm. Thus, Jo discloses: wherein the artificial intelligence process or machine learning process comprises a genetic algorithm (see page 2, 3, and 7, t he present invention relates to an alloy reverse design method and an integrated module interface using an artificial neural network-based forward machine learning and a genetic algorithm ….) . It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified a high efficiency integrated circuit testability design method based on machine learning of Han to include the artificial intelligence process or machine learning process comprises a genetic algorithm in order to simulates the evolutionary process of organisms to find the optimal solution (see Jo page 3 par [3]). Regarding claims 9 and 26 , Jo discloses: wherein the genetic algorithm comprises a fitness function that is either linear or non-linear (see page 13, a genetic algorithm-based reverse design that utilizes a forward machine learning model as a fitness function ….) . Regarding claims 15 and 32 , Jo discloses: wherein the optimization process comprises a supervised learning process (see page 3, A representative example is 'supervised learning', which uses an algorithm to analyze training data ….) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT BRIAN NGO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7011 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 7AM-4PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Jack Chiang can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712727483 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN NGO/ Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Jun 20, 2023
Application Filed
Mar 26, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.2%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 967 resolved cases by this examiner. Grant probability derived from career allow rate.

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