DETAILED ACTION
This action is in response to communications: Amendment filed June 25, 2026.
Claims 1-20 are pending in this case. Claims 1-3, 18, and 20 have been newly amended. No claims have been newly added or cancelled. This action is made FINAL.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10, 11, 13, 14, and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 10,083,538) in view of Hempel et al. (US 7,973,790).
As to claim 1, Li discloses a processing system configured to render one or more images of a scene (e.g. Figure 1, further implementing processes of Figures 15-23), the processing system comprising: rendering logic (scene renderer 142) configured to process graphics data to render generate an initial image suitable for display (2D projection(s) 160, 161)(column 9, lines 60 thru column 10 6-28 notes 3D scene model 141 contains a 3D representation of the objects that may be displayed to the user, where scene generator 142 generates one or more rendered 2D images, e.g. 2D projections 160, 161 from scene model 141, which may be displayed directly to display(s) 110, 111)(Figures 15-17, column 22, lines 33-67 notes partitioning a display image into display regions, e.g. as groups of pixels into grid elements, further as low resolution display regions and high resolution display regions, and renderer may generate values for grid elements of the display regions, where the renderer may be implemented as a “variable resolution renderer,” for rendering each of the different regions of the display, further described in Figure 19, column 23, lines 31 thru column 24, lines 3 notes renderer comprising different levels of detail models, e.g. a high level of detail model and a low level of detail model, Figure 20, column 24, lines 4-36 notes renderer comprising ray casting and ray tracing, Figures 21-23, column 24, lines 37 thru column 25, lines 64 notes renderer comprising rasterization), the initial image comprising pixel values representing an image of the scene (e.g. as noted above, pixels are grouped as part of grid elements representing an image of the scene, where Figure 18, column 23, lines 1-30 notes renderer renders a model onto grid 1801, each grid may correspond to 4 pixels in a display region, then the rendering process for grid elements sets the grid element values for each grid element, e.g. color, hue, saturation, value, intensity, texture, lighting, normal vector direction, material, transparency, or depth); ray tracing logic (ray tracing, e.g. part of scene renderer 142) configured to perform ray tracing for one or more regions of the initial image (e.g. column 24, lines 29-36 notes using mixed rendering techniques for rendering low resolution display regions and high resolution display regions, e.g. using ray casting to render low resolution display regions (column 24, lines 37-39 notes alternative to ray casting as rasterization) but other techniques to render high resolution display regions, e.g. ray tracing); and update logic (image warper 123) configured to update one or more pixel values of the initial image, to thereby determine an updated image to be outputted for display (column 10, lines 29-55 notes image warper for rerendering the 2D projections 160, 161 for certain types of changes in the user’s pose, which uses approximations to reduce calculations and communications required to update the display, e.g. Figure 7, column 14, lines 58 thru column 15, lines 15 further notes image warper 123 calculates virtual camera pose 242b corresponding to the most recent body pose 222b, and compares it to the virtual camera pose 242a used for rendering projection 161a, where the difference in these virtual camera poses is applied to post rendering correction 701, which modifies 2D projection 161a based on recent pose changes to generate corrected 2D projection 161b, which is sent to display 111).
As noted above, Li describes its renderer may be a “variable resolution renderer” which may comprise rasterization as well as ray casting and ray tracing, which may be used for rendering different regions of a display, e.g. rasterization may be used to render lower resolution display regions, where ray tracing may be used to render higher resolution display regions. However, Li does not elaborate on the ray tracing process/technique. Therefore, Li differs from the invention defined in claim 1 in that Li does not explicitly disclose its ray tracing logic to perform ray tracing to “determine ray traced data” for one or more regions of the initial image; and its update logic configured to update one or more pixel values of the initial image “using the determined ray traced data for the one or more regions of the initial image,” to thereby determine an updated image to be outputted for display (portions in quotations not explicitly taught).
Hempel et al. further disclose a processing system (e.g. a graphics processing system (not illustrated) including a graphics processing unit (GPU), column 3, lines 54-58) configured to render one or more images of a scene (e.g. to perform the process as outlined in Figure 1), the processing system comprising: rendering logic (e.g. rasterizer) configured to process graphics data to render an initial image, the initial image comprising pixel values representing an image of the scene (e.g. Figure 1, step 110, column 5, lines 66-67, notes generating an image using rasterization after determining which pixels contain polygon vertices that include reflective and/or refractive surfaces at step 100, column 5, lines 62-66, where column 6, lines 18-33 further notes the image is rendered with rasterization); ray tracing logic (e.g. ray tracer) configured to perform ray tracing to determine ray traced data for one or more regions of the initial image (e.g. Figure 1, step 140, column 6, lines 6-9 notes for each foreground polygon vertex determined in step 130 (column 6, lines 3-6), generating a secondary ray from the polygon using the directional vector associated with the polygon vertex); and update logic (e.g. shader) configured to update one or more pixel values of the initial image using the determined ray traced data for the one or more regions of the initial image (e.g. Figure 1, step 150, column 6, lines 9-12 notes a shader program is then invoked to accurately render the remainder of the image, the shader invocation may result in additional recursive secondary ray generation, where column 6, lines 18-52 further notes raytracing and rasterization may use the same shader programs to compute consistent colours), to thereby determine an updated image to be outputted for display (column 1, lines 45-47 notes each sampled point is written to an array of colour values called the frame buffer, each value in the colour array corresponds to a pixel on the screen, where it is well known in the art that these values are then output from the frame buffer to a display).
It would have been obvious to one of ordinary skill in the art to modify Li’s system and method of rendering lower and higher resolution display regions of images using hybrid techniques, e.g. rasterization and ray tracing, with Hempel et al.’s hybrid method of rasterization and ray tracing as well as shader techniques to allow more consistent evaluation of pixel properties, resulting in a more consistent image with accurate reflections (see Summary of the Invention of Hempel et al.).
As to claim 2, Li modified with Hempel et al. disclose the rendering logic is configured to process the graphics data using a rasterisation technique to render the initial image (Li, e.g. as noted in claim 1, the renderer may be a “variable resolution renderer,” where column 24, lines 29-39 notes it may include hybrid techniques including ray casting, ray tracing, and/or rasterization, thus may be used to generate the initial image; modified with Hempel, e.g. as noted in claim 1, rasterizer performs rasterization).
As to claim 3, Li modified with Hempel et al. disclose the rendering logic is configured to process the graphics data using a ray tracing technique to render the initial image (Li, e.g. as noted in claim 1, the renderer may be a “variable resolution renderer,” where column 24, lines 29-36 notes it may include hybrid techniques including ray tracing, thus may be used to generate the initial image).
As to claim 4, Li modified with Hempel et al. disclose the initial image is a lower detail image than the updated image (Li, e.g. as noted in claim 1, the 2D projection may include lower resolution display regions; modified with Hempel, e.g. as noted in claim 1, the initial image is generated via rasterization, where the image is ultimately shaded via shader (or shader program), where column 1, lines 43-44 notes a shader program computes colour for each point from the interpolated vertex attributes, and column 2, lines 32-34 notes shaders are important in high-quality rendering, thus may be considered to produce a higher detail image than the initial image generated via rasterization).
As to claim 10, Li modified with Hempel et al. disclose region identification logic configured to identify the one or more regions of the initial image, wherein the region identification logic is configured to analyse the initial image to determine one or more regions of high frequency, wherein the one or more determined regions of high frequency are the one or more identified regions of the initial image (Li, e.g. as noted in claim 1, renderer may partition the display image into display regions comprising low resolution display regions and high resolution display regions, where, for example, Figure 19, column 23, lines 31 thru column 24, lines 3 notes renderer comprising different levels of detail models, e.g. a high level of detail model and a low level of detail model, where the high level of detail model is utilized for rendering the high resolution display regions and the low level of detail model is utilized for rendering the low resolution display regions).
As to claim 11, Li modified with Hempel et al. disclose the rendering logic (Li, modified with Hempel, e.g. rasterizer) and the ray tracing logic (Li, modified with Hempel, e.g. ray tracer) are configured to operate asynchronously (modified with Hempel, e.g. as noted in claim 1, in each of Figures 1 and 2, rasterization is performed prior to ray tracing, thus may be considered to operate asynchronously).
As to claim 13, Li modified with Hempel et al. disclose time warping logic configured to apply an image warping process to the updated image before it is sent for display (Li, e.g. as noted in claim 1, image warper 123 for rerendering the 2D projections 160, 161 for certain types of changes in the user’s pose, which uses approximations to reduce calculations and communications required to update the display, e.g. Figure 7, column 14, lines 58 thru column 15, lines 15 further notes image warper 123 calculates virtual camera pose 242b corresponding to the most recent body pose 222b, and compares it to the virtual camera pose 242a used for rendering projection 161a, where the difference in these virtual camera poses is applied to post rendering correction 701, which modifies 2D projection 161a based on recent pose changes to generate corrected 2D projection 161b, which is sent to display 111).
As to claim 14, Li modified with Hempel et al. disclose acceleration structure building logic configured to determine an acceleration structure representing the graphics data of geometry in a scene of which an image is to be rendered (modified with Hempel, column 4, lines 19-27 notes techniques of the present invention used to conjunction with any raytracer algorithm, including that described in KD-Tree Acceleration Structures for a GPU Raytracer, which describes building an acceleration structure for scenes with many objects on the GPU (reference provided)).
As to claim 16, Li modified with Hempel et al. disclose the processing system is arranged to be included in a virtual reality system or an augmented reality system (Li, Figure 1, column 6, lines 43-48 notes embodiment of low-latency virtual reality display system, e.g. illustrated as virtual reality goggles in communication with a wireless mobile device).
As to claim 17, Li modified with Hempel et al. disclose the update logic (modified with Hempel, e.g. shader) is configured to update the initial image using the determined ray traced data for the one or more regions of the initial image by adding detail to the one or more regions of the initial image (modified with Hempel, e.g. as noted in claim 1, shading is performed after ray tracing, thus uses the determined ray traced data by adding detail, e.g. as further noted in claim 4, colour and high quality rendering).
As to claim 18, Li modified with Hempel et al. disclose a method of rendering one or more images of a scene at a processing system (Li, Figure 1; modified with Hempel, Figure 1), the method comprising steps similar to the steps as performed by the processing system of claim 1. Please see the rejection and rationale of claim 1 above.
As to claim 19, Li modified with Hempel et al. disclose displaying an image based on the updated image (Li, e.g. as noted in claim 1, after image warping is performed, the updated image may be displayed; modified with Hempel, column 1, lines 43-47 notes a shader program is invoked to compute colour for each point from the interpolated vertex attributes, each sampled point is written to an array of colour values called the frame buffer, each value in the colour array corresponds to a pixel on the screen, where it is well known in the art that these values are then output from the frame buffer to a display).
Claim(s) 5, 7, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 10,083,538) in view of Hempel et al. (US 7,973,790) as applied to claim 1 above, and further in view of Nilsson, Foveated Real-Time Ray Tracing, pages 1-6 (cited in Information Disclosure Statement (IDS) filed June 20, 2023).
As to claim 5, Li modified with Hempel et al. disclose region identification logic configured to identify the one or more regions of the initial image (Li, e.g. as noted in claim 1, renderer may partition display regions into low resolution display regions and high resolution display regions), where Nilsson further discloses region identification logic configured to identify the one or more regions of the initial image (e.g. identifying regions including foveal, parafoveal, and peripheral regions) and gaze tracking logic configured to determine one or more gaze positions for the initial image (e.g. eye tracking to determine observer’s gaze), wherein the region identification logic is configured to receive one or more indications of the one or more determined gaze positions, and to identify the one or more regions of the initial image based on the one or more determined gaze positions (page 2, section 3.1 Hardware, paragraph 1 notes Tobii EyeX Devkit Controller, which is a consumer-level corneal-reflection eye tracking device, which may [determine] the position the gaze of an observer on a computer screen, pages 2-3, section 3.2 Software, paragraphs 1-5 notes utilizing Tobii C/C++ SDK for retrieval of gaze positional data and communication with the eye tracking device, where the rendering process is subdivided into a number of FOV’s (e.g. fovea, parafovea, peripheral, etc.) to achieve varying levels of quality or resolution in the field of vision).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Li modified with Hempel et al.’s system including ray tracing logic to further comprise region identification logic and gaze tracking logic as described in Nilsson to accelerate the ray tracing algorithm by employing foveation to reduce graphics processing unit (GPU) workload, thus enhancing the functionality and performance of the graphics system (e.g. page 1, Introduction of Nilsson).
As to claim 7, Li modified with Hempel et al. and Nilsson one of the one or more identified regions of the initial image surrounds one of the one or more determined gaze positions, thereby representing a foveal region (Nilsson, pages 2-3, section 3.2 Software, paragraphs 1-5 notes identifying fovea, parafovea, and peripheral regions).
As to claim 8, Li modified with Hempel et al. and Nilsson a camera pipeline which is configured to: receive image data from a camera which is arranged to capture images of a user looking at a display on which a rendered image is to be displayed; and process the received image data to generate a captured image; wherein the gaze tracking logic is configured to analyse the captured image to determine the gaze position for the initial image (Nilsson, page 2, section 3.1 Hardware, paragraph 1 notes Tobii EyeX Devkit Controller, which is a consumer-level corneal-reflection eye tracking device, which may [determine] the position the gaze of an observer on a computer screen, pages 2-3, section 3.2 Software, paragraphs 1-5 notes utilizing Tobii C/C++ SDK for retrieval of gaze positional data and communication with the eye tracking device, and rendering a number of FOV’s (e.g. fovea, parafovea, peripheral, etc.) to achieve varying levels of quality or resolution in the field of vision, thus the hardware and software, e.g. pipeline, utilized for gaze tracking).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 10,083,538) in view of Hempel et al. (US 7,973,790) and Nilsson, Foveated Real-Time Ray Tracing, pages 1-6 as applied to claim 5 above, and further in view of D’Amico et al. (US 9,261,959).
As to claim 6, Li modified with Hempel et al. and Nilsson do not disclose, but D’Amico et al. disclose the gaze tracking logic is configured to implement a predictive model to anticipate movements in gaze (column 4, lines 27-45 notes memory 114 may function as a database of information related to gaze direction and/or HMD wearer eye location, where such information may be used by the HMD 100 to anticipate where the wearer will look and determine what images are to be displayed to the wearer).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Li modified with Hempel et al. and Nilsson’s system to include the gaze tracking logic with D’Amico et al.’s method of anticipating movements in gaze to ultimately enhance gaze tracking by speeding up processing, thus reducing latencies of the system (column 4, lines 27-45 of D’Amico et al.).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 10,083,538) in view of Hempel et al. (US 7,973,790) and Nilsson, Foveated Real-Time Ray Tracing, pages 1-6 as applied to claim 8 above, and further in view of Newcombe et al. (US 2012/0194644).
As to claim 9, Li modified with Hempel et al. and Nilsson disclose the ray tracing logic and the rasterisation logic are implemented on a graphics processing unit (Li, column 10, lines 6-21 notes scene renderer 142, as a “variable resolution renderer,” may be implemented in graphics processing units; modified with Hempel, column 3, lines 54-58 notes rasterization and raytracing implemented in GPU), but do not disclose, but Newcombe et al. disclose wherein the camera pipeline and the graphics processing unit are implemented as part of a system on chip (SOC) ([0096] notes computing-based device 1404 comprises one or more processors 1400 which may be microprocessors, graphics processing units (GPUs), controllers or any other suitable type of processors for processing computing executable instructions to control the operation of the device in order to provide real-time camera tracking, e.g. a system on chip architecture is used, where processors 1400 may include one or more fixed function blocks which implement a part of the method of real time camera tracking in hardware).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Li modified with Hempel et al. and Nilsson’s system to implement the camera pipeline and graphics processing unit as part of a system on chip (SoC) as described in Newcombe et al. which is well known to reduce transmission times between components of the SoC as well as reduce the overall size of the device, thus enhancing the system.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 10,083,538) in view of Hempel et al. (US 7,973,790) as applied to claim 1 above, and further in view of Du et al. (US 2009/0096797).
As to claim 12, Li modified with Hempel et al. disclose the ray tracing logic and the update logic…and…the rendering logic, but do not disclose, but Du et al. disclose the ray tracing logic and the update logic (e.g. fragment shader 314D) are configured to operate at a first rate, and wherein the rendering logic (e.g. rasterizer 314C) is configured to operate at a second rate, wherein the first rate is faster than the second rate (Figure 3, and associated text, e.g. [0032] notes power controller is configured to adjust power and clock input signals to each of the components of pipeline 308 independent of the other components based on status information collected for the components, where the power controller 210 can change (increase or decrease) the power and/or clock frequency to one or more components of the pipeline 308 while leaving the power and/or clock frequency for the other components of the pipeline 30 unchanged, thus considered that each pipeline component may operate at different rates).
NOTE: Although Du et al. do not disclose a ray tracing logic, Li and Hempel et al. explicitly discloses the ray tracing logic as part of the graphics pipeline, thus it would have been obvious that the method may be applied to any graphics pipeline component that may be not be explicitly described.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Li modified with Hempel et al.’s rendering logic, ray tracing logic, and update logic to operate independently of each other, including operating at different clock frequencies (e.g. rates) based on respective workloads and status information of each component to reduce bottlenecks of the graphics pipeline that may occur when components are slower than other, thus enhancing the performance of the system ([0032] and [0042] of Du et al.).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 10,083,538) in view of Hempel et al. (US 7,973,790) as applied to claim 14 above, and further in view of Mejdrich et al. (US 2010/0188396).
As to claim 15, Li modified with Hempel et al. do not disclose, but Mejdrich et al. disclose the processing system is configured to render a plurality of images representing a sequence of frames, and wherein the acceleration structure building logic is configured to determine the acceleration structure for a current frame by updating the acceleration structure for the preceding frame (Figure 4, [00[0041] notes rendering image data according to a rate of change in the perspective of a viewer in between frames, more specifically, rendering based on the rate of change of a camera perspective, where a ray tracing operation may include updating an acceleration data structure (ADS) 120 in between frames (e.g. frame-to-frame) in response to a changing vantage point, where [0015] notes the rate of change may be based upon a rate of change associated with preceding frames of the plurality of frames, thus considered to update a preceding frame for a current frame).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Li modified with Hempel et al.’s system including ray tracing logic and acceleration structure building logic to determine the acceleration structure as described by Mejdrich et al. as building acceleration structures are well known in the art and common technique in ray tracing, thus yielding predictable results (see [0005] and [0008]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 10,083,538) in view of Hempel et al. (US 7,973,790), further in view of Tavenrath (US 8,379,022).
As to claim 20, Li modified with Hempel et al. disclose an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processing system comprising: (Li, Figure 1 and associated text, e.g. column 10, lines 18-21 notes techniques of the system, e.g. including the components therein, implemented in software libraries and graphics processing units; modified with Hempel, e.g. graphics processing system (not illustrated) including a graphics processing unit (GPU), column 3, lines 54-58, further including components as described in claim 1). Please see the rejection and rationale of claim 1 above.
Li modified with Hempel et al. differ from the invention defined in claim 20 in that Li modified with Hempel et al. do not disclose, but Tavenrath discloses a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processing system comprising logic components (Figure 4, where column 4, lines 65 thru column 5, lines 54 notes computer readable medium as memory for storing instructions for performing the operations of the graphics system, which includes rasterization, ray tracing, and fragment shading).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Li modified with Hempel et al.’s system and method to be implemented in a non-transitory computer readable storage medium as described in Tavenreth as computer readable mediums are well known in the art as part of computer systems for storing instructions (e.g. code and/or programs) which are executed by a processor to perform the method as outlined, thus yielding predictable results.
Response to Arguments
Applicant’s arguments, see pages 6-8, filed June 25, 2026, with respect to claims 1-20 have been fully considered and are persuasive. The 35 U.S.C. 112(a) claim rejection of claims 1-20 has been withdrawn.
Applicant's arguments filed June 25, 2026 have been fully considered but they are not persuasive. Applicant amends independent claims 1, 18, and 20 to similarly recite, “…rendering logic configured to process graphics data to render an initial image suitable for display…” Applicant argues on pages 9-16 that Hempel, as evidenced by Oneppo, does not teach or suggest the limitations of the claims as now amended. More specifically, Applicant argues that the image of Hempel is not rendered “…such that it is suitable for display until the shader has been executed” (see pages 10-12 under Hempel). Applicant further argues regarding evidenced reference Oneppo and the combination of Hempel and Oneppo.
In reply, independent claims 1, 18, and 20 are now rejected by Li (US 10,083,538) in view of Hempel. As noted in the rejection above, Hempel explicitly discloses its rasterizer may “render” an initial image, e.g. a rasterized image, where Hempel further discloses each of its rasterizer and ray tracing may independently invoke a shader program to compute colour (column 6, lines 25-32). Hempel discloses at step 150 that the shader program is invoked to accurately render the remainder of the image, e.g. including the ray traced portion. However, Hempel does not explicitly disclose the rendered image is “suitable for display.” Therefore, Li is used for explicitly teaching its image rendered, e.g. via rasterization, is suitable for display, even prior to image warping, e.g. updating. Additionally, as argued by the Applicant, Li describes rendering different images, e.g. of lower and higher resolutions, using hybrid techniques, similar to Hempel. Oneppo is no longer cited as prior art. Please see the rejection and notes regarding the claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US 9,761,039) disclose a system and method of hybrid rendering, e.g. generating a first image by rendering one or more first tiles via ray tracing using geometric information and generating a second image by rendering one or more second tiles via rasterization, and outputting a final image by merging the first and second images;
Aguera y Arcas (US 8,149,235) discloses a system and method of providing an original image having an array of samples, defining a two-dimensional target image having a higher resolution than the original image, defining a splat in the target image for each of a plurality of samples in the array, and rendering the plurality of splats employing a graphics processor; and
Berstis (US 7,129,981) discloses a system and method of rendering images having differing foveal area and peripheral view area resolutions.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m.
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617
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