CTNF 18/212,057 CTNF 100125 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 102 a1 as being anticipated by Bains (WO 2017/192626) . Regarding claim 1, Bains teaches: A dual in-line memory module (DIMM) (see fig. 6B, DIMM 640) comprising: a plurality of dynamic random access memory (DRAM) devices (see fig. 6B, DRAMS 0-8) , wherein each of plurality of DRAM devices includes on-die ECC bits (see fig. 7, Memory 750, a DRAM, includes extra bits 756. And see para. 59: system bits 246 provide an example of extra bits in accordance with any embodiment described herein. System bits can provide addition information for ECC.) , and wherein at least one of the plurality of DRAM devices includes circuitry to provide access to read from and write to the on-die ECC bits of the DRAM device (see fig. 7, interface D[4] provides access to read from and write to the on-die ECC bits. And see para. 100: In one embodiment, memory controller 710 is capable of coupling to memory 730 and memory 750 in parallel via a data bus, which can exchange extra bits 726 with selected memory devices, and specifically with memory devices 750… D[4] connected for the exchange of extra bits.) ; and a pin to transmit metadata to and from the on-die ECC bits of the DRAM device. (see fig. 7, I/O interface logic 714 which is similar to I/O interface logic 122 in fig. 1. And see para. 36: Memory controller 120 includes I/0 interface logic 122 to couple to a memory bus, such as a memory channel as referred to above. I/0 interface logic 122 (as well as I/0 interface logic 142 of memory device 140) can include pins.) The extra bits of Bains are considered to be on-die ECC bits because they are stored on a die of the DRAM device and are associated with ECC operations. Regarding claim 2, Bains teaches the DIMM of claim 1. Bains further teaches: wherein: the DRAM device includes an on-die ECC pin coupled with the pin of the DIMM to transmit metadata to and from the on-die ECC bits of the DRAM device. (see fig. 7, I/O interface 752 of DRAM 750 is effectively coupled with I/O interface 714 of the Memory Controller of the DRAM. Also see para. 36: Memory controller 120 includes I/0 interface logic 122 to couple to a memory bus, such as a memory channel as referred to above. I/0 interface logic 122 (as well as I/0 interface logic 142 of memory device 140) can include pins. see para. 100: In one embodiment, memory controller 710 is capable of coupling to memory 730 and memory 750 in parallel via a data bus, which can exchange extra bits 726 with selected memory devices, and specifically with memory devices 750… D[4] connected for the exchange of extra bits.) Regarding claim 3, Bains teaches the DIMM of claim 1. Bains further teaches: the circuitry of the DRAM device is to provide the metadata stored in the on-die ECC bits in response to a read request. (see para. 52: In one embodiment, memory controller 120 can provide extra system bits to memory device 140, and the same extra bits can be returned by the memory device in response to a read request. And see fig. 7, which depicts extra bits connected to memory controller via DRAM circuitry interface D[4].) Regarding claim 4, Bains teaches the DIMM of claim 1. Bains further teaches: the DRAM device includes circuitry to write the metadata to the on-die ECC bits in response to a write request. (see para. 52: In one embodiment, memory controller 120 can provide extra system bits to memory device 140 (i.e., via a write request), and the same extra bits can be returned by the memory device in response to a read request. And see fig. 7, which depicts extra bits connected to memory controller via DRAM circuitry interface D[4].) Regarding claim 5, Bains teaches the DIMM of claim 1. Bains further teaches: the DRAM device includes one or more registers to store a value to enable reading metadata from and writing metadata to the on-die ECC bits. (see para. 43: In one embodiment, memory devices 140 include one or more registers 144. Register 144 represents one or more storage devices or storage locations that provide configuration or settings for the operation of the memory device… In one embodiment, register 144 includes one or more Mode Registers. In one embodiment, register 144 includes one or more multipurpose registers. The configuration of locations within register 144 can configure memory device 140 to operate in different "mode," where command information can trigger different operations within memory device 140 base on the mode. Additionally or in the alternative, different modes can also trigger different operation from address information or other signal lines depending on the mode Settings of register 144 can indicate configuration for 1/0 settings (e.g., timing, termination or ODT (on-die termination) 146, driver configuration, or other 1/0 settings). And see para. 45: Controller 150 can determine what mode is selected based on register 144, and configure the internal execution of operations for access to memory resources 160 or other operations based on the selected mode. Controller 150 generates control signals to control the routing of bits within memory device 140 to provide a proper interface for the selected mode and direct a command to the proper memory locations or addresses.) Regarding claim 6, Bains teaches the DIMM of claim 1. Bains further teaches: the DRAM device to provide access to read from and write to the on-die ECC bits is an ECC device of the DIMM. (see fig. 7, interface D[4] provides access to read from and write to the on-die ECC bits (extra bits).) Interface D[4] is considered to be an ECC device because it is used for the writing and reading of on-die ECC bits (extra bits), and is also considered to be a device of the DIMM because it is within a DRAM, and as shown in fig. 6B, all DRAMs are part of the DIMM. Regarding claim 7, Bains teaches the DIMM of claim 1. Bains further teaches: the on-die ECC pin of only one of the plurality of DRAM devices per channel is coupled with the pin of the DIMM. (see para. 96 and fig. 6B: As illustrated, DRAM[0], DRAM[2], DRAM[4], and DRAM[6] per channel provide an additional bit, and are illustrated as being Dx4+1, or a x4 interface for data, plus one additional signal line to transfer an extra bit. It will be understood that the implementation illustrated is merely one example, and any different DRAM device can be selected to provide an additional bit. In one embodiment, register 650 can select a DRAM device to provide the extra bit. And see para. 97: the DRAM devices illustrated as Dx4 have a fifth interface signal line, and could be configured as Dx4+1, but the additional interface signal line is not connected.) Any DRAM device can be selected to provide an additional bit (on-die ECC bit, extra bit 756 in fig. 7), therefore this discloses, for example, only DRAM[0] per channel is selected to provide an additional bit. This additional bit transferred on the fifth interface signal line corresponds to the connection between on-die ECC pin D[4] and the DIMM pin in I/O interface 714 from fig. 7. Regarding claim 8, Bains teaches the DIMM of claim 1. Bains further teaches: the on-die ECC pin of multiple DRAM devices of the plurality of DRAM devices are coupled with the pin of the DIMM. (see para. 96 and fig. 6B: As illustrated, DRAM[0], DRAM[2], DRAM[4], and DRAM[6] per channel provide an additional bit, and are illustrated as being Dx4+1, or a x4 interface for data, plus one additional signal line to transfer an extra bit. And see para. 97: the DRAM devices illustrated as Dx4 have a fifth interface signal line, and could be configured as Dx4+1, but the additional interface signal line is not connected.) This additional bit transferred on the fifth interface signal line corresponds to the connection between on-die ECC pin D[4] and the DIMM pin in I/O interface 714 from fig. 7. Regarding claim 9, Bains teaches the DIMM of claim 8. Bains further teaches: a data buffer to collate the metadata to and from the on-die ECC bits of the multiple DRAM devices. (see para. 87: Register 610 represents a controller for system 602, or a controller for a memory module or DIMM represented by system 602. It will be understood that the controller represented by register 610 is different from a host controller or memory controller (not specifically shown) of a computing device in which system 602 is incorporated. Likewise, the controller of register 610 is different from an on-chip or on-die controller that is included on the DRAM devices 620. In one embodiment, register 610 is a registered clock driver (which can also be referred to as a registering clock driver). The registered clock driver receives information from the host (such as a memory controller) and buffers the signals from the host to the various DRAM devices 620. If all DRAM devices 620 were directly connected to host 630, the loading on the signal lines would degrade high speed signaling capability. By buffering the input signals from the host, host 630 only sees the load of register 610, which can then control the timing and signaling to the DRAM devices 620. In one embodiment, register 610 is a controller on a DIMM to control signaling to the various memory devices. Also see para. 82: In one embodiment, where 9 DRAM devices are used, 5 devices can provide x4 interfaces (20 bits) plus another 4 devices that provide x5 interfaces (20 bits) such as those illustrated in Figures 4A-4C. Data transfers from the DRAM devices could be buffered (for example in a DIMM register) and transmitted over 40 signal lines.) Metadata to and from the DRAMs is disclosed to be buffered in a register. The term collate is interpreted as “collecting and storing together”, therefore a register receiving data and temporarily storing it via buffering is considered to be collating the data. Regarding claim 10, Bains teaches the DIMM of claim 1. Bains further teaches: the on-die ECC pin of selected DRAM devices of the plurality of DRAM devices is coupled with the pin of the DIMM; and the on-die ECC pin of unselected DRAM devices of the plurality of DRAM devices is open, or tied to VDD or VSS. (see para. 100: memory controller can exchange extra bits with selected memory devices, and specifically with memory devices 750. IN one embodiment, memory devices 730 include interface D[4], but is not connected, and only D[0:3] are connected for the exchange of data 722 and system ECC 724. In one embodiment, memory devices 750 are connected for the exchange of data 722 and system ECC 724 with D[0:3], and also include D[4] connected for the exchange of extra bits 726. Also see para. 97: the DRAM devices illustrated as Dx4 have a fifth interface signal line, and could be configured as Dx4+1, but the additional interface signal line is not connected.) This additional bit transferred on the fifth interface signal line corresponds to the connection between on-die ECC pin D[4] and the DIMM pin in I/O interface 714 from fig. 7. Claim 15 corresponds to claim 1, and is rejected accordingly, but for the following added limitations, which are additionally taught by Bains: A motherboard including a dual in-line memory module (DIMM) connector; (para. 41: in one embodiment, memory devices 140 are disposed directly on a motherboard, also see fig. 6B depicting the connection between DIMM 640 and Host 660, a DIMM connector.) a plurality of conductive contacts proximate to an edge of the DIMM to be received by the DIMM connector, wherein one or more of conductive contacts is to transmit metadata to and from the on-die ECC bits of at least one of the DRAM devices (see para. 34: As used herein, coupling can refer to an electrical coupling, communicative coupling, physical coupling, or a combination of these. Physical coupling can include direct contact. Electrical coupling includes an interface or interconnection that allows electrical flow between components, or allows signaling between components, or both. Communicative coupling includes connections, including wired or wireless, that enable components to exchange data. And see fig. 6B depicting host 660 connected to data bus 644[0] and 644[1] through a DIMM connector via conductive contacts proximate to an edge of the DIMM. Metadata is then transmit via these data busses to and from on-die ECC bits (extra bits) of DRAMs 0, 2, 4, and 6.) Regarding claim 20, Bains teaches the system of claim 15. Bains further teaches: Further comprising one or more of: A memory controller, a processor, and a display. (see para. 113: In one embodiment, system 1000 includes interface 1012 coupled to processor 1010, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem 1020 or graphics interface components 1040… In one embodiment, graphics interface 1040 can drive a high definition (HD) display that provides an output to a user. And see para. 114: In one embodiment, memory subsystem 1020 includes memory controller 1022, which is a memory controller to generate and issue commands to memory 1030.) Claims 11, 12-14, and 16-19 correspond to claims 1, 3-5, and 6-9 (respectively), and are rejected accordingly. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK KENSINGTON BARNETT/Examiner, Art Unit 2111 /MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111 Application/Control Number: 18/212,057 Page 2 Art Unit: 2111 Application/Control Number: 18/212,057 Page 3 Art Unit: 2111 Application/Control Number: 18/212,057 Page 4 Art Unit: 2111 Application/Control Number: 18/212,057 Page 5 Art Unit: 2111 Application/Control Number: 18/212,057 Page 6 Art Unit: 2111 Application/Control Number: 18/212,057 Page 7 Art Unit: 2111 Application/Control Number: 18/212,057 Page 8 Art Unit: 2111 Application/Control Number: 18/212,057 Page 9 Art Unit: 2111 Application/Control Number: 18/212,057 Page 10 Art Unit: 2111
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