Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 17, which discloses “the second switch circuit further comprises a seventh transistor with a control terminal of the seventh transistor coupled to the second switch signal, a first non-control terminal of the seventh transistor coupled to the respective second non-control terminals of the third and fourth transistors, and a second non-control terminal of the seventh transistor coupled to ground.” This is unclear. The examiner assumed the seventh transistor claimed is transistor (M7) of Figure 4. However, the first non-control terminal (drain) if the transistor (M7) ONLY coupled to the second non-control terminal (source) of transistor (M4), which is called third transistor, Note, the first non-control terminal (drain) of transistor (M7) is not coupled to the fourth transistor (M5). Clarification is needed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-6, 8, 9, 15 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khalaf et al. (20210194445), hereafter called KHALAF.
Regarding claim 1, KHALAF (Figs. 1 and 2) disclose a circuit comprising multiple gain circuits coupled in parallel, see Fig. 3, wherein one or more of the multiple gain circuits comprises: a first differential gain circuit (191) coupled to a first differential input (110), a second differential input (111), a first differential output (160), and a second differential output (161); a second differential gain circuit (192) cross-connected with the first differential gain circuit; and a switch circuit (180 and 171) and coupled to the first and second differential gain circuits (191 and 192) to selectively activate only one of the first and second differential gain circuits, see Figs. 1B and 1C.
Regarding claim 2, wherein the second differential gain circuit (192) is coupled in parallel with the first differential input and the second differential input and coupled with the first and second differential outputs reversed with respect to the first differential gain circuit.
Regarding claim 4, wherein the second differential gain circuit (192) provides neutralization for the first differential gain circuit when it is off, see Fig. 1B.
Regarding claim 5, wherein the switch circuit (180, 170) is further to set the second differential gain circuit (192) in either OFF/ON, which can be a cutoff mode or a saturation mode.
Regarding claim 6, wherein the switch circuit comprises: a first tail switch (180) controllable by a first switch signal (181) and coupled to the first differential gain circuit (191); and a second tail switch (170) controllable by a second switch signal (171) and coupled to the second differential gain circuit (192), wherein the second switch signal is a complement of the first switch signal.
Regarding claim 8, KHALAF (Figs. 1 and 2) discloses a circuit comprising a variable gain amplifier with multiple gain circuits coupled in parallel, wherein one or more of the multiple gain circuits comprises: a first differential pair of transistors (140, 150); and a complementarily switched second differential pair of transistors (120, 130) cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors.
Regarding claim 9, wherein the second differential gain circuit (192) provides neutralization for the first differential gain circuit when it is off, see Fig. 1B.
Claim(s) 1, 2, 4-6, 8, 9, 15 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (20060140034), hereafter called HSU.
Regarding claim 1, KHALAFHSU (Fig. 2) disclose a circuit comprising multiple gain circuits coupled in parallel, wherein one or more of the multiple gain circuits comprises: a first differential gain circuit (222 and 224) coupled to a first differential input (BL), a second differential input (BL-), a first differential output (111), and a second differential output (113); a second differential gain circuit (232 and 234) cross-connected with the first differential gain circuit; and a switch circuit (262 and 264) and coupled to the first and second differential gain circuits to selectively activate only one of the first and second differential gain circuits based on enable/disable of switches (262 and 264).
Regarding claim 2, wherein the second differential gain circuit (232 and 234) is coupled in parallel with the first differential input and the second differential input and coupled with the first and second differential outputs reversed with respect to the first differential gain circuit (222 and 224).
Regarding claim 4, wherein the second differential gain circuit (232 and 234) provides neutralization for the first differential gain circuit (222 and 224) when it disable.
Regarding claim 5, wherein the switch circuit (262 and 264) is further to set the second differential gain circuit (232 and 234) in either disable/enable, which can be a cutoff mode or a saturation mode.
Regarding claim 6, wherein the switch circuit comprises: a first tail switch (262) controllable by a first switch signal (via NOR gate (252)) and coupled to the first differential gain circuit (222 and 224); and a second tail switch (264) controllable by a second switch signal (via NOR gate (254)) and coupled to the second differential gain circuit (232 and 234), wherein the second switch signal is a complement of the first switch signal.
Regarding claim 8, HSU (Fig. 2) discloses a circuit comprising a variable gain amplifier with multiple gain circuits coupled in parallel, wherein one or more of the multiple gain circuits comprises: a first differential pair of transistors (222 and 224); and a complementarily switched second differential pair of transistors (232 and 234) cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors.
Regarding claim 9, wherein the second differential gain circuit (232 and 234) provides neutralization for the first differential gain circuit when it is disable.
Claim(s) 15, 16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (20060140034), hereafter called HSU.
Regarding claim 15, HSU (Fig. 4) discloses a circuit comprising: first (222), second (224), third (234), and fourth (232) transistors, each with respective control terminals (gate), first non-control terminals (drain), and second non-control terminals (source); respective control terminals of the first and third transistors (222 and 234) coupled to a first differential input (BL), and respective control terminals of the second and fourth transistors (224 and 232) coupled to a second differential input (BL-); respective first non-control terminals of the first and fourth transistors (222 and 232) coupled to a first differential output (111/OUT), and respective first non-control terminals of the second and third transistors (224 and 234) coupled to a second differential output (113/OUT-); respective second non-control terminals of the first and second transistors (222 and 224) coupled to ground through a first switch circuit (262) that is to be controlled by a first switch signal via NOR gate (252); and respective second non-control terminals of the third and fourth transistors (232 and 234) coupled to ground through a second switch circuit (264) that is to be controlled by a second switch signal via NOR gate (254) that is a complement of the first switch signal.
Regarding claim 16, wherein the first switch circuit comprises a fifth transistor (262) with a control terminal (gate) of the fifth transistor coupled to the first switch signal via NOR gate (252), a first non-control terminal (drain) of the fifth transistor coupled to the respective second non-control terminals (sources) of the first and second transistors (222 and 224), and a second non-control terminal (source) of the fifth transistor coupled to ground, and wherein the second switch circuit comprises a sixth transistor (264) with a control terminal (gate) of the sixth transistor coupled to the second switch signal via NOR gate (254), a first non-control terminal (drain) of the sixth transistor coupled to the respective second non-control terminals of the third and fourth transistors (232 and 234), and a second non-control terminal (source) of the sixth transistor coupled to ground.
Regarding claim 20, see Fig. 2 of HSU, wherein elements (240-254) formed a gain control circuit to selectively provide respective switch signals to respective slices of the variable gain amplifier based on an amount of gain to be provided by the variable gain amplifier.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over KHALAF/HSU.
Regarding claim 3, which stated the second differential gain circuit is coupled in parallel with the first differential output and the second differential output and coupled with the first and second differential inputs reversed with respect to the first differential gain circuit. KHALAF discloses cross-coupled/connected output and not input as claimed. This is another way of obtain a cross-coupled/connected, which is well known in the art and thus would have been obvious to a person having ordinary skill in the art, see Meninger (20120206198), Fig. 4.
Regarding claims 7 and 14, which stated an operational frequency of the variable gain amplifier is in excess of ten gigahertz. This is considered a matter of design engineering based on circuit design and configuration, such as components selected, and thus would have been obvious to a person having ordinary skill in the art.
Allowable Subject Matter
Claims 10-13, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 10-12, prior art(s) does not disclose a first tail switch transistor controllable by a first switch signal and coupled between the first differential pair of transistors and ground; and a second tail switch transistor controllable by a second switch signal and coupled between the second differential pair of transistors and ground, wherein the second switch signal is a complement of the first switch signal.
Regarding claim 13, prior art(s) does not disclose a third fixed and non-switchable capacitively neutralized differential pair of transistors coupled in parallel with the first and second differential pairs of transistors.
Regarding claim 18, prior art(s) does not disclose the second switch circuit further comprises a high- impedance resistor coupled between the first non-control terminal of the sixth transistor and ground.
Regarding claim 19, prior art(s) does not disclose eighth and ninth transistors, each with respective control terminals, first non-control terminals, and second non-control terminals; a control terminal of the eighth transistors coupled to the first differential input, and a control terminal of the ninth transistor coupled to the second differential input; a first non-control terminal of the eighth transistor coupled to the first differential output, and a first non-control terminal of the ninth transistor coupled to the second differential output; respective second non-control terminals of the eighth and ninth transistors coupled to ground; a first capacitor coupled between the control terminal of the eighth transistor and the second differential output; and a second capacitor coupled between the control terminal of the ninth transistor and the first differential output.
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Wyse et al. (8,903,342), which is considered to be the closest prior art to the subject matters of claimed, discloses two differential stages that are cross-connected. However, it lack the switching circuit as claimed.
Wu et al. (11,791,777) is also closed. However, it lacks the connections between terminals of transistors claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JESSICA HAN can be reached on (571) 272-2078. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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