DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 3/12/2026 have been fully considered but they are not persuasive. Applicant’s arguments (Applicant’s Remarks pages 10-11) assert that the prior art of record (US 20230351962 A1 (Song et al), and US 20210217833 A1 (Yu et al) in view of US 20200411629 A1 (Kim et al) do not teach or suggest the amended limitations “a fourth electrode in a same layer as the third electrode”. The Examiner respectfully disagrees, as in the case of Song, FIG. 13 illustrates layer 160 which has both the claimed third and fourth electrodes located in it. In the case of Yu in view of Kim, a layer formed of multiple non-labeled interlayer insulation layers is also found to provide a same layer that both the claimed third and fourth electrodes are located in.
New claims 25-26 are also found obvious based on the disclosure of Song in view of US 20240081099 A1 (Bae et al), US 20240040863 A1 (Lee et al), and US 20210119177 A1 (Bang et al).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 6-10, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US patent publication US 20230351962 A1 (Song et al hereinafter Song).
Regarding claim 1, Song discloses a display device (display device 1, illustrated in FIG. 1 and having cross-sectional views in FIGS. 8-17 and the pixel circuit of FIG. 6 ¶ [0048, 0050-0059]), comprising: a substrate (FIGS. 12-17 each illustrate substrate SUB ¶ [0108]) having a display area (FIG. 1, active area AAR ¶ [0085]) and a non-display area (FIG. 1, non-active area NAR ¶ [0085]); an emitting element (FIGS. 6 and 13, light emitting element EL ¶ [0085]) connected to a gate line (FIG. 6, scan line GWLk ¶ [0125]) and a data line (FIG. 6, data line DLj crosses scan line GWLk in the display area AAR ¶ [0125]) crossing the gate line in the display area, the emitting element including a first electrode (FIG. 13, pixel electrode 171 ¶ [0137]), an emitting layer (FIG. 13, organic light emitting layer 172 ¶ [0231]) and a second electrode (FIG. 13, common electrode 173 ¶ [0137]); a first thin film transistor (FIG. 6, driving transistor DT ¶ [0134]) supplying a driving current to the emitting element according to a data voltage of the data line (FIG. 6, data line DLj provides a data voltage to the driving transistor ¶ [0139]), the first thin film transistor including a first semiconductor layer (FIG. 12, channel layer DTA ¶ [0185]), a first source electrode and a first drain electrode (FIG. 12, first and second electrodes DTS and DTD are the source and drain electrodes of driving transistor DT ¶ [0147, 0185]; it is known in the art that transistors have a source and a drain electrode at either end of a channel layer); a second thin film transistor (FIG. 6, first transistor T1 ¶ [0134]) controlling an operation of the first thin film transistor according to a gate voltage of the gate line (FIG. 6, first transistor T1 switches on and off based on the gate voltage of scan line GWLk to control an operation of driving transistor DT ¶ [0190]), the second thin film transistor including a second semiconductor layer (FIG. 12, channel layer A1 ¶ [0190]); a third thin film transistor (FIG. 6, second transistor T2 ¶ [0134]) controlling an operation of the first thin film transistor by sensing a threshold voltage of the first thin film transistor (FIG. 6, second transistor T2 controls an operation of driving transistor DT by sensing the threshold voltage ¶ [0140]), the third thin film transistor including a third semiconductor layer (FIG. 13, channel layer A2 ¶ [0192]); a third electrode (FIG. 13, anode connection electrode ANDE ¶ [0182]) electrically connecting the first electrode and one of the first and second thin film transistors (FIGS. 6 and 13, anode connection electrode ANDE connects pixel electrode 171 to the pixel circuit, which electrically connects to driving transistor DT when transistor T5 is switched on); and a fourth electrode (FIG. 13, shielding electrode SHE ¶ [0179]) in a same layer (FIG. 13, both anode connection electrode ANDE and shielding electrode SHE are located in first organic layer 160, with ANDE in an upper part and SHE in a lower part ¶ [0230]) as the third electrode.
Regarding claim 2, Song discloses the limitations of claim 1 as detailed above and further discloses that the first thin film transistor further includes a first upper gate electrode (FIG. 12, driving transistor DT includes upper gate DTG above channel layer DTA ¶ [0185]) on the first semiconductor layer, wherein the second thin film transistor further includes a second upper gate electrode (FIG. 12, first transistor T1 includes upper gate electrode G1 on channel layer A1 ¶ [0190]) on the second semiconductor layer, and wherein the third thin film transistor further includes a third upper gate electrode (FIG. 13, second transistor T2 includes upper gate electrode G2 on channel layer A1 ¶ [0192]) on the third semiconductor layer.
Regarding claim 6, Song discloses the limitations of claim 1 as detailed above and further discloses that at least one of the first semiconductor layer, the second semiconductor layer, or the third semiconductor layer includes an oxide semiconductor material (the active layer of second transistor T2, which includes the claimed third semiconductor layer, may be an oxide semiconductor¶ [0148]).
Regarding claim 7, Song discloses the limitations of claim 1 as detailed above and further discloses that the third semiconductor layer includes an oxide semiconductor material (the active layer of second transistor T2, which includes the claimed third semiconductor layer, may be an oxide semiconductor¶ [0148]).
Regarding claim 8, Song discloses the limitations of claim 1 as detailed above and further discloses that the fourth electrode is separated from the third electrode (FIG. 13, shielding electrode SHE and connection electrode ANDE are spaced apart from each other), and wherein the fourth electrode extends (FIGS. 8-13, shielding electrode SHE extends over the sub-pixel in a top-down view) across an entire display area (an ‘entire display area’ may be considered an area of one sub-pixel of the device, e.g. that which is illustrated in FIGS. 8-13), excluding a region where the third electrode resides and a gap between the third electrode and the fourth electrode (FIGS. 8-13, the claimed ‘gap’ fills out any area not occupied by either connection electrode ANDE or shielding electrode SHE).
Regarding claim 9, Song discloses the limitations of claim 1 as detailed above and further discloses that the third electrode or the fourth electrode includes a plurality of layers (FIG. 13, connection electrode ANDE is formed as part of second data metal layer DTL2, and that metal layer may be formed of a multilayer i.e. a plurality of layers ¶ [0248]).
Regarding claim 10, Song discloses the limitations of claim 9 as detailed above and further discloses that a bottom layer of the plurality of layers includes a low reflection material (suggested materials for second data metal layer DTL2 molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (N1), and copper (Cu) are low reflection materials ¶ [0248], and forming a bottom layer of the multilayer of any of those listed materials satisfies the claimed limitation; present application claim 13 clearly indicates that such materials are considered low reflection).
Regarding claim 17, Song discloses the limitations of claim 1 as detailed above and further discloses an encapsulation part (FIGS. 12-13, encapsulation layer TFE is formed on emitting element EL ¶ [0229, 0276]) on the emitting element, the encapsulation part including a first encapsulating layer, a second encapsulating layer and a third encapsulating layer (FIGS. 12-13 encapsulation layer TFE may have its upper third, middle third, and lower third designated as first, second and third encapsulation layers); and a touch part (FIG. 3, window WDL is disposed on encapsulation TFE and may be touched by a user ¶ [0109]) on the encapsulation part.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20230351962 A1 (Song et al hereinafter Song) as applied to claim 2 above, and further in view of US 20210020722 A1 (Liu).
Song discloses the limitations of claim 2 as detailed above, but does not explicitly teach that a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the first semiconductor layer and the first upper gate electrode, and wherein a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the second semiconductor layer and the second upper gate electrode. A distance between the semiconductor layers and their corresponding upper gate electrodes is determined by the thickness of first gate insulating layer 131 (FIG. 12, DT and T1 share layer 131 ¶ [0230]) in the case of the first and second semiconductor layers and upper gate electrodes, and by the thickness of second gate insulating layer 132 (FIG. 13, T2 has layer 132 as its gate insulating layer ¶ [0230]) in the case of the third semiconductor layer and upper gate electrode.
However, it is known in the art that the gate insulation thickness (the thickness of layers 131 and 132 of Song FIGS. 12-13) is a result-effective variable in view of Liu, which teaches that gate insulation thickness influences power consumption and parasitic capacitance in a display device in a manner that can be adjusted depending on the desired device characteristics (¶ [0007]); the gate dielectric thickness and correspondingly the claimed distances between the respective semiconductor layers and upper gate electrodes are therefore result-effective variables.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the distances between the respective semiconductor layers and upper gate electrodes since those distances have been identified as result-effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a set of distances wherein a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the first semiconductor layer and the first upper gate electrode, and wherein a distance between the third semiconductor layer and the third upper gate electrode is greater than a distance between the second semiconductor layer and the second upper gate electrode, in order to achieve a desired balance of reduced power consumption and parasitic capacitance for each respective transistor.
Claims 4 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Song as applied to claim 2 above, and further in view of US patent publication US 20210168937 A1 (Guo et al hereinafter Guo).
Regarding claim 4, Song discloses the limitations of claim 2 as detailed above, but does not further disclose that the first thin film transistor further includes a first lower gate electrode under the first semiconductor layer, wherein the second thin film transistor further includes a second lower gate electrode under the second semiconductor layer, and wherein the third thin film transistor further includes a third lower gate electrode under the third semiconductor layer.
However, it would be obvious to try (MPEP 2143 I (E)) further including those features in view of Guo, which teaches that a display device (the device of FIG. 9) includes a thin film transistor (FIG. 9, thin film transistor 111 ¶ [0077]) which may interchangeably be configured as a top-gate, bottom-gate, or dual-gate TFT (¶ [0077]). When the channel is arranged with a horizontal alignment as in the devices of Song and Guo, there are three possibilities for the gate’s configuration: top-gate, bottom-gate, or dual-gate, and Guo has demonstrated that any of those three configurations are suitable for use in a pixel circuit. The choice between top-gate, bottom-gate, and dual-gate also affects the performance characteristics of the device, which a person of ordinary skill in the art would recognize as a factor to consider when configuring the gates of the transistors.
Song and Guo both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Song in view of Guo to employ dual-gate transistors for the first, second and third thin film transistors such that the first thin film transistor further includes a first lower gate electrode under the first semiconductor layer, wherein the second thin film transistor further includes a second lower gate electrode under the second semiconductor layer, and wherein the third thin film transistor further includes a third lower gate electrode under the third semiconductor layer, in order to configure dual-gate transistors in the device of Song to achieve desirable performance characteristics.
Regarding claim 11, Song in view of Guo discloses the limitations of claim 4 as detailed above and further discloses that the second thin film transistor further includes a second source electrode (Song FIG. 12, first electrode S1 and third connection electrode BE3 form a source electrode of transistor T1 ¶ [0147, 0187, 0191]) and a second drain electrode (Song FIG. 12, second electrode D1 forms a source electrode of transistor T1 ¶ [0147, 0190]), wherein the third thin film transistor further includes a third source electrode (Song FIG. 13, first electrode S2 and first connection electrode BE1 form a source electrode for transistor T2 ¶ [0147, 0182, 0192]) and a third drain electrode (Song FIG. 13, second electrode D2 ¶ [0147, 0186]), and wherein the first source electrode, the second source electrode, the third source electrode, the first drain electrode, the second drain electrode, or the third drain electrode comprises a plurality of layers (Song FIG. 13, first electrode S2 and first connection electrode BE1 are a plurality of layers that form the source electrode of transistor T2).
Regarding claim 12, Song in view of Guo discloses the limitations of claim 11 as detailed above and further discloses that a top layer of the plurality of layers includes a low reflection material (first connection electrode BE1, the top layer of the source electrode of transistor T2, is formed as part of first data metal layer DTL1 and includes a low reflection material ¶ [0246]).
Regarding claim 13, Song in view of Guo discloses the limitations of claim 12 as detailed above and further discloses that the low reflection material comprises at least one of molybdenum (Mo), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), chromium (Cr), tungsten (W), vanadium (V), niobium (Nb), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), silver (Ag), aluminum (Al) and gold (Au) and an alloy thereof (a layer or multilayer of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) are all taught as options of materials for first connection electrode BE1 by Song ¶ [0246]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Guo as applied to claim 4 above, and further in view of Liu.
Song in view of Guo discloses the limitations of claim 4 as detailed above but does not explicitly disclose that a distance between the second semiconductor layer and the second lower gate electrode is greater than a distance between the first semiconductor layer and the first lower gate electrode, and wherein a distance between the third semiconductor layer and the third lower gate electrode is greater than a distance between the first semiconductor layer and the first lower gate electrode.
However, it is known in the art that the gate insulation is a result-effective variable in view of Liu, which teaches that gate insulation thickness influences power consumption and parasitic capacitance in a display device in a manner that can be adjusted depending on the desired device characteristics (¶ [0007]); the gate dielectric thickness and correspondingly the claimed distances between the respective semiconductor layers and lower gate electrodes are therefore result-effective variables.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the distances between the respective semiconductor layers and lower gate electrodes since those distances have been identified as result- effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a set of distances wherein a distance between the second semiconductor layer and the second lower gate electrode is greater than a distance between the first semiconductor layer and the first lower gate electrode, and wherein a distance between the third semiconductor layer and the third lower gate electrode is greater than a distance between the first semiconductor layer and the first lower gate electrode, in order to achieve a desired balance of reduced power consumption and parasitic capacitance for each respective transistor.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Guo as applied to claim 11 above, and further in view of US patent publication US 20210193785 A1 (Kim et al hereinafter Kim 2).
Song in view of Guo discloses the limitations of claim 11 as detailed above, but does not further disclose that the first source electrode is electrically connected to the first lower gate electrode, that configuration of those elements relative to each other not being explicitly suggested by the combination of references.
However, Kim 2 discloses a display device (the device of FIGS. 6-7 ¶ [0020-0021]) comprising a driving transistor (FIGS. 6-7, driving transistor DR ¶ [0096]) wherein the first source electrode is electrically connected to the first lower gate electrode (FIG. 6, the electrical signal from ELVDD reaches both the lower gate and the source of the driving transistor in pixel circuit 110a), in order to initialize both the lower gate and source of the driving transistor to the driving voltage ELVDD (¶ [0145]).
Song, Guo, and Kim 2 pertain to the field of display devices. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Song in view of Guo further in view of Kim 2 such that the first source electrode is electrically connected to the first lower gate electrode, in order to initialize both the lower gate and source of the driving transistor to the driving voltage of the pixel circuit.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Song as applied to claim 1 above, and further in view of US patent publications US 20200411629 A1 (Kim et al hereinafter Kim) and US 20210119177 A1 (Bang et al hereinafter Bang).
Regarding claim 15, Song discloses the limitations of claim 1 as detailed above and further discloses a line part (FIGS. 2 and 6, scan write line GWLk is a line part that extends into the non-display area to reach scan driver 23 ¶ [0093, 0102, 0125]) and a gate driving unit (FIG. 2, scan driver 23 is a gate driving unit in the non-display area ¶ [0093]) in the non-display area. Song does not further disclose a dam layer or a fourth thin film transistor in the gate driving unit, the fourth thin film transistor applying the gate voltage to the second thin film transistor and including a fourth semiconductor layer; Song does teach that the scan write line GWLk applies the gate voltage to the second thin film transistor, but does not illustrate the structure of the scan driver (gate driving unit) in detail.
However, Kim discloses a display device (the device of FIG. 2, ¶ [0018]) which comprises a dam layer (FIG. 2, DAM ¶ [0058]), which is noted to suppress a diffusion of the encapsulation material (¶ [0058]).
Song and Kim both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Song in view of Kim to include a dam layer, in order to suppress a diffusion of the encapsulation material in the device of Song.
Song in view of Kim do not explicitly disclose a fourth thin film transistor in the gate driving unit, the fourth thin film transistor applying the gate voltage to the second thin film transistor and including a fourth semiconductor layer.
However, Bang discloses a display device (FIG. 6, display panel 100 ¶ [0092]) comprising a gate driving unit (FIG. 6, scan driver SD ¶ [0072, 0092]) comprising a fourth thin film transistor (scan driver SD includes thin film transistors ¶ [0092]) in the gate driving unit, the fourth thin film transistor applying the gate voltage to a second thin film transistor (the transistors in scan driver SD provide gate voltages to the gates in the pixel circuit ¶ [0072, 0092, 0104]) and including a fourth semiconductor layer (the thin film transistors include semiconductor layers ¶ [0092]). A person of ordinary skill in the art before the effective filing date of the claimed invention would recognize that including the fourth transistor in the gate driving unit would allow the gate driving unit to provide a signal to the signal line that controls the gate of the second thin film transistor.
Song, Kim, and Bang all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Song in view of Kim further in view of Bang to include a fourth thin film transistor in the gate driving unit, the fourth thin film transistor applying the gate voltage to the second thin film transistor and including a fourth semiconductor layer, in order to configure the gate driving unit to control the gate of the second thin film transistor.
Regarding claim 16, Song in view of Kim and Bang discloses the limitations of claim 15 as detailed above, but did not explicitly disclose that the fourth semiconductor layer includes a polycrystalline semiconductor material, suitable materials specifically for the fourth semiconductor layer not being explicitly listed out. However, Bang does disclose that the semiconductor layers of the transistors in the display area may include a polycrystalline semiconductor material (FIG. 8, active layer 121 may include polycrystalline silicon or low-temperature polycrystalline silicon ¶ [0135]). Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Song in view of Kim and Bang further in view of Bang such that the fourth semiconductor layer includes a polycrystalline semiconductor material, in order to provide a suitable semiconducting material for the fourth thin film transistor in the gate driving unit, taking into consideration materials costs and changing market conditions.
Claims 18-24 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20210217833 A1 (Yu et al hereinafter Yu) in view of Kim.
Regarding claim 18, Yu discloses a display device, comprising: a substrate (FIG. 8, substrate 10 ¶ [0030]); a thin film transistor (FIG. 8, first transistor T1 on substrate 10 ¶ [0030]) on the substrate, the thin film transistor including: a semiconductor layer (FIG. 8, first active layer w1 ¶ [0030]) including oxide semiconductor, and a source electrode (FIG. 8, first source electrode s1 ¶ [0030]) and a drain electrode (FIG. 8, second drain electrode d2 ¶ [0036]), the source electrode and drain electrode above the semiconductor layer (FIG. 8, both electrodes s1 and d2 are above active layer w1); a light emitting element (FIG. 8, light emitting element 30 located above first transistor T1 ¶ [0030]) on the thin film transistor, wherein the light emitting element includes a first electrode (FIG. 8, first electrode 31 ¶ [0031], excluding the portion that extends into first via 41), an emitting layer (FIG. 8, light emitting layer 32 ¶ [0031]), and a second electrode (FIG. 8, second electrode 33 ¶ [0031]); a third electrode (FIG. 8, first drain electrode d1 and the portion of first electrode 31 that extends into first via 41 ¶ [0030-0031]) between the thin film transistor and the light emitting element on a planarizing layer (FIG. 8, the unlabeled fourth layer above substrate 10 is a planarizing layer, MPEP 2125 I; for further context, an analogous layer in FIG. 14 is designated first planarization layer 64 ¶ [0064]), wherein the third electrode electrically connects the first electrode to one of the source electrode or the drain electrode of the thin film transistor (FIG. 8, first drain electrode d1 and the portion of first electrode 31 in first via 41 electrically connects the rest of first electrode 31 to second drain electrode d2 of first transistor T1 ¶ [0047]); and a fourth electrode in a same layer as the third electrode (FIG. 8, a layer formed of unlabeled third, fourth, and fifth layers above substrate 10 is a same layer that both light shielding layer 50 and first drain electrode d1 are formed in ¶ [0035]), wherein the fourth electrode overlaps the semiconductor layer in a first direction (FIG. 8, a vertical direction), and at least a portion of the fourth electrode is spaced apart from the third electrode (FIG. 8, there is a gap between light shielding layer 50 and the portion of first electrode 31 that is located in first via 41).
Yu does not disclose the semiconductor layer including oxide semiconductor (in Yu, the semiconductor layer is suggested to be formed of a silicon material ¶ [0051]). However, Kim discloses a display device (the device of FIG. 2, ¶ [0018]) wherein a thin film transistor (FIG. 2, thin film transistor TFT ¶ [0043]) includes a semiconductor layer (FIG. 2, semiconductor layer 140A ¶ [0043]) wherein the semiconductor layer may be formed of an oxide semiconductor (¶ [0046]; the option of forming it of silicon is also contemplated), and Kim further teaches that oxide semiconductors have a large band gap and low off-current, which enables a short on-time and a long off-time, and that it may be applied in a switching transistor or a driving transistor, depending on the characteristics of the display (¶ [0076]).
Yu and Kim both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Yu in view of Kim wherein the semiconductor layer including oxide semiconductor, in order to provide a known alternative material of the semiconductor layer which has a large band gap and low off-current, which enables a short on-time and a long off-time, which may be found beneficial depending on the characteristics of the display as suggested by Kim.
Regarding claim 19, Yu in view of Kim discloses the limitations of claim 18 as detailed above, and further discloses that the fourth electrode is configured to block at least a portion of light incident to the fourth electrode from reaching the semiconductor layer (Yu FIG. 8, light shielding layer 50 blocks incident light coming from the direction above the light shielding layer and first active layer w1 ¶ [0035, 0061]).
Regarding claim 20, Yu in view of Kim discloses the limitations of claim 18 as detailed above, and further discloses that the fourth electrode includes a plurality of layers (Yu FIG. 8, light shielding layer 50 is formed of the same material as first source electrode s1, which may be “a three-layer structure formed by titanium, aluminum, and titanium” ¶ [0065]), and a bottom layer of the plurality of layers is a low reflection material layer configured to absorb at least a portion of light reflected to the low reflection material layer (a titanium sub-layer of light shielding layer 50 may be the bottom layer and absorb at least a portion of light; as present application’s claim 23 indicates, either titanium or aluminum are suitable materials for absorbing at least a portion of reflected light).
Regarding claim 21, Yu in view of Kim discloses the limitations of claim 18 as detailed above, and further discloses that the third electrode includes a plurality of layers (Yu FIG. 8, first drain electrode d1 and the portion of first electrode 31 in first via 41 form a plurality of layers of the third electrode), and a bottom layer of the plurality of layers is a low reflection material layer configured to absorb at least a portion of light reflected to the low reflection material layer (first drain electrode d1, formed of molybdenum ¶ [0037], is a bottom layer of the third electrode; as present application’s claim 23 indicates, molybdenum is a suitable material for absorbing at least a portion of reflected light).
Regarding claim 22, Yu in view of Kim discloses the limitations of claim 18 as detailed above, and further discloses that the source electrode or the drain electrode includes a plurality of layers (first source electrode s1 may be “a three-layer structure formed by titanium, aluminum, and titanium” Yu ¶ [0065]), a top layer of the plurality of layers is a low reflection material layer configured to absorb at least a portion of light reflected from a bottom surface of the fourth electrode to the low reflection material layer (a titanium sub-layer of first source electrode s1 may be the top layer and absorb at least a portion of light; as present application’s claim 23 indicates, either titanium or aluminum are suitable materials for absorbing at least a portion of reflected light).
Regarding claim 23, Yu in view of Kim discloses the limitations of claim 20 as detailed above, and further discloses that the low reflection material layer comprises at least one of molybdenum (Mo), titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), chromium (Cr), tungsten (W), vanadium (V), niobium (Nb), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), silver (Ag), aluminum (Al) and gold (Au) and an alloy thereof (light shielding layer 50 includes both titanium and aluminum, Yu ¶ [0065]).
Regarding claim 24, Yu in view of Kim discloses the limitations of claim 18 as detailed above, and further discloses that the substrate includes a pixel area (FIG. 8, the region overlapped by light emitting element 30 is a pixel area), but Yu only illustrates the pixel area of one pixel; it is not explicitly described that the pixel area includes a plurality of thin film transistors, the plurality of thin film transistors including the thin film transistor, each of the plurality of thin film transistors includes a semiconductor layer including oxide semiconductor, and the fourth electrode extends across to overlap the semiconductor layers of the plurality of thin film transistors.
However, Yu FIG. 15 illustrates a plurality of pixels having an overall pixel area drawn up as the plurality of light-emitting elements whose projections are indicated by dashed lines (FIG. 15, light emitting elements 30/30Y, ¶ [0060]), where FIG. 15 is a top view of the embodiment of FIG. 14. However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Yu in view of Kim as applied to claim 18 in view of FIG. 15 of Yu such that the pixel area includes a plurality of thin film transistors (Yu FIGS. 8 and 15, each light emitting element 30 has a transistor T1 disposed under it), the plurality of thin film transistors including the thin film transistor (Yu FIG. 8, the transistor T1 illustrated in that figure is one of the transistors of the plurality formed in view of FIG. 15), each of the plurality of thin film transistors includes a semiconductor layer including oxide semiconductor (Yu in view of Kim ¶ [0046, 0076], active layer w1 may be formed of oxide semiconductor), and the fourth electrode extends across to overlap the semiconductor layers of the plurality of thin film transistors (Yu FIGS. 8 and 15, light shielding layer 50 extends over and overlaps the active layers w1 of the transistors T1), since doing so would multiplicatively increase the device’s light emission capacity, and would require no more than a mere duplication of parts (which has been found to be obvious unless a new an unexpected result is produced, MPEP 2144.04 VI. B).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Song as applied to claim 1 above, and further in view of US patent publications US 20240081099 A1 (Bae et al hereinafter Bae) and US 20240040863 A1 (Lee et al hereinafter Lee).
Song discloses the limitations of claim 1 as detailed above and further discloses that the first thin film transistor further includes a first upper gate electrode (FIG. 12, drive transistor DT has upper gate electrode DTG on channel layer DTA ¶ [0185]) on the first semiconductor layer and the second thin film transistor further includes a second upper gate electrode (FIG. 12, transistor T1 has gate electrode G1 on channel layer A1 ¶ [0190]) on the second semiconductor layer. Song does not further disclose a first lower gate electrode under the first semiconductor layer and a second lower gate electrode under the second semiconductor layer, wherein the first lower gate electrode is electrically connected to the first source electrode, and wherein the second lower gate electrode is electrically connected to the second upper gate electrode.
However, Bae discloses a display device (the device of FIG. 3) wherein a first thin film transistor (FIG. 3, driving transistor T2 ¶ [0047], which is analogous in function to the driving transistor of Song) includes a first upper gate electrode (FIG. 3, second gate electrode 155b ¶ [0066]) on a first semiconductor layer (FIG. 3, second semiconductor layer 136b ¶ [0062]) and a first lower gate electrode (FIG. 3, blocking layer 160 functions as a lower gate electrode under semiconductor layer 136b ¶ [0052]) under the first semiconductor layer, wherein the first lower gate electrode is electrically connected to the first source electrode (FIG. 3, source electrode 161b electrically connects to blocking layer 160 ¶ [0073]). Bae also teaches that since the first lower gate electrode receives the driving voltage, it prevents deterioration of display quality due to unnecessary parasitic capacitance (¶ [0068]).
Song and Bae both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Song in view of Bae to include a first lower gate electrode under the first semiconductor layer, wherein the first lower gate electrode is electrically connected to the first source electrode, in order to provide a blocking layer that overlaps the semiconductor layer which also prevents deterioration of display quality due to unnecessary parasitic capacitance.
Song in view of Bae do not further disclose a second lower gate electrode under the second semiconductor layer wherein the second lower gate electrode is electrically connected to the second upper gate electrode.
However, Lee discloses a display device (the device of FIGS. 1-4 ¶ [0037-0039]) which includes a second thin film transistor (FIG. 4, compensation transistor T3 ¶ [0101]) comprising a second lower gate electrode (FIG. 4, transistor T3 includes both a top and a bottom gate ¶ [0122]) under a second semiconductor layer (transistor T3 includes a semiconductor layer ¶ [0122]) wherein the second lower gate electrode is electrically connected to a second upper gate electrode (FIG. 4, the top and bottom gates of transistor T3 are electrically connected ¶ [0122]). Lee also teaches that having a top and bottom gate configuration at the second thin film transistor allows the metal gates to reflect or absorb incoming external light which might otherwise have interfered with the semiconductor layer’s operation (¶ [0122]).
Song, Bae, and Lee all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Song in view of Bae further in view of Lee to include a second lower gate electrode under the second semiconductor layer wherein the second lower gate electrode is electrically connected to the second upper gate electrode, in order to allows the bottom gate to reflect or absorb incoming external light to prevent interference with the semiconductor layer’s operation.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Bae and Lee as applied to claim 25 above, and further in view of Bang.
Song in view of Bae and Lee disclose the limitations of claim 25 as detailed above, but they do not further disclose a fourth thin film transistor applying the gate voltage to the second thin film transistor, wherein the fourth thin film transistor includes a fourth semiconductor layer and a fourth gate electrode on the fourth semiconductor layer, and wherein the second lower gate electrode and the fourth gate electrode are disposed in a same layer as each other.
However, Bang discloses a display device (FIG. 6, display panel 100 ¶ [0092]) comprising a gate driving unit (FIG. 6, scan driver SD ¶ [0072, 0092]) comprising a fourth thin film transistor (scan driver SD includes thin film transistors ¶ [0092]) in the gate driving unit, the fourth thin film transistor applying the gate voltage to a second thin film transistor (the transistors in scan driver SD provide gate voltages to the gates in the pixel circuit ¶ [0072, 0092, 0104]), wherein the fourth thin film transistor includes a fourth semiconductor layer (the thin film transistors include semiconductor layers ¶ [0092]) and a fourth gate electrode (the thin film transistors include gate electrodes ¶ [0092]). While Bang did not explicitly state that the fourth gate electrode was on the fourth semiconductor layer (a statement of whether the fourth thin film transistor is top-gate or bottom-gate not directly set forth), a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to do so in view of Bang FIG. 8, which illustrates that a transistor (FIG. 8, thin film transistor 120 ¶ [0132]) in the TFT layer (FIG. 8, TFTL ¶ [0132]) has a top-gate configuration wherein the gate electrode (FIG. 8, gate electrode 122 ¶ [0134]) is on the semiconductor layer (FIG. 8, active layer 121 ¶ [0134]), in order to configure the fourth transistor in the scan driver region to apply the gate voltage to the second thin film transistor.
Regarding the limitation “wherein the second lower gate electrode and the fourth gate electrode are disposed in a same layer as each other”, Bang illustrates that the “TFT layer” (FIG. 8, TFTL ¶ [0132]) may contain all of the transistor elements in itself. A person of ordinary skill in the art before the effective filing date of the claimed invention would have therefore found it obvious to designate an overall “TFT layer” in the context of the device of Song in view of Bae, Lee, and Bang such that the second lower gate electrode and the fourth gate electrode are disposed in a same layer as each other, in order to set forth a subsection of the device wherein all transistor elements are located.
Song, Bae, Lee, and Bang all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Song in view of Bae and Lee further in view of Bang to include a fourth thin film transistor applying the gate voltage to the second thin film transistor, wherein the fourth thin film transistor includes a fourth semiconductor layer and a fourth gate electrode on the fourth semiconductor layer, and wherein the second lower gate electrode and the fourth gate electrode are disposed in a same layer as each other, in order to configure the fourth transistor in the scan driver region to apply the gate voltage to the second thin film transistor.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publication US 20260033171 A1 (similar pixel circuit, light blocking member 71 in same layer 182 with connection electrode 74) and US patents US 12593577 B2, US 12557477 B2, US 12548513 B2, and US 12550518 B2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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