Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art (in the claims, the first instance of all acronyms, e.g. GAA and CFET, should be spelled out for clarity).
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 20040252572 (BECKER) in view of US 20210005243 A1 (BAE).
With respect to claim 1, US 20040252572 (BECKER) teaches an apparatus [method and circuit for reducing power consumption (Abstract; Fig. 4 and Fig. 6; Par. 0032)], comprising: a plurality of bitcells each having a bit memory cell (bmc) including first and second complementary bit nodes
(a plurality of memory cells, each memory cell having a bit line and a complement bit line) [Par. 0015-0016],
a first bitline switch to couple the first bit node to a first bitline, and a second bitline switch to couple the second bit node to a second bitline
(first n-channel transistor coupled between the charge share line and the bit line and a second n-channel transistor is coupled between the charge share line and the complement bit, i.e., when either charge sharing transistor 22 or 24 turns on, the charge on bit line or bit line bar will be shared with the charge on charge share line 21 (Fig. 7; Par. 0031-0033]; and
charge sharing circuitry coupled between the first and second bitlines to share charge between the bitlines after a write operation and prior to a next read operation
[charge sharing circuit line charge share circuit to couple a charge share line which is coupled to one of the bit line and the bit line complement during the write operation, and decoupling the bit line from the charge share line after (Par. 0031-0034).
BECKER fails to specifically teach the charge sharing circuitry to share charge between the bitlines prior to a next read operation. However, BAE teaches
semiconductor memory device is provided, the semiconductor memory device including a first memory cell connected to a bit line; a second memory cell connected to a complementary bit line, a first isolation transistor connected between the bit line and a sensing bit line, and having a gate configured to receive an isolation signal, a second isolation transistor connected between the complementary bit line and a complementary sensing bit line, and having a gate configured to receive the isolation signal [Par. 0006-0008; Par. 0034-0038] charge sharing occurring between the memory cell bitlines, the bit line BL and the complementary bit line BLB, and between the memory cell and the sensing bit line SABL and the complementary sensing bit line SABLB [Par. 0068] isolation signal ISO to temporally inactivate in response to the writing command WR , a first isolation portion and the second isolation portion may temporally disconnect the bit line BL from the sensing bit line SABL and may connect the bit line BL to the sensing bit line SABL again and may temporally disconnect the complementary bit line BLB from the complementary sensing bit line SABLB and may connect the complementary bit line BLB to the complementary sensing bit line SABLB again, in response to the isolation signal ISO, thereby temporally disconnecting the sense amplifier [Par. 0040-0041].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to combine the shared charge feature for reducing power consumption, as taught by BECKER the bitlines prior to a next read operation, as taught by BAE, in order to improve an operational speed of a semiconductor memory device, such that the semiconductor memory device write the data in a data writing operation prior to asserting read word line, as taught by BAE [Par. 0007].
With respect to claim 2, reciting the apparatus, wherein the memory bit cells each include an equal number of P and N type transistors BECKER teaches n-channel transistor coupled between the charge share line and the bit line and coupled between the charge share line and the complement bit line [BECKER’s Par. 0015-0016]; BAE teaches transistor circuits forming data input and output lines having gates configured to receive the column selection signal and a sense amplifier connected between the sensing bit line and the complementary sensing bit line [BAE’s Par. 0043-0048; Par. 0079-0083].
Neither BECKER nor BAE teaches the memory bit cells each include an equal number of P and N type transistors. However, this features is well known in the applicable art, as evidence in:
1) Applicant’s disclosure describing typical contemporary integrated circuit designs implement numerous complementary FET (CFET) technology implementations which balance between P and N type transistors [Fig. 1 and Par. 0016],
2) ASENOV (US 11894049 B1), featuring technology relate to a CFET SRAM cell utilizing 8 transistors (8T) where one unique aspect of a CFET is that in an exemplary CFET cell, an equal number of transistors are typically fabricated [Col. 3, Lines 11-18]. One of ordinary skill in the art at the time the invention was filed would use the combination of BECKER and BAE and additionally use 8 transistors CFET SRAM of ASENOV in order to achieve improvements in writability and improvements in readability while maintaining stability [Col. 3, Lines 26-31]; and
3) US 20060194567 (KELLY et al) suggesting symmetrically stacked wherein each transistor grouping comprises an equal number of stacked transistors [Par. 0068-0069]. One of ordinary skill in the art at the time the invention was filed would use the combination of BECKER and BAE and additionally use the symmetrical stacked transistor in order to permit alternatively enabling and disabling selective pairs of transistor groupings [Par. 0050].
With respect to claim 3, reciting: the apparatus, wherein the bitline switches are pass gates formed from a pair of N and P type transistors (BAE teaches transistor circuits forming data input and output lines having gates configured for charge sharing [BAE’s Par. 0043-0048; Par. 0079-0083].
Neither BECKER nor BAE teaches the bitline switches are pass gates formed from a pair of N and P type transistors. However, this features is well known in the applicable art, as evidence in:
1) Applicant’s disclosure describing typical contemporary integrated circuit designs implement numerous complementary FET (CFET) technology implementations which balance between P and N type transistors [Fig. 1 and Par. 0016],
2) ASENOV (US 11894049 B1), featuring technology relate to a CFET SRAM cell utilizing 8 transistors (8T) where one unique aspect of a CFET is that in an exemplary CFET cell, an equal number of transistors are typically fabricated [Col. 3, Lines 11-18]. One of ordinary skill in the art at the time the invention was filed would use the combination of BECKER and BAE and additionally use 8 transistors CFET SRAM of ASENOV in order to achieve improvements in writability and improvements in readability while maintaining stability [Col. 3, Lines 26-31]; and
3) US 20060194567 (KELLY et al) suggesting symmetrically stacked wherein each transistor grouping comprises an equal number of stacked transistors [Par. 0068-0069]. One of ordinary skill in the art at the time the invention was filed would use the combination of BECKER and BAE and additionally use the symmetrical stacked transistor in order to permit alternatively enabling and disabling selective pairs of transistor groupings [Par. 0050].
With respect to claim 7, BECKER and BAE, combined teach the apparatus, further comprising a memory array having a plurality of memory slices each having bitcells and charge sharing circuitry (memory array comprised of a plurality of memory cells, bit lines coupled to each memory cell in the memory array and used to read and write data into the cell coupled through charge share control circuitry) [BECKER’s Abstract; Par. 0032-0034].
With respect to claim 8, BECKER and BAE, combined teach the apparatus, wherein the memory array further comprises a block of cache memory (memory array comprised of a plurality of memory cells for read and write data through charge share control circuitry) [BECKER’s Par. 0032-0034].
With respect to claim 9, BECKER and BAE, combined teach the apparatus, wherein the memory slices comprise multiple sections of bitcells and charge sharing circuits coupled to the bitlines, which are local bitlines, the local bitlines being coupled to global bitlines to provide output data from the read operation (input and output gate circuit to include read data latches storing data of a pair of bit lines selected by a column selection signal, and a writing driver for writing data in the memory cell array) [BAE’s Par. 0023-0025]
(semiconductor memory for write data read out data by sensing between a pair of bit lines, the pair of data input and output lines being for electrically connect and disconnecting the pair of bit lines from the sense amplifier) [BAE’s Par. 0023-0025; Par. 0007-0008].
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 20040252572 (BECKER) in view of US 20210005243 A1 (BAE) and further in view of US 20210065784 A1 (BRACERAS et al).
With respect to claim 4, BECKER and BAE, combined teach charge sharing line equalizes the charge on the selected bit line and the charge share line and reduces the voltage differential that must be swung to write data into the cell (Abstract; Par. 0017]. Neither BECKER nor BAE the apparatus wherein the write operation includes a differential write to the first and second bitlines. However, BRACERAS teaches an eight transistor (8T) bitcell using a differential bitline port for write operation [Par. 0049-0050; Par. 0020-0022]. Therefore, it would have been obvious to one having ordinary skill on the art before the effective filing date of the instant application to include, into BECKER and BAE combined elements, differential write to the first and second bitlines as taught by BRACERAS, in order to synchronize the ports, therefore amplifying the differential between the true data line DLT and complement data line DLC., as taught by BRACERAS [Par. 0049].
With respect to claim 5, BECKER, BAE, and BRACERAS, combined, teach the apparatus, wherein the read operation is a single-ended read from one of the bitlines
(multi-port memory including a multiple transistor bitcell single ended read port) [BRACERAS’ Abstract; PAR. 0005-0006; Par. 0020];
(input and output gate circuit to include read data latches storing data of a pair of bit lines selected by a column selection signal, and a writing driver for writing data in the memory cell array 110] BAE’s Par. 0023-0025].
With respect to claim 6, BECKER, BAE, and BRACERAS, combined teach the apparatus, wherein the read operation is a single-ended read from the first bitline from a selected one of the bitcells and a single-ended read from the second bitline from a selected different one of the bitcells
(multi-port memory including a multiple transistor bitcell single ended read port) [BRACERAS’ Abstract; PAR. 0005-0006; Par. 0020]
(charge sharing transistor pulling down control signal (normally high) going to low and turning off transistor during a write operation and, when turned on, the charge on bit line or bit line bar will be shared with the charge on charge share line) [BECKER’s Par. 0032-0034].
Claims 10-25 are rejected under 35 U.S.C. 103 as being unpatentable over US 20120224440 A1 (BATRA) in view of US 20210005243 A1 (BAE).
US 20120224440 A1 (BATRA) with respect to claims 10 and 17, an integrated circuit having a memory array (a memory device, a bitline write voltage is applied to a first bitline), comprising: a plurality of memory slices each (wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline) [Par. 0013-0015]; and charge sharing circuitry controllably coupled between the bitlines to turn on and share charge between the bitlines for a period of time after a write operation has sufficiently completed and then to turn off and decouple them from each other prior to a read operation (first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline during a first time interval; connected the second bit line for a predetermined time after electrically connecting the first bitline and the second bitline, and the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline) [Abstract; Par. 0013-0015].
BATRA teaches that the charge of a first bitline that has been used for writing data to a first memory cell is partially transferred to a second bitline that is used for writing data to a second memory cell in a subsequent memory access cycle [Par. 0021]; but fails to specifically teach the memory slices each including complementary bitlines. However, BAE teaches charge sharing occurring between the memory cell and the bit line BL and the complementary bit line BLB, and between the memory cell and the sensing bit line SABL and the complementary sensing bit line SABLB; where in a time interval, data transmitted to the data input and output line and the complementary data input and output line IOB through the writing may be transmitted to the bit line BL and the complementary bit line BLB via selection transistors CS1 and CS2 of a first a selection portion and the second selection portion, where, in this case, the bit line BL and the complementary bit line BLB may be disconnected from the sense amplifier by being disconnected from the sensing bit line SABL and the complementary sensing bit line SABLB connected to the sense amplifier, i.e., an isolation transistors IS1 and IS2 may be placed in an off-state by the isolation signal ISO transited to a low level in response to the writing command WR, and accordingly, the bit line BL and the complementary bit line BLB may be disconnected from the sensing bit line SABL and the complementary sensing bit line SABLB [Par. 0051-0058; Par. 0074; Par. 0082-00074; Par. 0007-0008].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to combine the shared charge feature for reducing power consumption, as taught by BATRA, the slices each including complementary bitlines bit, the lines written to prior to a next read operation, as taught by BAE, in order to improve an operational speed of a semiconductor memory device, such that the semiconductor memory device write the data in a data writing operation selecting corresponding word line WL transited to a high level in response to an active command read command, as taught by BAE [Par. 0051-0058].
With respect to claims 11 and 18, BATRA and BAE, combined teach integrated circuit, wherein the charge sharing circuitry comprises a first switch that is controlled off of a write select signal to turn on when the write is completing (isolation transistors turned off during a first time interval and turned on during a second time interval, connecting the complementary bit line BLB to the sensing bit line SABL or disconnecting the complementary bit line BLB from the sensing bit line SABL) [BAE’s Par. 0063-0065; Par. 0057-0060].
With respect to claims 12 and 19, BATRA and BAE, combined teach integrated circuit, wherein the charge sharing circuitry comprises a second switch in series with the first switch to turn off upon the end of the period of time after the first switch has turned on
(charge recycling end signal applied to the bitline charge control circuit switched to off and the transistor to electrically disconnect the bitline from the bitline connection line) [BATRA’s Par. 0077-0080]
(transistors turned off during a first time interval and turned on during a second time interval) [BAE’s Par. 0063-0065].
With respect to claims 13 and 20, BATRA and BAE, combined teach integrated circuit, wherein the second switch is controlled by a signal that is a delay of the write select signal
(pass gates used for charge sharing with charge generated internally to the memory device using fixed inverter delays) [BATRA’s Par. 0099-0100).
With respect to claims 14-16 and 21-23, reciting integrated circuit, wherein each slice includes a plurality of 8T bitcells coupled to the bitlines; integrated circuit, wherein the 8T bitcells each comprise four N-type devices and four P-type devices; the P and N type devices are formed from a GAA CFET process (pass gates can be used for charge sharing) BECKER teaches n-channel transistor coupled between the charge share line and the bit line and coupled between the charge share line and the complement bit line [BECKER’s Par. 0015-0016]; BAE teaches transistor circuits forming data input and output lines having gates configured to receive the column selection signal and a sense amplifier connected between the sensing bit line and the complementary sensing bit line [BAE’s Par. 0043-0048; Par. 0079-0083].
Neither BECKER nor BAE teaches each slice includes a plurality of 8T bitcells coupled to the bitlines; integrated circuit, wherein the 8T bitcells each comprise four N-type devices and four P-type devices; the P and N type devices are formed from a GAA CFET process. However, this features is well known in the applicable art, as evidence in:
1) Applicant’s disclosure describing typical contemporary integrated circuit designs implement numerous complementary FET (CFET) technology implementations which balance between P and N type transistors [Fig. 1 and Par. 0016],
2) ASENOV (US 11894049 B1), featuring technology relate to a CFET SRAM cell utilizing 8 transistors (8T) where one unique aspect of a CFET is that in an exemplary CFET cell, an equal number of transistors are typically fabricated [Col. 3, Lines 11-18]. One of ordinary skill in the art at the time the invention was filed would use the combination of BECKER and BAE and additionally use 8 transistors CFET SRAM of ASENOV in order to achieve improvements in writability and improvements in readability while maintaining stability [Col. 3, Lines 26-31]; and
3) US 20060194567 (KELLY et al) suggesting symmetrically stacked wherein each transistor grouping comprises an equal number of stacked transistors [Par. 0068-0069]. One of ordinary skill in the art at the time the invention was filed would use the combination of BECKER and BAE and additionally use the symmetrical stacked transistor in order to permit alternatively enabling and disabling selective pairs of transistor groupings [Par. 0050].
With respect to claim 24, BATRA and BAE, combined teach integrated circuit, wherein the processor is formed on multiple chiplets within a system on package having chiplets formed from different semiconductor processes
input and output gate circuit to include read data latches storing data of a pair of bit lines selected by a column selection signal, and a writing driver for writing data in the memory cell array) [BAE’s Par. 0023-0025]
(semiconductor memory for write data read out data by sensing between a pair of bit lines, the pair of data input and output lines being for electrically connect and disconnecting the pair of bit lines from the sense amplifier) [BAE’s Par. 0023-0025; Par. 0007-0008].
With respect to claim 25, BATRA and BAE, combined teach integrated circuit, wherein the processor has a graphics processing unit comprising at least some of the memory slices
(semiconductor memory device being graphics double data rate including a plurality of memory cells connected a pair of bit lines BAE’s Par. 0021-0023];
(processing circuitry to include semiconductor memory device BATRA’s Par. 0104-0106)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210343330 A1 JUNG ) teaching second memory cell connected to a complementary bit line, a first isolation transistor connected between the bit line and a sensing bit line, and having a gate configured to receive an isolation signal, a second isolation transistor connected between the complementary bit line and a complementary sensing bit line, and having a gate configured to receive the isolation signal.
US 20200365226 A1 (RYU et al) teaching semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder, the bit-line switch connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block, the block switch connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block.
US 20210005243 A1 (BAE) teaching semiconductor memory device including a plurality of memory cells connected a pair of bit lines, a column selection circuit, and a sense amplifier, wherein: when the semiconductor memory device is in a data writing operation, the column selection circuit electrically connects a pair of data input and output lines to the pair of bit lines during a first time interval and a second time interval, consecutively arranged, and the sense amplifier electrically disconnects from the pair of bit lines during the first time interval, and senses and amplifies a voltage difference between the pair of bit lines during the second time interval.
US 20090231939 A1 (HSU et al) teaching circuit and method for a sense amplifier for sensing the charge stored by a memory, the memory cell coupled to a bit line, a complementary bit line and a differential sense amplifier coupled to the bit line and the complementary bit line, a control signal coupled a reference voltage to the complementary bit line.
WO 2022272184 A1 (BANERGIARIGIT et al) teaching circuit having a storing data in an array of memory bit cells (200) that are arranged as a set of rows and columns, where a portion of the rows is connected to a read bit line and not connected to another bit line, the data stored in a memory bit cell being conveyed to the former bit line through an asymmetrical read access circuit, in response to receiving an indication of a read operation targeting a row of the portion comprising the bit cell.
US 8929153 B1 (CHABA et al) teaching memory (102) having several bit cells (110,112) arranged in a row and a first read word line is connected to a first subset of the bit cells; a second read word line is connected to a second subset of bit cells, in which the first and second subsets are located in the same row of bit cells; a first charging circuit is configured to pre-charge read bit lines of first subset prior to asserting first read word line; a second charging circuit is configured to pre-charge read bit lines of second subset prior to asserting the second read word line.
US 11894049 B1 (ASENOV) teaches memory cell comprises a pair of cross-coupled inverters as a storage element; the memory cell comprises a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node. A first complementary transmission gate includes a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line. A second complementary transmission gate includes a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line.
US 8,929,153 (GULATI et al) teaching memory comprising: a plurality of bit cells arranged in a row wherein each of the plurality of bit cells has a write port and a read port; a first read word line connected to a first subset of the plurality of bit cells; a second read word line connected to a second subset of the plurality of bit cells wherein write word line connected to the plurality of bit cells pre-charged during write operation where the write word line (WWL) may be asserted, which can cause data values to be stored in the bit cells corresponding to the row that corresponds to the address received by control circuit prior to asserting read word line, such that, when a read enable signal is received by the address decoder and word line drivers, the address decoder and word line drivers may assert the read word line that corresponds to the address received by the control circuit.
US 9,030,893 (10. An integrated circuit having a memory array, comprising: a plurality of memory slices each including: complementary bitlines; and charge sharing circuitry controllably coupled between the bitlines to turn on and share charge between the bitlines for a period of time after a write operation has sufficiently completed ( when performing said write operation, connects one of said first bitline and said second bitline to said ground line for charge sharing between said one of said first and said second bitline) and then to turn off and decouple them from each other prior to a read operation (subsequently connects said one of said first bitline and said second bitline to ground, and maintains the other of said first bitline and said second bitline at said precharge voltage).
(during a write mode of operation for the memory cell in which one of a local write bitline and a local write bitline bar for the memory cell is asserted to a logic high state while a remaining one of the local write bitline and the local write bitline bar is maintained at a logic low state, coupling the charged local power supply node and the charged memory cell capacitor to the asserted one of the local write bitline and the local write bitline bar to share charge between the memory cell supply capacitor and the asserted one of the local write bitline and the local write bitline bar so that a voltage for the local power supply node and the asserted one of the local write bitline and the local write bitline bar temporarily drops below the power supply voltage VddM
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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