DETAILED ACTION
Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2021/0042146 A1 to Fleming et al. in view of U.S. Pub. No. 2018/0373633 A1 to Herdrich et al.
As to claim 1, Fleming teaches a processor, comprising:
a plurality of cores (one or more hardware cores such as core 119/plurality of cores), each core of the plurality of cores to provide at least one logical processor of a plurality of logical processors (first logical processor/second logical processor/per logical processor (e.g., thread)) (“…In some embodiments, this is enforced through one or more machine state registers (MSRs) that specifies the active RMID of a logical processor. FIG. 3 illustrates an embodiment of these registers. In this example, a per logical processor (e.g., thread) MSR 301 includes fields for class of service (CLOS) 303 and RMID 305…These MSRs are hardware components of a processor that are accessible to a logical processor such as a thread, as illustrated by logical processor 109. Writing to this MSR changes the active RMID of the logical processor from an old value to a new value and the same with CLOS. In this example, RMID 113 and CLOS 115 are shown as separate entities in the logical processor, but as noted above in FIG. 3, they may be fields in a single register. The logical processor 109 also includes a mechanism (such as one or more registers or cache memory) to store a state of the logical processor 109. Typically, there are more than one logical processors 109, 117 that are executed on one or more hardware cores such as core 119. Not shown is a credit accounting mechanism of the core which, in some embodiments, is per logical processor (RMID)…A processor comprising: a plurality of cores, a first core of the plurality of cores comprising multi-threaded execution circuitry to simultaneously execute instructions, the multi-threaded execution circuitry to provide a first logical processor and a second logical processor…” paragraphs 0023/0024/Claim 1);
a first plurality of registers (MSRs), each register of the first plurality of registers to associate a class of service (CLOS) value with a corresponding logical processor of the plurality of logical processors (“…These MSRs are hardware components of a processor that are accessible to a logical processor such as a thread, as illustrated by logical processor 109. Writing to this MSR changes the active RMID of the logical processor from an old value to a new value and the same with CLOS…resource management circuitry to assign a first resource management identifier (RMID) value and a first class of service (CLOS) value to the first logical processor” paragraph 0024/claim 1); and
a first control register (first model-specific register (MSR)) of a first logical processor of the plurality of logical processors to be configured with a reserved CLOS value (first CLOS value) associated with a trusted control structure (first logical processor) (“…a first model-specific register (MSR) to store control data related to execution of the first logical processor, the control data comprising the first RMID value and the first CLOS value, wherein the first MSR is to store the first RMID value in a first field and to store the first CLOS value in a second field…” claim 1);
Fleming does not explicitly teaches a second plurality of registers, each register of the second plurality of registers to indicate a portion of a shared resource to be allocated to a corresponding CLOS value,
resource reservation circuitry configurable by secure firmware or software to indicate a reserved portion of the shared resource associated with the reserved CLOS value, and
enforcement circuitry to limit access to the reserved portion of the shared resource to threads or logical processors associated with the reserved CLOS value.
Herdrich teaches a second plurality of registers (Set of Model-Specific Registers (MSRs)), each register of the second plurality of registers to indicate a portion of a shared resource to be allocated to a corresponding CLOS value (a mask value 0x00FF is stored in the MSR at offset CLOS[1]) (“…In some embodiments, a set of model-specific registers (MSRs) 430 is implemented or utilized to serve as a CLOS-to-control-mechanism mapping table for storing the mapping of CLOS tags to control mechanisms. In one embodiment, the control mechanisms comprise of different way masks. Similar to the mapping of requestor to RMID/CLOS tags illustrated in FIGS. 3A and 3B, the CLOS-to-control-mechanism mapping table may utilize a direct-mapping scheme or an indirect-mapping scheme. FIG. 5 illustrates a logical view of an embodiment of a directly mapped CLOS-to-control-mechanism mapping table, with way masks serving as the control mechanism. According to the embodiment, each CLOS tag is to indicate a position in a MSR in which a corresponding way mask is stored. For instance, the CLOS tag may indicate an offset into a particular MSR. As illustrated in FIG. 5, a mask value 0x00FF is stored in the MSR at offset CLOS[1]. This mask value (0x00FF) is used by the usage control circuitry 424 to restrict the region of L3 cache that is available for fulfilling resource requests having the “CLOS[1]” tag. To control and adjust the shared resources that are available to each of the CLOS tags, the OS/VMM 404, or the software running there on, may simply modify the CLOS-to-way-mask mapping table, by changing the way mask associated with a CLOS tag. In one embodiment, the modifications are made through the QoS software interface 406…” paragraph 0048),
resource reservation circuitry configurable by secure firmware or software to indicate a reserved portion of the shared resource associated with the reserved CLOS value (Usage Control Circuitry 424) (“…According to an embodiment, the usage control circuitry 424 may control and restrict resource usage based on the CLOS tag associated with each resource request. For example, core way mask 426 and agent way mask 428 each includes a mask that can restrict the region or cache lines that new cache lines may be allocated into. When the incoming resource request is tagged with a CLOS tag that is associated with a core requestor, the core way mask 426 is used…Similar to the monitoring mechanism described above, the resource control mechanism can coexist with existing control mechanism(s) that are in place for the processor core 402. In the embodiment illustrated in FIG. 4, the usage control circuitry 424 can restrict the cache resources available to fulfill requests from both the core 402 and the PCIe device, by applying different way masks based on CLOS tag in the request. Requests from the core 402 and the PCIe device 416 may be tagged with CLOS tags from the same CLOS tag pool. Alternatively, separate pools of CLOS tags may be maintained, one for tagging requests from processor cores (e.g., core 402) and one for tagging requests from non-core agents (e.g., PCIe device 416). In addition to separate CLOS pools, separate usage control circuitries may also be implemented. Each of the control circuitries corresponds to a different CLOS pool, as well as a set of one or more way masks. Each of the control circuitries processes only the CLOS tags from its corresponding CLOS pool and applies only its corresponding set of way masks…” paragraphs 0044/0045), and
enforcement circuitry to limit access to the reserved portion of the shared resource to threads or logical processors associated with the reserved CLOS value (restrict resource usage based on a the CLOS tag) (“…According to an embodiment, the usage control circuitry 424 may control and restrict resource usage based on the CLOS tag associated with each resource request. For example, core way mask 426 and agent way mask 428 each includes a mask that can restrict the region or cache lines that new cache lines may be allocated into…Similar to the monitoring mechanism described above, the resource control mechanism can coexist with existing control mechanism(s) that are in place for the processor core 402. In the embodiment illustrated in FIG. 4, the usage control circuitry 424 can restrict the cache resources available to fulfill requests from both the core 402 and the PCIe device, by applying different way masks based on CLOS tag in the request…” paragraphs 0044/0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Fleming with the teaching of Herdrich because the teaching of Herdrich would improve the system of Fleming by providing a technique for restricting access to shared resource to only to those components that own mask lock.
As to claim 2, Herdrich teaches the processor of claim 1 wherein the second plurality of registers comprise a plurality of mask registers, each mask register of the plurality of mask registers to store a mask value indicating a corresponding portion of the shared resource to be allocated to the corresponding CLOS value ((a mask value 0x00FF is stored in the MSR at offset CLOS[1]) (“…In some embodiments, a set of model-specific registers (MSRs) 430 is implemented or utilized to serve as a CLOS-to-control-mechanism mapping table for storing the mapping of CLOS tags to control mechanisms. In one embodiment, the control mechanisms comprise of different way masks. Similar to the mapping of requestor to RMID/CLOS tags illustrated in FIGS. 3A and 3B, the CLOS-to-control-mechanism mapping table may utilize a direct-mapping scheme or an indirect-mapping scheme. FIG. 5 illustrates a logical view of an embodiment of a directly mapped CLOS-to-control-mechanism mapping table, with way masks serving as the control mechanism. According to the embodiment, each CLOS tag is to indicate a position in a MSR in which a corresponding way mask is stored. For instance, the CLOS tag may indicate an offset into a particular MSR. As illustrated in FIG. 5, a mask value 0x00FF is stored in the MSR at offset CLOS[1]. This mask value (0x00FF) is used by the usage control circuitry 424 to restrict the region of L3 cache that is available for fulfilling resource requests having the “CLOS[1]” tag. To control and adjust the shared resources that are available to each of the CLOS tags, the OS/VMM 404, or the software running there on, may simply modify the CLOS-to-way-mask mapping table, by changing the way mask associated with a CLOS tag. In one embodiment, the modifications are made through the QoS software interface 406…” paragraph 0048),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Fleming with the teaching of Herdrich because the teaching of Herdrich would improve the system of Fleming by providing a technique for restricting access to shared resource to only to those components that own mask lock.
As to claim 3, Herdrich teaches the processor of claim 2 wherein a first register of the second plurality of registers associated with the reserved CLOS value is to store a first mask value to indicate a portion of the reserved portion of the shared resource allocated to the reserved CLOS value ((a mask value 0x00FF is stored in the MSR at offset CLOS[1]) (“…In some embodiments, a set of model-specific registers (MSRs) 430 is implemented or utilized to serve as a CLOS-to-control-mechanism mapping table for storing the mapping of CLOS tags to control mechanisms. In one embodiment, the control mechanisms comprise of different way masks. Similar to the mapping of requestor to RMID/CLOS tags illustrated in FIGS. 3A and 3B, the CLOS-to-control-mechanism mapping table may utilize a direct-mapping scheme or an indirect-mapping scheme. FIG. 5 illustrates a logical view of an embodiment of a directly mapped CLOS-to-control-mechanism mapping table, with way masks serving as the control mechanism. According to the embodiment, each CLOS tag is to indicate a position in a MSR in which a corresponding way mask is stored. For instance, the CLOS tag may indicate an offset into a particular MSR. As illustrated in FIG. 5, a mask value 0x00FF is stored in the MSR at offset CLOS[1]. This mask value (0x00FF) is used by the usage control circuitry 424 to restrict the region of L3 cache that is available for fulfilling resource requests having the “CLOS[1]” tag. To control and adjust the shared resources that are available to each of the CLOS tags, the OS/VMM 404, or the software running there on, may simply modify the CLOS-to-way-mask mapping table, by changing the way mask associated with a CLOS tag. In one embodiment, the modifications are made through the QoS software interface 406…” paragraph 0048),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Fleming with the teaching of Herdrich because the teaching of Herdrich would improve the system of Fleming by providing a technique for restricting access to shared resource to only to those components that own mask lock.
As to claim 4, Herdrich teaches the processor of claim 3 wherein the portion of the reserved portion of the shared resource is to be used to store data shared within a trust domain associated with the reserved CLOS value (restrict resource usage based on a the CLOS tag) (“…According to an embodiment, the usage control circuitry 424 may control and restrict resource usage based on the CLOS tag associated with each resource request. For example, core way mask 426 and agent way mask 428 each includes a mask that can restrict the region or cache lines that new cache lines may be allocated into…Similar to the monitoring mechanism described above, the resource control mechanism can coexist with existing control mechanism(s) that are in place for the processor core 402. In the embodiment illustrated in FIG. 4, the usage control circuitry 424 can restrict the cache resources available to fulfill requests from both the core 402 and the PCIe device, by applying different way masks based on CLOS tag in the request…” paragraphs 0044/0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Fleming with the teaching of Herdrich because the teaching of Herdrich would improve the system of Fleming by providing a technique for restricting access to shared resource to only to those components that own mask lock.
As to claim 5, Herdrich teaches the processor of claim 1 wherein the shared resource comprises a cache and wherein each mask value comprises a plurality of bits corresponding to a plurality of cache ways, wherein a bit of the plurality of bits is to be set to a first value to indicate that a corresponding cache way is allocated to the corresponding CLOS value (a mask value 0x00FF is stored in the MSR at offset CLOS[1]) (“…According to an embodiment, the usage control circuitry 424 may control and restrict resource usage based on the CLOS tag associated with each resource request. For example, core way mask 426 and agent way mask 428 each includes a mask that can restrict the region or cache lines that new cache lines may be allocated into…Similar to the monitoring mechanism described above, the resource control mechanism can coexist with existing control mechanism(s) that are in place for the processor core 402. In the embodiment illustrated in FIG. 4, the usage control circuitry 424 can restrict the cache resources available to fulfill requests from both the core 402 and the PCIe device, by applying different way masks based on CLOS tag in the request…In some embodiments, a set of model-specific registers (MSRs) 430 is implemented or utilized to serve as a CLOS-to-control-mechanism mapping table for storing the mapping of CLOS tags to control mechanisms. In one embodiment, the control mechanisms comprise of different way masks. Similar to the mapping of requestor to RMID/CLOS tags illustrated in FIGS. 3A and 3B, the CLOS-to-control-mechanism mapping table may utilize a direct-mapping scheme or an indirect-mapping scheme. FIG. 5 illustrates a logical view of an embodiment of a directly mapped CLOS-to-control-mechanism mapping table, with way masks serving as the control mechanism. According to the embodiment, each CLOS tag is to indicate a position in a MSR in which a corresponding way mask is stored. For instance, the CLOS tag may indicate an offset into a particular MSR. As illustrated in FIG. 5, a mask value 0x00FF is stored in the MSR at offset CLOS[1]. This mask value (0x00FF) is used by the usage control circuitry 424 to restrict the region of L3 cache that is available for fulfilling resource requests having the “CLOS[1]” tag. To control and adjust the shared resources that are available to each of the CLOS tags, the OS/VMM 404, or the software running there on, may simply modify the CLOS-to-way-mask mapping table, by changing the way mask associated with a CLOS tag. In one embodiment, the modifications are made through the QoS software interface 406…” paragraphs 0044/0045/0048).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Fleming with the teaching of Herdrich because the teaching of Herdrich would improve the system of Fleming by providing a technique for restricting access to shared resource to only to those components that own mask lock.
As to claims 9 and 15, see the rejection of claim 1 above, expect for a machine-readable medium.
Fleming teaches a machine-readable medium (Memory 1240).
As to claims 10 and 16, see the rejection of claim 2 above.
As to claims 11 and 17, see the rejection of claim 3 above.
As to claims 12 and 18, see the rejection of claim 4 above.
As to claims 13 and 19, see the rejection of claim 5 above.
Claims 6, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2021/0042146 A1 to Fleming et al. in view of U.S. Pub. No. 20180373633 A1 to Herdrich et al. as applied to claims 1, 9 and 15 above, and further in view of U.S. Pub. No. 2021/0359955 A1 to Musleh et al.
As to claim 6, Fleming as modified by Herdrich teaches the processor of claim 5 however it is silent with reference to cache management circuitry to manage allocations and evictions of cache lines within the cache, wherein the cache management circuitry is to allocate multiple copies of some cache lines, including first copies of the cache lines in a reserved region of the cache associated with the reserved CLOS value and second copies of the cache lines in one or more non- reserved regions of the cache associated with non-reserved CLOS values.
Musleh teaches cache management circuitry to manage allocations and evictions of cache lines within the cache (Cache Manager 102) (“…FIG. 1 depicts an example system. Various examples of components of network interface device 150 and server 100 (e.g., memory 104 and processors 106) are provided herein with respect at least to FIGS. 11 and 12 respectively. In some examples, cache manager 102 can manage utilization of QP cache 152 to store or evict contexts and/or data associated with one or more QPs as described herein…In some examples, a driver can configure network interface 1250 or a cache manager to allocate cache space for a context and/or identify one or more contexts to evict to make space to store a context, as described herein. For example, configuration can take place using one or more of a configuration file, a register write, or application program interface (API) to turn on or turn off operation of the cache manager to allocate cache space for a context and/or identify one or more contexts to evict to make space to store a context, as described herein…” paragraphs 0017/0086), wherein the cache management circuitry is to allocate multiple copies of some cache lines, including first copies of the cache lines in a reserved region of the cache associated with the reserved CLOS value and second copies of the cache lines in one or more non- reserved regions of the cache associated with non-reserved CLOS values (“…FIG. 6 depicts an example of way or partition sharing. A bit map or bit mask can indicate for a particular CLOS/TC level or RMID value, which specific ways and number of ways of a cache to allocate to store contexts and data associated with the CLOS/TC level or RMID value. As shown, some ways can be exclusively allocated to a particular CLOS/TC level or RMID value. Some ways can be shared among CLOS/TC levels 2 and 4 or different RMID values…” paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Fleming and Herdrich with the teaching of Musleh because the teaching of Musleh would improve the system of Fleming and Herdrich by providing a cache manager for managing utilization of QP cache to store or evict contexts (Musleh paragraph 0017).
As to claims 14 and 20, see the rejection of claim 6 above.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2021/0042146 A1 to Fleming et al. in view of U.S. Pub. No. 20180373633 A1 to Herdrich et al. and further in view of U.S. Pub. No. 20210359955 A1 to Musleh et al. as applied to claim 1 above, and further in view of U.S. Pat. No. 5,517,648 A issued to Bertone et al.
As to claim 7, Fleming as modified by Herdrich and Musleh teaches the processor of claim 6, however it is silent with reference to wherein in response to snoop requests from logical processors associated with a non-reserved CLOS value, the cache management circuitry is to ignore the first copies of the cache lines in the reserved region.
Bertone teaches wherein in response to snoop requests (cache snooping operations) from logical processors associated with a non-reserved CLOS value, the cache management circuitry is to ignore the first copies of the cache lines in the reserved region (“…The convention is as follows: A cache can contain no copy of a cache line; or it can be the Exclusive (meaning only) cache to contain a particular cache line; or, if others also contain a copy, it can be Sharing access to a cache line; or, if the cache line has been altered, it is a Modified cache line and no one else can have it; or, if someone else Modifies their copy, we mark our copy Invalid as if we did not have it, freeing the space for reuse, and sending modified data back to memory…The cache snooping operations are summarized in FIGS. 17 and 18: For a CPU cache, in response to a write into a cache line 270, the local cache snoop logic 270 checks to see if the local copy is marked "Exclusive" at 222; and if so, at 224, it is marked "Modified." Nothing more needs to be done, since no other cache contains a copy. No XA-MP bus address or data cycle is required…At 226, if it is marked "shared," then a "PICL" command is sent out to the other snoop logic units to invalidate other copies of this data that exist in other caches, and again it is marked "Modified". All other copies are marked "Invalid" by their local snoop logic. This takes only a XA-MP bus address cycle and no data cycles…” Col. 28 Ln. 63-67, Col. 29 Ln. 448-60).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Fleming, Herdrich and Musleh with the teaching of Bertone because the teaching of Bertone would improve the system of Fleming, Herdrich and Musleh by providing a sharing mechanism that allows varying number requesters to share access to computing resources.
As to claim 8, Fleming as modified by Herdrich and Musleh teaches the processor of claim 7 however it is silent with reference to wherein in response to snoop requests from logical processors associated with the reserved CLOS value, the cache management circuitry is to ignore the second copies of cache lines in the one or more non-reserved regions of the cache.
Bertone teaches wherein in response to snoop requests (cache snooping operations) from logical processors associated with the reserved CLOS value, the cache management circuitry is to ignore the second copies of cache lines in the one or more non-reserved regions of the cache (“…The convention is as follows: A cache can contain no copy of a cache line; or it can be the Exclusive (meaning only) cache to contain a particular cache line; or, if others also contain a copy, it can be Sharing access to a cache line; or, if the cache line has been altered, it is a Modified cache line and no one else can have it; or, if someone else Modifies their copy, we mark our copy Invalid as if we did not have it, freeing the space for reuse, and sending modified data back to memory… The cache snooping operations are summarized in FIGS. 17 and 18: For a CPU cache, in response to a write into a cache line 270, the local cache snoop logic 270 checks to see if the local copy is marked "Exclusive" at 222; and if so, at 224, it is marked "Modified." Nothing more needs to be done, since no other cache contains a copy. No XA-MP bus address or data cycle is required…At 226, if it is marked "shared," then a "PICL" command is sent out to the other snoop logic units to invalidate other copies of this data that exist in other caches, and again it is marked "Modified". All other copies are marked "Invalid" by their local snoop logic. This takes only a XA-MP bus address cycle and no data cycles…” Col. 28 Ln. 63-67, Col. 29 Ln. 448-60).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Fleming, Herdrich and Musleh with the teaching of Bertone because the teaching of Bertone would improve the system of Fleming, Herdrich and Musleh by providing a locking mechanism for exclusively reserving computing resources
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gilford et al. and directed to "DNA: Dynamic Resource Allocation for Soft Real-Time Multicore Systems".
U.S. Pub. No. 2021/0042228 A1 to Herdrick et al. and shared resource monitoring and control system.
U.S. No. 2020/0012514 A1 to Fleming et al. and directed to systems, methods, and apparatuses for resource monitoring.
U.S. No. 2021/0042228 A1 to Herdrick et al. and directed to controller for locking of selected cache regions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES E ANYA whose telephone number is (571)272-3757. The examiner can normally be reached Mon-Fir. 9-6pm.
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/CHARLES E ANYA/Primary Examiner, Art Unit 2194
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