Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Response to Election/Restriction filed on 6/24/2026.
Claims 1-6, 8-15, and 17-19 are pending for this examination.
Claims 7, 16, and 20 were withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/29/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-15, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Krashinsky (US 9,830,156), herein referred to as Krashinsky ‘156.
Referring to claim 1, Krashinsky ‘156 teaches a processor (see Fig. 2, GPCs 208) comprising:
an instruction unit (see Fig. 3C, warp scheduler and instruction unit 312 that is a part of streaming multiprocessor (SPM) 310 of each GPC 208) to receive a single instruction, multiple thread (SIMT) instruction (see Col. 12, lines 8-37, where a SIMT instruction goes through various pipeline stages within the SPM 310), the SIMT instruction having at least one field to provide at least one value (see Fig. 4B, where instruction 440 includes several fields that provide values needed to execute an instruction), the at least one value to indicate a plurality of threads that are to execute the SIMT instruction (see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and considers a predication register values and instruction predication field in determining threads that do not execute the SIMT instruction to optimize efficiency and reduce the number or cycles for which the SIMT instruction is dispatched); and
a SIMT processor (see Fig. 2, GPCs 208) coupled with the instruction unit (see Fig. 3C, warp scheduler and instruction unit 312 that is a part of streaming multiprocessor (SPM) 310 that is a part of the GPC 208, i.e. coupled with the GPC 208), the SIMT processor to execute the SIMT instruction for each of the plurality of threads (see Col. 6, lines 60-67, Col. 7, lines 1-13).
As to claim 2, Krashinsky ‘156 teaches the processor of claim 1, wherein the at least one value is to indicate the plurality of threads as being only a subset of a plurality of threads configured for the processor (see Col. 12, lines 38-55, where sub-groups of threads can be dispatched in parallel in a temporal SIMT architecture; also see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and not dispatch SIMT instruction for dispatch sub-groups of sequential threads that are inactive according to the active mask).
As to claim 3, Krashinsky ‘156 teaches the processor of claim 1, wherein the at least one value is to indicate the plurality of threads as being only a subset of a plurality of threads initialized to execute code including the SIMT instruction (see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and not dispatch SIMT instruction for dispatch sub-groups of sequential threads that are inactive according to the active mask, i.e. which threads to execute based on the active mask).
As to claim 4, Krashinsky ‘156 teaches the processor of claim 1, wherein the SIMT processor includes a plurality of processing elements initialized to execute a plurality of threads of a parallel thread group concurrently, and wherein the at least one value is to indicate that only a subset of the plurality of processing elements are to execute the SIMT instruction (see Col. 7, lines 39-57; also see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and not dispatch SIMT instruction for dispatch sub-groups of sequential threads that are inactive according to the active mask, i.e. which threads to execute based on the active mask).
As to claim 5, Krashinsky ‘156 teaches the processor of claim 4, wherein the subset is one of only a single thread, only half the plurality of processing elements, only one quarter the plurality of processing elements, or only one eighth the plurality of processing elements (see Col. 12, lines 38-55, wherein dispatch groups can be 4 threads corresponding to four parallel processing pipelines for 32 threads in a thread group, i.e. a quarter).
As to claim 6, Krashinsky ‘156 teaches the processor of claim 4, wherein the plurality of threads of the parallel thread group are a warp or a wavefront (see Col. 7, lines 38-57).
As to claim 8, Krashinsky ‘156 teaches the processor of claim 1, wherein the at least one value is to indicate only a subset of warps initialized to execute code including the SIMT instruction or only a subset of wavefronts initialized to execute code including the SIMT instruction (see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and not dispatch SIMT instruction for dispatch sub-groups of sequential threads that are inactive according to the active mask).
As to claim 9, Krashinsky ‘156 teaches the processor of claim 1, wherein the instruction unit is to receive a second SIMT instruction, the second SIMT instruction having at least one field to provide a source thread identifier and at least one field to provide a source register identifier (see Col. 9, lines 36-47, wherein each thread is assigned a unique thread identifier accessible during its execution, where thread identifiers can be stored in local register files, see Col. 10, lines 46-67; see Col. 12, lines 8-37, where two source operands are used in the SIMT instruction in which operands are stored into a source register).
As to claim 10, Krashinsky ‘156 teaches the processor of claim 9, wherein a processing element of the SIMT processor is to execute the second SIMT instruction for a first thread to receive data from a register that is to be identified by the source register identifier of a second, different thread that is to be identified by the source thread identifier (see Col. 10, lines 46-67, where different lanes can be populated by data for different threads executing the same SIMD / SIMT; see Col. 12, lines 8-37, where two source operands are used in the SIMT instruction in which operands are stored into a source register).
As to claim 11, Krashinsky ‘156 teaches the processor of claim 10, wherein the second SIMT instruction has at least one field to provide a second source thread identifier and at least one field to provide a second source register identifier, and wherein the processing element is to execute the second SIMT instruction for the first thread to receive data from a second register that is to be identified by the second source register identifier of a third, different thread that is to be identified by the second source thread identifier (see Col. 10, lines 46-67, where different lanes can be populated by data for different threads executing the same SIMD / SIMT; see Col. 12, lines 8-37, where two source operands are used in the SIMT instruction in which operands are stored into a source register).
As to claim 12, Krashinsky ‘156 teaches the processor of claim 10, wherein the second SIMT instruction has at least one field to provide a destination thread identifier and at least one field to provide a destination register identifier, and wherein the processing element is to execute the second SIMT instruction for the first thread to store a result in a third register that is to be identified by the destination register identifier in a third, different thread that is to be identified by the destination thread identifier (see Col. 10, lines 46-67, where different lanes can be populated by data for different threads executing the same SIMD / SIMT; see Col. 12, lines 8-37, where a destination operand is used in the SIMT instruction in which operands are stored into a destination register).
Referring to claim 13, Krashinsky ‘156 teaches a method (see Abstract) comprising:
receiving a single instruction, multiple thread (SIMT) instruction (see Col. 12, lines 8-37, where a SIMT instruction goes through various pipeline stages within the SPM 310), the SIMT instruction having at least one field providing at least one value (see Fig. 4B, where instruction 440 includes several fields that provide values needed to execute an instruction), the at least one value indicating a plurality of threads that are to execute the SIMT instruction (see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and considers a predication register values and instruction predication field in determining threads that do not execute the SIMT instruction to optimize efficiency and reduce the number or cycles for which the SIMT instruction is dispatched); and
executing the SIMT instruction for each of the plurality of threads (see Col. 6, lines 60-67, Col. 7, lines 1-13) on a SIMT processor (see Fig. 2, GPCs 208).
As to claim 14, Krashinsky ‘156 teaches the method of claim 13, wherein the at least one value indicates the plurality of threads as being only a subset of a plurality of threads configured and initialized to execute code including the SIMT instruction (see Col. 12, lines 38-55, where sub-groups of threads can be dispatched in parallel in a temporal SIMT architecture; also see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and not dispatch SIMT instruction for dispatch sub-groups of sequential threads that are inactive according to the active mask, i.e. which threads to execute based on the active mask).
As to claim 15, Krashinsky ‘156 teaches the method of claim 13, wherein the at least one value indicates that only a subset of a plurality of processing elements initialized to execute a plurality of threads of a parallel thread group concurrently are to execute the SIMT instruction concurrently (see Col. 7, lines 39-57; also see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and not dispatch SIMT instruction for dispatch sub-groups of sequential threads that are inactive according to the active mask, i.e. which threads to execute based on the active mask).
As to claim 17, Krashinsky ‘156 teaches the method of claim 13, further comprising: receiving a second SIMT instruction, the second SIMT instruction having at least one field providing a source thread identifier and at least one field providing a source register identifier (see Col. 9, lines 36-47, wherein each thread is assigned a unique thread identifier accessible during its execution, where thread identifiers can be stored in local register files, see Col. 10, lines 46-67; see Col. 12, lines 8-37, where two source operands are used in the SIMT instruction in which operands are stored into a source register); and executing the second SIMT instruction with a processing element of a SIMT processor for a first thread to receive data from a register identified by the source register identifier of a second, different thread identified by the source thread identifier (see Col. 10, lines 46-67, where different lanes can be populated by data for different threads executing the same SIMD / SIMT; see Col. 12, lines 8-37, where two source operands are used in the SIMT instruction in which operands are stored into a source register).
Referring to claim 18, Krashinsky ‘156 teaches a system (see Fig. 1, computer system 100) comprising:
a processor (see Fig. 2, GPCs 208) comprising:
an instruction unit (see Fig. 3C, warp scheduler and instruction unit 312 that is a part of streaming multiprocessor (SPM) 310 of each GPC 208) to receive a single instruction, multiple thread (SIMT) instruction (see Col. 12, lines 8-37, where a SIMT instruction goes through various pipeline stages within the SPM 310), the SIMT instruction having at least one field to provide at least one value (see Fig. 4B, where instruction 440 includes several fields that provide values needed to execute an instruction), the at least one value to indicate a plurality of threads that are to execute the SIMT instruction (see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and considers a predication register values and instruction predication field in determining threads that do not execute the SIMT instruction to optimize efficiency and reduce the number or cycles for which the SIMT instruction is dispatched); and
a SIMT processor (see Fig. 2, GPCs 208) coupled with the instruction unit (see Fig. 3C, warp scheduler and instruction unit 312 that is a part of streaming multiprocessor (SPM) 310 that is a part of the GPC 208, i.e. coupled with the GPC 208), the SIMT processor to execute the SIMT instruction for each of the plurality of threads (see Col. 6, lines 60-67, Col. 7, lines 1-13); and
a dynamic random access memory (DRAM) (see Fig. 2, DRAM 220) coupled with the processor (see Fig. 2, wherein DRAMs are coupled to parallel processing unit 202 comprising multiple GPCs 208).
As to claim 19, Krashinsky ‘156 teaches the system of claim 18, wherein the SIMT processor includes a plurality of processing elements initialized to execute a plurality of threads of a parallel thread group concurrently, and wherein the at least one value is to indicate that only a subset of the plurality of processing elements are to execute the SIMT instruction (see Col. 7, lines 39-57; also see Col. 13, lines 36-54, wherein instruction dispatch unit 415 uses active make for thread groups to control which threads execute each SIMT instruction and not dispatch SIMT instruction for dispatch sub-groups of sequential threads that are inactive according to the active mask, i.e. which threads to execute based on the active mask).
Response to Arguments
Applicant’s arguments, mailed 6/24/2026, have been fully considered but they are not deemed to be persuasive.
Applicants have elected to continue with prosecution of claim group I listed in the Election/Restriction sent 4/24/2026 (see Page 1 of Applicant’s argument). Thereby Claims 7, 16, and 20 indicated as claim group II have been withdrawn, and the remaining claims have been examined as set forth above.
In summary, Krashinsky ‘156 teaches the claimed invention as set forth above.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Barik et al. (US 2018/0307980) teaches a multiprocessor system implementing convolution operations that uses parallel graphics processors with SIMT architectures executing SIMT instructions synchronously.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183
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