CTNF 18/213,669 CTNF 91509 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 20180375488 A1 (Sira), in view of US 20130113300 A1 (Zybura) . Regarding Claims 1, 11 and 15 : A system, comprising: a digital-to-analog converter (DAC); a transformer coupled to an output of the DAC, the transformer comprising a first inductor comprising a first plurality of windings; and a second inductor comprising a second plurality of windings, the second inductor configured to inductively couple to the first inductor, a capacitor coupled at a tap point of the second plurality of windings; and an amplifier coupled to an output of the second inductor (Sira: Figs. 1-2, a transmitter matching network configuration that comprises a DAC and a matching network, where the outputs 110 connects to “subsequent circuit/block/device (e.g., a power amplifier)” (e.g., par. 44); a transformer comprises a primary winding L1, and a secondary windings of L2A and L2B, and the L1 and L2A-B are inductively coupled; Figs. 3A-B and par. 54, “the arrangement 300 utilizes adjustable capacitors to perform harmonic tuning and mitigate or prevent generation of the fundamental harmonics” ), Sira does not teach explicitly on a capacitor coupled at a tap point of the second plurality of windings. However, Zybura teaches (Figs. 4A-C and par. 36-43, a capacitor 126 is placed with one terminal on the ground and the other terminal on the tap of windings of the secondary winding ). It would have been obvious for one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Sira with a capacitor coupled at a tap point of the second plurality of windings as further taught by Zybura. The advantage of doing so for “adding a capacitor in parallel with a portion of the secondary inductor creates a harmonic trap (filter), and also efficiently uses the secondary coil (inductor) as a resonating element for a particular harmonic” (Zybura: par. 11). Regarding claim 2, Sire as modified further teaches: The transmitter of claim 1, wherein the one or more windings comprise a first winding, a second winding, a third winding, and a fourth winding (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 3, Sire as modified further teaches: The transmitter of claim 2, wherein the second inductor is coupled to an output port at the first winding (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 4, Sire as modified further teaches: The transmitter of claim 2, wherein the second inductor is coupled to ground at the fourth winding (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 5, Sire as modified further teaches: The transmitter of claim 2, wherein the second winding is coupled between the first winding and the third winding (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 6, Sire as modified further teaches: The transmitter of claim 2, wherein the third winding is coupled between the second winding and the fourth winding (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 7, Sire as modified further teaches: The transmitter of claim 2, wherein the capacitor is coupled at the first terminal to the third winding of the one or more windings (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 8, Sire as modified further teaches: The transmitter of claim 1, wherein the capacitor comprises a harmonic rejection capacitor that is configured to perform harmonic rejection for a second harmonic of an input signal to the transmitter (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 9, Sire as modified further teaches: The transmitter of claim 1, wherein the capacitor comprises a harmonic rejection capacitor that is configured to perform harmonic rejection for a third harmonic of an input signal to the transmitter (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 10, Sire as modified further teaches: The transmitter of claim 1, wherein the capacitor comprises a harmonic rejection capacitor that is configured to perform harmonic rejection for a second harmonic and a third harmonic of an input signal to the transmitter (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements ). Regarding claim 12, Sire as modified further teaches: The transformer of claim 11, wherein the second inductor comprises n windings, and the capacitor is coupled between an nth winding and an n-1 winding of the second inductor at a first terminal of the capacitor and is coupled to ground at a second terminal of the capacitor (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements. It is further noted that without explicitly limiting “n” and “m”, the “n” and “m” can be any digits ). Regarding claim 13, Sire as modified further teaches: The transformer of claim 11, wherein the second inductor comprises n windings, and the capacitor is coupled between an n-1 winding and an n-2 winding of the second inductor at a first terminal of the capacitor and is coupled to ground at a second terminal of the capacitor (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements. It is further noted that without explicitly limiting “n” and “m”, the “n” and “m” can be any digits ). Regarding claim 14, Sire as modified further teaches: The transformer of claim 11, wherein the second inductor comprises n windings starting at an mth winding, and the capacitor is coupled between the mth winding and an m+1 winding of the second inductor at a first terminal of the capacitor and is coupled to ground at a second terminal of the capacitor (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements. It is further noted that without explicitly limiting “n” and “m”, the “n” and “m” can be any digits ). Regarding claim 16, Sire as modified further teaches: The system of claim 15, wherein the capacitor is coupled at a first terminal of the capacitor to a winding at the tap point and coupled at a second terminal of the capacitor to ground (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements. ). Regarding claim 17, Sire as modified further teaches: The system of claim 16, wherein the second plurality of windings comprises n number of windings in between the tap point and the ground, wherein the n number of windings and the capacitor are configured to perform harmonic rejection (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements. It is further noted that without explicitly limiting “n” and “m”, the “n” and “m” can be any digits ). Regarding claim 18, Sire as modified further teaches: The system of claim 17, wherein the n number of windings and the capacitor are configured to perform harmonic rejection for a second harmonic, a third harmonic, or both, of an input signal of the transformer (Zybura: Figs. 4A-C; par. 39-41, multi[le windings of the secondary inductor ; par. 54, “ FIGS. 7A-7D illustrate results for a single additional capacitor (first order topology), specifically for a simulation of a CX40 FL transformer with an additional capacitor tapped at 1/4 and 3/4 of the length of the secondary coil.”, which teaches that harmonic rejection performance varies with tap position and that multiple tap position are available, making selection among them a matter of optimization based on design requirements. It is further noted that without explicitly limiting “n” and “m”, the “n” and “m” can be any digits ). Regarding claim 19, Sire as modified further teaches: The system of claim 15, wherein the first plurality of windings comprises fewer windings than the second plurality of windings (Sira: par. 35 “ The primary winding is a single winding and is generally coupled to the analog input signal 108. The secondary windings include a first secondary winding and a second secondary winding ”). Regarding claim 20, Sire as modified further teaches: The system of claim 15, wherein the first plurality of windings comprises more windings than the second plurality of windings (Sira: Figs. 2-4A-C, primary has few windings than secondary ; Zybura: Figs. 4A-C, primary has equal amount windings with the secondary, where it would be obvious a design variations to a person of ordinary skill to design a configuration with more windings on primary than the secondary ). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHITONG CHEN whose telephone number is (571) 270-1936. The examiner can normally be reached on M-F 9:30am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yuwen Pan can be reached on 571-272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZHITONG CHEN/ Primary Examiner, Art Unit 2649 Application/Control Number: 18/213,669 Page 2 Art Unit: 2649 Application/Control Number: 18/213,669 Page 3 Art Unit: 2649 Application/Control Number: 18/213,669 Page 4 Art Unit: 2649 Application/Control Number: 18/213,669 Page 5 Art Unit: 2649 Application/Control Number: 18/213,669 Page 6 Art Unit: 2649 Application/Control Number: 18/213,669 Page 7 Art Unit: 2649 Application/Control Number: 18/213,669 Page 8 Art Unit: 2649 Application/Control Number: 18/213,669 Page 9 Art Unit: 2649 Application/Control Number: 18/213,669 Page 10 Art Unit: 2649 Application/Control Number: 18/213,669 Page 11 Art Unit: 2649 Application/Control Number: 18/213,669 Page 12 Art Unit: 2649
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