CTNF 18/214,014 CTNF 101497 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings 06-37 AIA The drawings were received on 26 June 2023 . These drawings are acceptable . Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Teraguchi (US 9,484,810 B2; hereinafter “Teraguchi”) . In re claim 1, Teraguchi discloses an apparatus (Figs. 2, 4, 6) comprising: a clock node included in a voltage regulator (Fig. 2) to receive an input clock signal (Sx); a first power switching block (Figs. 4 and 5 are connected in series shown in Fig. 2) included in the voltage regulator, the first power switching block including a first clock generator (BCP) and first switched capacitor circuitry (Cp1-3 and Dp1-4, shown in Fig. 5), the first clock generator including a clock input node to receive the input clock signal (Sx), and clock output nodes to provide first clock signals (Pcka and Pckb) based on the input clock signal (Sx), the first switched capacitor circuitry (Cp1-3 and Dp1-4) including input nodes to receive first control signals (TPcka and TPckb) generated based on the first clock signals; and a second power switching block included in the voltage regulator, the second power switching block, including a second clock generator (BCN) and second switched capacitor circuitry (Cn1-3 and Dn1-4, shown in Fig. 5), the second clock generator including a clock input node to receive the input clock signal (Sx), and clock output nodes to provide second clock signals (Ncka and Nckb) based on the input clock signal, the second switched capacitor circuitry including input nodes to receive second control signals (TNcka and TNckb) generated based on the second clock signals Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or non-obviousness. 07-21-aia AIA Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Teraguchi (US 9,484,810 B2; hereinafter “Teraguchi”) in view of Shen et al. (US 10,574,243 B2; hereinafter “Shen”) . In re claim 7, Teraguchi discloses an apparatus (see rejection above and Figs. 2, 4; 6). Teraguchi does not disclose, further comprising: a processor; and a power controller coupled to the processor, wherein the power controller includes the first power switching block, and the second power switching block. Whereas, Shen discloses a similar apparatus (Figs. 2, 3, 6, 9, 10A-13, 17), further comprising: a processor (2110); and a power controller (2150) coupled to the processor, wherein the power controller includes the first power switching block, and the second power switching block. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Teraguchi such that adding a processor and a power controller as shown by Shen . The selection of adding a processor and a power controller would be a routine matter to the person of ordinary skill to increase control of the apparatus, as taught by Shen , cited above . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 8-20 allowed. 13-03 AIA The following is an examiner’s statement of reasons for allowance: With respect to independent claim 8, Teraguchi (US 9,484,810 B2; hereinafter “Teraguchi”) was found to be the closest prior art. Teraguchi discloses an apparatus (Figs. 2, 4; 6) comprising: a clock node (Sx); a voltage input node and a voltage output node; a first power switching block including a first clock generator coupled to the clock node (Figs. 4 and 5 are connected in series shown in Fig. 2) and first switched capacitor circuitry (Cp1-3 and Dp1-4, shown in Fig. 5) including a first capacitor and first circuits. Teraguchi does not disclose each of the first circuits including a first node coupled to a plate of the first capacitor, and a second node coupled to one of the voltage input node and the voltage output node; and a second power switching block including a second clock generator coupled to the clock node and second switched capacitor circuitry including a second capacitor and second circuits, each of the second circuits including a first node coupled to a plate of the second capacitor and a second node coupled to one of the voltage input node and the voltage output node, wherein: each of the first and second clock generators includes a third circuit and a fourth circuit coupled to the third circuit; a structure of the third circuit is based on a structure of a first selected circuit among the first circuits and the second circuits; and a structure of the fourth circuit is based on a structure of a second selected circuit among the first circuits and second circuits. The other prior art on record does not provide the suggestion to modify Teraguchi to arrive at the claimed invention. Claims 9-17 each depend, directly or indirectly, from claim 2 and therefore are allowable for the same reasons explained above. With respect to independent claim 18, Teraguchi (US 9,484,810 B2; hereinafter “Teraguchi”) was found to be the closest prior art. Teraguchi discloses a method (Figs. 2-6) comprising: generating an input clock signal (Pcka-b or Ncka-b) based on a clock signal (Sx) from an output node of a comparator (Ge) of a voltage regulator; providing the input clock signal (Sx) to a first clock generator (BCP) of a first power switching block of the voltage regulator; providing the input clock signal (Sx) to a second clock generator (BCN) of a second power switching block of the voltage regulator; generating, at the first clock generator, a first clock signal (Pcka-b) based on the input clock signal; generating, at the first clock generator, a second clock signal (Ncka-b) based on the first clock signal. Teraguchi does not disclose wherein the second clock signal at the first clock generator is generated such that a time interval between two closest edges of the first and second clock signals is based on a first voltage at a gate of a first transistor in the first clock generator and a second voltage at a gate of a second transistor in the first clock generator; generating, at the second clock generator, a third clock signal based on the input clock signal; generating, at the second clock generator, a fourth clock signal based on the third clock signal, wherein the fourth clock signal is generated such that a time interval between two closest edges of the third and fourth clock signals at the second clock generator is based on a first voltage at a gate of a first transistor in the second clock generator and a second voltage at a gate of a second transistor in the second clock generator; providing first control signals to switched capacitor circuitry of the first power switching block, wherein a time interval between edges of the first control signals are based on the time interval between two closest edges of the first and second clock signals; and providing the second control signals to switched capacitor circuitry of the second power switching block, wherein a time interval between edges of the second control signals are based on the time interval between two closest edges of the third and fourth clock signals. The other prior art on record does not provide the suggestion to modify Teraguchi to arrive at the claimed invention. Claims 19-20 depend from claim 18 and therefore are allowable for the same reasons explained above . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” 12-151-08 AIA 07-43 12-51-08 Claim s 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: In re claim 2, Teraguchi discloses the apparatus (see rejection above). Teraguchi does not disclose an apparatus wherein the voltage regulator includes: a conductive line coupled to clock node and the first and second power switching blocks; a third power switching block coupled to the conductive line, the third power switching block including a third clock generator and third switched capacitor circuitry, the third clock generator including a clock input node to receive the input clock signal, and clock output nodes to provide third clock signals based on the input clock signal, the third switched capacitor circuitry including input nodes to receive third control signals generated based on the third clock signals; a fourth power switching block coupled to the conductive line, the fourth power switching block including a fourth clock generator and fourth switched capacitor circuitry, the fourth clock generator including a clock input node to receive the input clock signal, and clock output nodes to provide fourth clock signals based on the input clock signal, the fourth switched capacitor circuitry including input nodes to receive fourth control signals generated based on the fourth clock signals; and wherein the first and second power switching blocks are located on a first side of the conductive line, and third and fourth power switching blocks are located on a second side of the conductive line opposite from the first side. The other prior art on record does not provide the suggestion to modify Teraguchi to arrive at the claimed invention. Claim 3 depends from claim 2 and therefore contains allowable subject matter for the same reasons explained above. In re claim 4, Teraguchi discloses an apparatus of (see Claim 1 rejection above (Figs. 2-4), further comprising: buffer circuitry (BCP) including an input node to receive the input clock (Sx), and an output node to provide an additional input clock signal (Pcka-b). Teraguchi does not disclose a third power switching block coupled to the output node of the buffer circuit the third power switching block including a third clock generator and third switched capacitor circuitry, the third clock generator including a clock input node to receive the additional input clock signal, and clock output nodes to provide third clock signals based on the additional input clock signal, the third switched capacitor circuitry including input nodes to receive third control signals generated based on the third clock signals; and a fourth power switching block coupled to the output node of the buffer circuitry, the fourth power switching block including a fourth clock generator and fourth switched capacitor circuitry, the fourth clock generator including a clock input node to receive the additional input clock signal, and clock output nodes to provide fourth clock signals based on the additional input clock signal, the fourth switched capacitor circuitry including input nodes to receive fourth control signals generated based on the fourth clock signals. The other prior art on record does not provide the suggestion to modify Teraguchi to arrive at the claimed invention. In re claim 5, Teraguchi discloses an apparatus (see rejection above and Figs. 2, 4; 6), wherein the voltage regulator includes: a voltage input node (Vd1); a voltage output node (TOUTp or TOUTn), wherein each of the first and second switched capacitor circuitries includes an input node coupled to the voltage input node (Vd1 or GND), and an output node (Vp or Vn) coupled to the voltage output node. Teraguchi does not disclose a comparator including a first input node coupled to a voltage node, a second input to receive a voltage based on an output voltage at the voltage output node; and buffer circuitry including an input node coupled to an output node of the comparator, and an output node coupled to the clock node. The other prior art on record does not provide the suggestion to modify Teraguchi to arrive at the claimed invention. Claim 6 depends from claim 5 and therefore contains allowable subject matter for the same reasons explained above . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure : Garrity. US 8736309 B2 Non-overlapping Clock Generator Circuit And Method Tran et al. US 10847227 B2 Charge Pump For Use In Non-volatile Flash Memory Devices Zhang. EP 4456402 A1 CHARGE PUMP CIRCUIT, POWER MANAGEMENT CIRCUIT, AND TERMINAL Shinohara et al. US 7804794 B2 Power-saving Network Switching Device Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas A Chapa Mills whose telephone number is (571)272-3683. The examiner can normally be reached Mon-Fri 9am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICOLAS ALDEN CHAPA MILLS/ Examiner, Art Unit 2838 /CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838 Application/Control Number: 18/214,014 Page 2 Art Unit: 2838 Application/Control Number: 18/214,014 Page 3 Art Unit: 2838 Application/Control Number: 18/214,014 Page 4 Art Unit: 2838 Application/Control Number: 18/214,014 Page 5 Art Unit: 2838 Application/Control Number: 18/214,014 Page 6 Art Unit: 2838 Application/Control Number: 18/214,014 Page 7 Art Unit: 2838 Application/Control Number: 18/214,014 Page 8 Art Unit: 2838 Application/Control Number: 18/214,014 Page 9 Art Unit: 2838 Application/Control Number: 18/214,014 Page 10 Art Unit: 2838 Application/Control Number: 18/214,014 Page 11 Art Unit: 2838
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