DETAILED ACTION
1. This Office action is in response to the amendment filed on 02/26/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6 Claim(s) 1 - 2, 5, 9 - 12, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2016/0211811 A1 in view of US Pub. No 2022/0200590 A1 ; (hereinafter Koerts et al and Ramond) Both cited in previous office action date 12/02/2025.
Regarding claim 1, Koerts et al [e.g., Figs. 2, 3 and 6] discloses a switching power stage circuit arrangement [e.g., switching unit connected between powerstage control 140 and amplifiers 150], comprising: a half bridge comprising a high side switch and low side switch [e.g., half bridge shown containing high-side and low-side transistors]; and a cycle-by-cycle protection against over-currents circuit [e.g., OCP 130 and PWM] configured to receive a PWM signal [e.g., carrier_p1] and output a cycle-by-cycle protected driving signal for controlling driving of said high side switch and low side switch [e.g., PWM signal generated by POWERSTAGE Control 140 and outputted to switching unit]; wherein said cycle-by- cycle protection against over-currents circuit [e.g., OCP 130 and PWM] is configured to: receive signals indicative of a detected over-current at said high side switch and low side switch [e.g., signals (ocd_ls_p1 and ocd_hd_p2) received by OCP 130 supplied by amplifiers 150 p. 0028 recites "OCP block 130 may also receive four OCD signals from four respective amplifiers 150 within each output driver 110/120. In this way, as described in further detail below, OCP block 130 may both detect an over-current condition and control inversion of signals within each output driver 110/120."]; and output said cycle-by-cycle protected driving signal [e.g., outputs inverted signals (invert_hs_p1 and Invert_ls_p1)], in response to the signals indicative of the detected over-current indicating that current flowing in the turned on high side switch or low side switch crosses a given threshold during a time interval within which the high side switch or low side switch is turned on [e.g., in response to when excessive current event is detected at time 610 -- refer to Fig. 6 for a chart 600 for generation of the ocp_count signals , p's. 0046 - 0047 recites "After the sensor detects an excessive current event at running event position 610, the phase (pwm_carrier, phase 0) gets the detection signal from the sensor at the time 620, marked with the first dashed line. The value of a counter, starting at the rising edge of the pwm-carrier, is stored by a sample and hold technique. This is the ocd_event_position 620. Because the running_event_position 610 is larger than the stored ocd_event_position 620 the output signal should be inverted. After enough time has elapsed to reach time 630 the running_event_position 610 becomes larger than the stored ocd_event_position 620. Thus, this output should also be inverted."], as an inverted PWM signal by turning off the turned on high side switch or low side switch [e.g., outputs inverted (signals invert_hs_p1 and Invert_ls_p1), p. 0039 recites "The pwm_in_p1/2 signals from the PWM have a particular duty cycles that are related to output voltages of the amplifier. When a current is too large, the ocd_hs_p1 signal from the excessive current comparator of outp1 is activated. The powerstage_control circuit then inverts pwm_out_p1 to limit the output current. As a consequence, the pulse width of pwm_out_p1 is now smaller than pwm_in_p1"], and otherwise output said cycle-by-cycle protected driving signal as a not inverted PWM signal [e.g., pwm_out_p1 during normal operation p. 0053 recites "During normal operation, when there is no clipping and no excessive current events occur, the state machine runs through the inner six states as controlled by the pwm_in signal. These six states ensure that the pwm_out signal switches once per pwm-period. This maintains a minimum pulse width. The minimum pulse width may ensure that the output switching frequency remains fixed”]; and wherein said power stage further comprises an anomaly detection circuit [e.g., current limiter 200 -- refer to Fig. 3 for details of current limiter 200 --] configured to receive the signals indicative of the detected over-current [e.g., receives signals ocd_hs_p1 and ocd_ls_p1].
Koerts et al does not disclose switch off both the high side switch and low side switch when an anomaly is detected in a pattern of over-current events indicated by the signals indicative of the detected over-current.
Ramond [e.g., Figs. 3 and 5] teaches switch off both the high side switch and low side switch when an anomaly is detected in a pattern of over-current events indicated by the signals indicative of the detected over-current [e.g., Fault Management 528 received HDETECT and LDETECT and generates fault signal to controller 521 to cease generating CONTROL signal, p. 0031 recites “Fault management circuit 528 receives both HDETECT and LDETECT and responsively forms the fault signal “. It continues on p. 0032 recites “In one embodiment of switched mode power converter 520, controller 521 ceases generating HCONTROL and LCONTROL in response to the fault signal. In this example, controller 521 can refrain from generating HCONTROL and LCONTROL either until an external signal is provided to switched mode power converter 520, switched mode power converter 520 is restarted, or a predetermined time passes.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Koerts et al with switch off both the high side switch and low side switch when an anomaly is detected in a pattern of over-current events indicated by the signals indicative of the detected over-current as suggested by Ramond to disable operation of the transistors during short circuit conditions to avoid damaging the power converter.
Regarding claim 2, Koerts et al discloses the claimed invention except for wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit comprises a previous detected over-current in the turned on high side switch or low side switch and a further detected over-current event within a given time interval in after a same switch as the turned on high side switch or low side switch.
Ramond [e.g., Figs. 3 - 5] teaches wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit [e.g., -- refer to Fig. 3 for timing diagram --, Short-to-ground signal (340)] comprises a previous detected over-current in the turned on high side switch or low side switch [e.g., first Short-to-ground (340) detected at t4, p. 0020 recites “At t4 a short from the source terminal of the transistor to ground occurs, represented by Short-to-Ground going to a logic high state and VSW going to a low voltage amplitude. When the short circuit condition occurs, the drain-to-source voltage drop caused by an increased current flowing across the ON resistance of the transistor causes the voltage at the input of the inverter to rise above its switchpoint and INV activates. The digital processing circuit determines from CONTROL and INV that the short circuit condition occurred during a switching cycle of the gate driver and responsively activates DETECT.”] and a further detected over-current event signaled within a given time interval in a same switch as the turned on high side switch or low side switch [e.g., second Short-to-ground (340) detected within the new switching cycle (t6), p. 0020 recites “At t6, a new switching cycle is initiated, CONTROL is activated, and the gate driver turns on the transistor after a propagation delay. In this example, the short circuit condition persists; therefore, the digital processing circuit reactivates DETECT and the gate driver and transistor are disabled for the remainder of the switching cycle.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Koerts et al with wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit comprises a previous detected over-current in the turned on high side switch or low side switch and a further detected over-current event within a given time interval in after a same switch as the turned on high side switch or low side switch as suggested by Ramond to control and protect the power transistors during short circuit conditions.
Regarding claim 5, Koerts et al discloses the claimed invention except for wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit comprises a previous detected over-current in the turned on high side switch or low side switch and a further detected over-current event in an other of the high-side switch or low side switch within a given time interval after the previous detected over-current event.
Ramond [e.g., Figs. 3 - 5] teaches wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit [e.g., -- refer to Fig. 3 for timing diagram --, Short-to-ground signal (340)] comprises a previous detected over-current in the turned on high side switch or low side switch [e.g., first Short-to-ground (340) detected at t4, p. 0020 recites “At t4 a short from the source terminal of the transistor to ground occurs, represented by Short-to-Ground going to a logic high state and VSW going to a low voltage amplitude. When the short circuit condition occurs, the drain-to-source voltage drop caused by an increased current flowing across the ON resistance of the transistor causes the voltage at the input of the inverter to rise above its switchpoint and INV activates. The digital processing circuit determines from CONTROL and INV that the short circuit condition occurred during a switching cycle of the gate driver and responsively activates DETECT.”] and a further detected over-current event in an other of the high-side switch or low side switch within a given time interval after the previous detected over-current event [e.g., second Short-to-ground (340) detected within the new switching cycle (t6) at either high-side transistor or low-side transistor, p. 0020 recites “At t6, a new switching cycle is initiated, CONTROL is activated, and the gate driver turns on the transistor after a propagation delay. In this example, the short circuit condition persists; therefore, the digital processing circuit reactivates DETECT and the gate driver and transistor are disabled for the remainder of the switching cycle.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Koerts et al with wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit comprises a previous detected over-current in the turned on high side switch or low side switch and a further detected over-current event in an other of the high-side switch or low side switch within a given time interval after the previous detected over-current event as suggested by Ramond to control and protect the power transistors during short circuit conditions.
Regarding claim 9, Koerts et al discloses the claimed invention except for wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit comprises a previous detected over-current in the turned on high side switch or low side switch and a further detected over-current on one of the high side switch or low side switch when the cycle-by-cycle protected driving signal commands said one of the high side switch or low side switch to be turned off.
Ramond [e.g., Figs. 3 - 5] teaches wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit [e.g., -- refer to Fig. 3 for timing diagram --, Short-to-ground signal (340)] comprises a previous detected over-current in the turned on high side switch or low side switch [e.g., first Short-to-ground (340) detected at t4, p. 0020 recites “At t4 a short from the source terminal of the transistor to ground occurs, represented by Short-to-Ground going to a logic high state and VSW going to a low voltage amplitude. When the short circuit condition occurs, the drain-to-source voltage drop caused by an increased current flowing across the ON resistance of the transistor causes the voltage at the input of the inverter to rise above its switchpoint and INV activates. The digital processing circuit determines from CONTROL and INV that the short circuit condition occurred during a switching cycle of the gate driver and responsively activates DETECT.”] and a further detected over-current on one of the high side switch or low side switch when the cycle-by-cycle protected driving signal commands said one of the high side switch or low side switch to be turned off [e.g., second Short-to-ground (340) detected within the new switching cycle (t6) at either high-side transistor or low-side transistor as INV turns off transistor (VSW is 0), p. 0020 recites “At t6, a new switching cycle is initiated, CONTROL is activated, and the gate driver turns on the transistor after a propagation delay. In this example, the short circuit condition persists; therefore, the digital processing circuit reactivates DETECT and the gate driver and transistor are disabled for the remainder of the switching cycle.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Koerts et al with wherein the pattern of over-current events for said anomaly detected by the anomaly detection circuit comprises a previous detected over-current in the turned on high side switch or low side switch and a further detected over-current on one of the high side switch or low side switch when the cycle-by-cycle protected driving signal commands said one of the high side switch or low side switch to be turned off as suggested by Ramond to control and protect the power transistors during short circuit conditions.
Regarding claim 10, Koerts et al [e.g., Figs. 2, 3 and 6] discloses wherein said power stage circuit arrangement is comprised in a class D bridge audio amplifier [e.g., p. 0011 recites " FIG. 2 illustrates a current limiter with the Class D amplifier"].
Regarding claim 11, Koerts et al [e.g., Figs. 2, 3 and 6] discloses a method for switching a power stage circuit arrangement [e.g., switching unit connected between powerstage control 140 and amplifiers 150], comprising: generating a cycle-by-cycle protected driving signal in response to a PWM signal [e.g., PWM signal generated by POWERSTAGE Control 140 and outputted to switching unit]; driving a half bridge comprising a high side switch and low side switch [e.g., driving half bridge shown containing high-side and low side transistors] in response to the cycle-by-cycle protected driving signal [e.g., outputs inverted (signals invert_hs_p1 and Invert_ls_p1), p. 0039 recites "The pwm_in_p1/2 signals from the PWM have a particular duty cycles that are related to output voltages of the amplifier. When a current is too large, the ocd_hs_p1 signal from the excessive current comparator of outp1 is activated. The powerstage_control circuit then inverts pwm_out_p1 to limit the output current. As a consequence, the pulse width of pwm_out_p1 is now smaller than pwm_in_p1"]; detecting over-currents at said high side switch and low side switch and generating signals indicative of the over-currents detected at said high side switch and low side switch [e.g., signals (ocd_ls_p1 and ocd_hd_p2) received by OCP 130 supplied by amplifiers 150 p. 0028 recites "OCP block 130 may also receive four OCD signals from four respective amplifiers 150 within each output driver 110/120. In this way, as described in further detail below, OCP block 130 may both detect an over-current condition and control inversion of signals within each output driver 110/120."], outputting said cycle-by-cycle protected driving signal [e.g., outputs inverted signals (invert_hs_p1 and Invert_Is_p1)], in response to the signals indicative of the detected over-current indicating that current flowing in the turned on high side switch or low side switch crosses a given threshold during a time interval within which the high side switch or low side switch is turned on [e.g., in response to when excessive current event is detected at time 610-- refer to Fig. 6 for a chart 600 for generation of the ocp_count signals , p's. 0046 - 0047 recites "After the sensor detects an excessive current event at running event position 610, the phase (pwm_carrier, phase 0) gets the detection signal from the sensor at the time 620, marked with the first dashed line. The value of a counter, starting at the rising edge of the pwm-carrier, is stored by a sample and hold technique. This is the ocd_event_position 620. Because the running_event_position 610 is larger than the stored ocd_event_position 620 the output signal should be inverted. After enough time has elapsed to reach time 630 the running_event_position 610 becomes larger than the stored ocd_event_position 620. Thus, this output should also be inverted."], as an inverted PWM signal by turning off the turned on high side switch or low side switch [e.g., outputs inverted (signals invert_hs_p1 and Invert_ls_p1), p. 0039 recites "The pwm_in_p1/2 signals from the PWM have a particular duty cycles that are related to output voltages of the amplifier. When a current is too large, the ocd_hs_p1 signal from the excessive current comparator of outp1 is activated. The powerstage_control circuit then inverts pwm_out_p1 to limit the output current. As a consequence, the pulse width of pwm_out_p1 is now smaller than pwm_in_p1"], and otherwise outputting said cycle-by-cycle protected driving signal as a not inverted PWM signal [e.g., pwm_out_p1 during normal operation p. 0053 recites "During normal operation, when there is no clipping and no excessive current events occur, the state machine runs through the inner six states as controlled by the pwm_in signal. These six states ensure that the pwm_out signal switches once per pwm-period. This maintains a minimum pulse width. The minimum pulse width may ensure that the output switching frequency remains fixed”]; performing an anomaly detection on the basis of at least the signals indicative of the detected over-current [e.g., detect excessive current event via signal ocd_hs_p1 and ocd_ls_p1)].
Koerts et al does not disclose switching off both the high side switch and low side switch when the anomaly is detected in a pattern of over-current events in the signals indicative of the detected over-current.
Ramond [e.g., Figs. 3 and 5] teaches switching off both the high side switch and low side switch when the anomaly is detected in a pattern of over-current events in the signals indicative of the detected over-current [e.g., Fault Management 528 received HDETECT and LDETECT and generates fault signal to controller 521 to cease generating CONTROL signal, p. 0031 recites “Fault management circuit 528 receives both HDETECT and LDETECT and responsively forms the fault signal “. It continues on p. 0032 recites “In one embodiment of switched mode power converter 520, controller 521 ceases generating HCONTROL and LCONTROL in response to the fault signal. In this example, controller 521 can refrain from generating HCONTROL and LCONTROL either until an external signal is provided to switched mode power converter 520, switched mode power converter 520 is restarted, or a predetermined time passes.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Koerts et al with switching off both the high side switch and low side switch when the anomaly is detected in a pattern of over-current events in the signals indicative of the detected over-current as suggested by Ramond to disable operation of the transistors during short circuit conditions to avoid damaging the power converter.
Regarding claim 12, Koerts et al [e.g., Figs. 2, 3 and 6] discloses wherein the anomaly [e.g., ocd_hs_p1 and ocd_Is_p1] is detected when a further over-current event is signaled in a given time interval after a previous over-current event for a same switch [e.g., OCD event withing time interval shown in Fig. 4 and 5] after a previous over-current event for a same switch [e.g., p. 0049 recites "The ocd_event_position 620 may be stored for more than one cycle of the pwm_carrier. However, storing it for more than three cycles may have diminishing returns. Thus, the ocd_event_position 620 may be stored for two of the pwm-carrier edges after an ocd- event."].
Regarding claim 15, Koerts et al [e.g., Figs. 2, 3 and 6] discloses wherein the anomaly is detected when a further over-current event [e.g., ocd_hs_p1 and ocd_ls_p1] in one switch is signaled in a given time interval after a previous over- current event of another switch [e.g., p. 0045 recites "The ocp_count block may have multiple functions, such as counting the pwm_carrier position, sampling and holding the counted position when an excessive current event occurs, and continuing to hold the position for the next two PWM carrier edges. The carrier edges may be either positive or negative. Each output (outp1, outp2, outm1, and outm2) may have a respective own ocp_count block". It continues on p. 0049 recites "The ocd_event_position 620 may be stored for more than one cycle of the pwm_carrier. However, storing it for more than three cycles may have diminishing returns. Thus, the ocd_event_position 620 may be stored for two of the pwm-carrier edges after an ocd-event."].
Regarding claim 18, Koerts et al [e.g., Figs. 2, 3, 6, 7] discloses wherein the anomaly detected [e.g., signals ocd_hs_p1 and ocd_ls_p1] is a pattern of over- current events including an over-current event on one switch when the cycle-by- cycle protected driving signal commands said one switch to be turned off [e.g., p's 0045 - 0047 recites "The ocp_count block may have multiple functions, such as counting the pwm_carrier position, sampling and holding the counted position when an excessive current event occurs, and continuing to hold the position for the next two PWM carrier edges. The carrier edges may be either positive or negative. Each output (outp1, outp2, outm1, and outm2) may have a respective own ocp_count block. [0046] After the sensor detects an excessive current event at running event position 610, the phase (pwm_carrier, phase 0) gets the detection signal from the sensor at the time 620, marked with the first dashed line. The value of a counter, starting at the rising edge of the pwm-carrier, is stored by a sample and hold technique. This is the ocd_event_position 620. [0047] Because the running_event_position 610 is larger than the stored ocd_event_position 620 the output signal should be inverted. After enough time has elapsed to reach time 630 the running_event_position 610 becomes larger than the stored ocd_event_position 620. Thus, this output should also be inverted". It continues on p. 0049 "The ocd_event_position 620 may be stored for more than one cycle of the pwm_carrier”].
7. Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Koerts et al in view of Ramond and U.S Patent No. 8,018,694 B1; (hereinafter Koerts et al, Ramond and Wu). Both cited in previous Office Action dated 12/02/2025.
Regarding claim 6, Koerts et al discloses the claimed invention except for a logic circuit configured to perform a logic OR between the signal indicative of the detected over-current at said high side switch and the signal indicative of the detected over-current at said low side switch.
Wu [e.g., Fig. 1] teaches a logic circuit configured to perform a logic OR [e.g., OR gate 22, column 5 lines 59 - 62 recites "The OR gates 22, 24 each receive the output signal from latch circuit 26 and a respective signal from control logic 12. The OR gates 22, 24 each perform an OR operation on the received input signals and provide a drive signal to the gates of switches 14, 16, respectively"] between the signal indicative of the detected over-current at said high side switch [e.g., signal supplied by control logic 12, columns 5 lines 4 - 20 recites "Current sensing circuitry 46 senses the current through switch 14, which can be the same as that flowing through the inductor 18. Current sensing circuitry 46 can be implemented with a current sensing amplifier. The PWM comparator 48 receives the current sensing signal from current sensing circuitry 46. PWM comparator 48 also receives a signal from a compensation node (which, as shown, can be the junction between error amplifier 32, compensation circuitry 40, and over-current protection circuitry 44). The relationship between the current through inductor 18 and the compensation node is linear. Thus, the voltage or current at the compensation node is proportional to the value of the inductor current. When current through inductor 18 is at its maximum (the primary current limit), the value of the compensation node likewise is at its maximum. The PWM comparator 48 compares the two input signals and provides an output signal for pulse-width modulation to the control logic 12.”] and the signal indicative of the detected over- current at said low side switch [e.g., signal provided by latch 26 column 5 lines 28 - 40 recites "The latch circuit 26, as shown, can be implemented as a set-reset (SR) flip- flop. The set input of the latch circuit 26 receives the output from over-current protection circuitry 44, and the reset input receives the output from comparator 28. Latch circuit 26 provides a signal to each of the OR gates 22 and 24. When the over-current protection circuitry outputs a signal indicating that there is an over-current condition or short-circuit, latch circuit 26 is set so that normal switching is halted--the high-side switch 14 is latched off, and the low-side switch 16 is latched on. The application of a reset signal to the reset input of the latch circuit 26 releases the latch circuit 26 and allows the normal switching behavior to resume or continue for switches 14 and 16"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Koerts et al with a logic circuit configured to perform a logic OR between the signal indicative of the detected over-current at said high side switch and the signal indicative of the detected over-current at said low side switch as suggested by Wu to compare signals and generate a high logic during over-current periods on either high side or low side switch.
Response to Arguments
8. Applicant's arguments filed 02/26/2026 have been fully considered but they are not persuasive.
Applicant(s) argue(s):
Applicants respectfully disagree and request reconsideration of the rejection. Claim 1 specifically requires, for the anomaly detection circuit, an operation to "switch off both the high side switch and low side switch." Ramond Figure 5 shows a circuit with a high side switch 523 and a low side switch 526. There is a high side short circuit detection circuit 524 that operates to detect a short circuit event for the high side switch 523 when the high side switch 523 is turned on and in response thereto control high side driver 522 to turn off the high side switch 523. Similarly, there is a low side short circuit detection circuit 527 that operates to detect a short circuit event for the low side switch 526 when the low side switch 526 is turned on and in response thereto control low side driver 525 to turn off the low side switch 526. The overcurrent detection circuits 525, 527 in Ramond operate completely independently of each other, and thus are not configured to "switch off both the high side switch and low side switch" responsive to the detected over-current.
In response, as suggested by Ramond on paragraph 0031 “High-side short circuit detection circuit 524 senses HIGH-DRAIN. When high-side transistor 523 is conducting and a short circuit condition occurs, high-side short circuit detection circuit 524 activates HDETECT, disabling high-side driver 522 and high-side transistor 523 for the remainder of the switching cycle. Low-side short circuit detection circuit 527 senses LOW-DRAIN. When low-side transistor 526 is conducting and a short circuit condition occurs, low-side short circuit detection circuit 527 activates LDETECT, disabling low-side driver 525 and low-side transistor 526 for the remainder of the switching cycle. Fault management circuit 528 receives both HDETECT and LDETECT and responsively forms the fault signal.” It continues on paragraph 0032 “ …, controller 521 ceases generating HCONTROL and LCONTROL in response to the fault signal. In this example, controller 521 can refrain from generating HCONTROL and LCONTROL either until an external signal is provided to switched mode power converter 520, switched mode power converter 520 is restarted, or a predetermined time passes.” Therefore, as a result of the fault signal generated by the Fault Management circuit 528 and received by controller 521, the controller ceases generating signals HCONTROL and LCONTROL causing both HDRV and LDRV to stop operation until an external signal is provided to switched mode power converter, restarted, or a predetermined time passes.
Additionally, the applicant(s) argues(s)
Claim 1 still further requires, for the anomaly detection circuit, switching off both the high side switch and low side switch "when an anomaly is detected in a pattern of over-current events indicated by the signals indicative of the detected over-current." The overcurrent detection and switch turn off taught by Ramond occurs independently with respect to each switch (as noted above) and furthermore occurs in response to a detecting single overcurrent event (at either switch). There is no consideration made in Ramond for detecting "a pattern of over-current events indicated by [overcurrent] signals. The claimed operation requires plural (two or more) "over- current events" which occur in "a pattern" in order to trigger "switching off both the high side switch and low side switch." There is no teaching or suggestion for this anomaly detection circuit operation in Ramond.
In response, as displayed on timing diagram 300 in Fig. 3 and suggested in paragraph 0020 recites “At t4 a short from the source terminal of the transistor to ground occurs, represented by Short-to-Ground going to a logic high state and VSW going to a low voltage amplitude. When the short circuit condition occurs, the drain-to-source voltage drop caused by an increased current flowing across the ON resistance of the transistor causes the voltage at the input of the inverter to rise above its switchpoint and INV activates. The digital processing circuit determines from CONTROL and INV that the short circuit condition occurred during a switching cycle of the gate driver and responsively activates DETECT. When DETECT becomes active, the gate driver turns off the transistor for the remainder of the switching cycle. At t5, CONTROL is deactivated, and DETECT is reset. At t6, a new switching cycle is initiated, CONTROL is activated, and the gate driver turns on the transistor after a propagation delay. In this example, the short circuit condition persists; therefore, the digital processing circuit reactivates DETECT and the gate driver and transistor are disabled for the remainder of the switching cycle.” As a result, as mentioned above, during short circuit condition the voltage at the input of the inverter rises above its switchpoint and INV activates. As a result, while INV signal is active (low logic) is detected during the new switching cycle indicative of a short circuit condition. Therefore, the rejection is maintained.
Examiner’s Note
9. Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
10. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
11. Claims 3 - 4, 7 - 8, 13 - 14 and 16 - 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… wherein said given time interval has a length longer than a cycle of a frequency of the PWM signal as determined from a clock signal having a frequency that is equal to or greater than the frequency of the PWM signal.”
The primary reason for the indication of the allowability of claim 7 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… wherein said given time interval has a length longer than a cycle of a frequency of the PWM signal as determined from a clock signal having a frequency that is equal to or greater than the frequency of the PWM signal.”
The primary reason for the indication of the allowability of claim 13 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… wherein said given time interval has a length longer than a cycle of a frequency of the PWM signal as determined from a clock signal having a frequency that is equal to or greater than the frequency of the PWM signal.”
The primary reason for the indication of the allowability of claim 16 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… wherein said given time interval has a length longer than a cycle of a frequency of the PWM signal as determined from a clock signal having a frequency that is equal to or greater than the frequency of the PWM signal.”
Conclusion
12. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
Prosecution Insights