Prosecution Insights
Last updated: October 02, 2026
Application No. 18/215,033

DISTRIBUTED CIRCUIT FOR ELECTROSTATIC DISCHARGE PROTECTION FOR A SIGNAL PAD

Non-Final OA §102
Filed
Jun 27, 2023
Examiner
JACKSON, STEPHEN W
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
996 granted / 1077 resolved
+32.5% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
9 currently pending
Career history
1081
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
24.6%
-15.4% vs TC avg
§102
34.2%
-5.8% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1077 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4 and 7-9 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liu (2020/0219828A1). With regard to claims 1,2 and 8, Liu discloses An integrated circuit (IC) device, comprising: a first signal pad 102; a first inductor 130 coupled in series with the first signal pad 102; a first set of primary ESD diodes 132 coupled to the first signal pad 102 and a first side of the first inductor 130; and a first set of secondary ESD diodes 133 coupled to a second side of the first inductor 130 (see para 0028). With regard to claim 3, para 0028 discloses different junction areas for the first and second diode sets 132 and 133, with the area directly related to the amount of ESD protection provided. With regard to claims 4 and 9, para 0028 discloses that the different areas for ESD diodes 132 and 133 are used to establish different capacitive loads for the first and second (primary and secondary) diode sets. With regard to claim 7, in para 0042, Liu discloses a frequency range extending to 40 Ghz. Allowable Subject Matter Claims 15-20 are allowed. Claims 5,6 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: in the above mentioned claims the combination of N and P type diodes with a resistor connected to a junction between the diode types and the signal pad, and the transformer limitations of claim 15, have not been taught or been fairly suggested by the prior art of record. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN W JACKSON whose telephone number is (571)272-2051. The examiner can normally be reached M-F 6:30-3:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. SWJackson August 20, 2026 /STEPHEN W JACKSON/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jun 27, 2023
Application Filed
Oct 24, 2023
Response after Non-Final Action
Aug 24, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+7.3%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1077 resolved cases by this examiner. Grant probability derived from career allowance rate.

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