Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed December 1st, 2025 has been entered. Claims 1-7 and 9-21 are pending in the application while claim 8 has been cancelled. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed September 10th, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 9, 18 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Said et al. (US 11171097 B2) hereinafter referred to as "Said").
Regarding claim 1, Said teaches a semiconductor apparatus, configured to perform a predetermined function based on a plurality of circuit components, the semiconductor apparatus comprising: a first circuit (Fig. 3A, element 900; [column 6, line 6]), including a first semiconductor substrate (Fig. 3A, element 908; [column 6, line 9]), a first group of circuit components (Fig. 3A, element 920; [column 6, line 9]) among the plurality of circuit components formed on the first semiconductor substrate, and a first group of metal layers (Fig. 3A, element 46; [column 6, line 38]), wherein, the first group of circuit components are distributed to at least one circuit block (Fig. 3A, element 920, [column 6, line 9]), and traces (Fig. 3A, element 982; [column 7, line 22]) for each circuit block are formed in at least some metal layers of the first group of metal layers; a second circuit (Fig. 3A, element 700; [column 12, line 34]), including a second semiconductor substrate (Fig. 3A, element 708; [column 12, line 36]), a second group of circuit components (Fig. 3A, element 720; [column 12, line 36]) among the plurality of circuit components formed on the second semiconductor substrate, and a second group of metal layers (Fig. 3A, element 780, D0, D1; [column 12, line 39]), wherein, the second group of circuit components are distributed to at least one circuit block (Fig. 3A, element 720; [column 12, line 36]), and traces (Fig. 3A, element D0, D1; [column 13, line 24-26]) for each circuit block are formed in at least some metal layers of the second group of metal layers; wherein, the first circuit and the second circuit form a stacked structure and have electrical connections (Fig. 3A, element 900, 700; [column 16, line 40-43]) therebetween, and lower surfaces of the first semiconductor substrate (Fig. 3A, element 908; [column 6, line 9]) and the second semiconductor substrate (Fig. 3A, element 708; [column 12, line 36]) respectively serve as an upper surface and a lower surface of the stacked structure, wherein one or more metal layers included in one of the first circuit and the second circuit serve as a shared metal layer for supplying a signal/power to a predetermined circuit component included in the other one of the first circuit and the second circuit (Fig. 3A, element 700, 982 (bit line driver); [column 12, line 60-67]).
Regarding claim 2, Said teaches the first semiconductor substrate and the second semiconductor substrate being fabricated based on Wafer-on-Wafer (WoW) technology (Fig. 3A, element 908, 708; [column 16, line 40-43]).
Regarding claim 9, Said teaches the second group of circuit components including one or more voltage regulators (Fig. 3A, element 700 (source power supply); [column 13, line 7-9]), configured to supply power to circuit components to be powered in the first group of circuit components, and wherein, the one or more voltage regulators are distributed to one or more power supplying circuit blocks of the second circuit (Fig. 3A, element 700; [column 12, line 61]), and the one or more power supplying circuit blocks are arranged opposite to circuit blocks to be powered including the circuit components to be powered included in the first circuit (Fig. 3A, element 900, [column 13, line 9]).
Regarding claim 18, Said teaches a semiconductor apparatus, configured to perform a predetermined function based on a plurality of circuit components, the semiconductor apparatus comprising: a first circuit (Fig. 3A, element 900; [column 6, line 6]), including a first semiconductor substrate (Fig. 3A, element 908; [column 6, line 9]), a first group of circuit components (Fig. 3A, element 920; [column 6, line 9]) among the plurality of circuit components formed on the first semiconductor substrate, and a first group of metal layers (Fig. 3A, element 46; [column 6, line 38]), wherein, the first group of circuit components are distributed to at least one circuit block (Fig. 3A, element 920, [column 6, line 9]), and traces (Fig. 3A, element 982; [column 7, line 22]) for each circuit block are formed in at least some metal layers of the first group of metal layers; a second circuit (Fig. 3A, element 700; [column 12, line 34]), including a second semiconductor substrate (Fig. 3A, element 708; [column 12, line 36]), a second group of circuit components (Fig. 3A, element 720; [column 12, line 36]) among the plurality of circuit components formed on the second semiconductor substrate, and a second group of metal layers (Fig. 3A, element 780, D0, D1; [column 12, line 39]), wherein, the second group of circuit components are distributed to at least one circuit block (Fig. 3A, element 720; [column 12, line 36]), and traces (Fig. 3A, element D0, D1; [column 13, line 24-26]) for each circuit block are formed in at least some metal layers of the second group of metal layers; wherein, the first circuit and the second circuit form a stacked structure and have electrical connections (Fig. 3A, element 900, 700; [column 16, line 40-43]) therebetween, and lower surfaces of the first semiconductor substrate (Fig. 3A, element 908; [column 6, line 9]) and the second semiconductor substrate (Fig. 3A, element 708; [column 12, line 36]) respectively serve as an upper surface and a lower surface of the stacked structure, wherein, the second group of circuit components including one or more voltage regulators (Fig. 3A, element 700 (source power supply); [column 13, line 7-9]), configured to supply power to circuit components to be powered in the first group of circuit components, and wherein, the one or more voltage regulators are distributed to one or more power supplying circuit blocks of the second circuit (Fig. 3A, element 700; [column 12, line 61]), and the one or more power supplying circuit blocks are arranged opposite to circuit blocks to be powered including the circuit components to be powered included in the first circuit (Fig. 3A, element 900, [column 13, line 9]).
Regarding claim 19, Said teaches one or more metal layers (Fig. 3A, element 46, 980, 780, D0, D1; [column 12, line 58-60], [column 13 line 23-26]), in the first group of metal layers and the second group of metal layers, between a first circuit block (Fig. 3A, element 920; [column 6, line 9]) in the first circuit and a second circuit block (Fig. 3A, element 720; [column 12, line 36]) in the second circuit serve as one or more shared metal layers, wherein, a first circuit component included in the first circuit block in the first circuit and a second circuit component included in the second circuit block in the second circuit are capable of supplying a signal and/or power to each other through the one or more shared metal layers (Fig. 3A, element 982 (bit line driver); [column 12, line 60-67]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Said in view of Kim et al. (US 20220359341 A1) hereinafter referred to as "Kim" .
Regarding claim 3, Said teaches the semiconductor apparatus according to claim 1. However, Said does not teach one or more sides of a projection region of each circuit block on a lower surface of a corresponding semiconductor substrate being adjacent to or aligned with one or more sides of the lower surface of the corresponding semiconductor substrate.
Kim teaches one or more sides (Fig. 18, element 10, 20, 30, 40, 50; ¶: [0134]) of a projection region of each circuit block on a lower surface of a corresponding semiconductor substrate being adjacent to or aligned with one or more sides of the lower surface of the corresponding semiconductor substrate.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the circuit blocks of the semiconductor device in such a manner in order to increase its capacity and multifunction (¶: [0003]).
Regarding claim 4, Said teaches the semiconductor apparatus according to claim 1. However, Said does not teach at least two sides of a projection region of at least one circuit block on a lower surface of a corresponding semiconductor substrate being adjacent to or aligned with at least two sides of the lower surface of the corresponding semiconductor substrate.
Kim teaches at least two sides (Fig. 18, element 10, 20, 30, 40, 50; ¶: [0134]) of a projection region of at least one circuit block on a lower surface of a corresponding semiconductor substrate being adjacent to or aligned with at least two sides of the lower surface of the corresponding semiconductor substrate.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the circuit blocks of the semiconductor device in such a manner in order to increase its capacity and multifunction (¶: [0003]).
Regarding claim 5, Said teaches the semiconductor apparatus according to claim 1. However, Said does not teach projection regions of two or more different circuit blocks in a same circuit on a lower surface of a corresponding semiconductor substrate having sides of a same length in a first direction.
Kim teaches projection regions of two or more different circuit blocks (Fig. 18, element 10, 20, 30, 40, 50; ¶: [0134]) in a same circuit on a lower surface of a corresponding semiconductor substrate having sides of a same length in a first direction.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the circuit blocks of the semiconductor device in such a manner in order to increase its capacity and multifunction (¶: [0003]).
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Claim(s) 11, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Said in view of Lee et al. (US 20210065602 A1) hereinafter referred to as "Lee", and further in view of Cheng et al. (US 20220093037 A1) hereinafter referred to as "Cheng".
Regarding claim 11, Said teaches the semiconductor apparatus according to claim 1. However, Said does not teach a display driver integrated circuit, the display driver integrated circuit including: a Static Random Access Memory (SRAM), an Auto Place & Route (APR) area, a Gate Driver (GD), a Source Driver (SD), and an Interface (I/O).
Lee teaches a display driver integrated circuit, the display driver integrated circuit including: a Static Random Access Memory (SRAM) (Fig. 4A, 4B, element “SRAM”; ¶: [0071]), a Gate Driver (GD) (Fig. 4A, 4B, element “Gate”; ¶: [0071]), a Source Driver (SD) (Fig. 4A, 4B, element “Source”; ¶: [0071]), and an Interface (I/O) (¶: [0076]). Neither Said nor Lee teach an Auto Place & Route (APR) area.
Cheng teaches an Auto Place & Route (APR) area (element “FPGA”; ¶: [0173]).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include various circuits in order to control various components of the semiconductor device, such as driving data lines, as well as storing and improving the quality of data received (Lee, ¶: [0048-0049]).
Regarding claim 20, Said teaches a semiconductor apparatus, configured to perform a predetermined function based on a plurality of circuit components, the semiconductor apparatus comprising: a first circuit (Fig. 3A, element 900; [column 6, line 6]), including a first semiconductor substrate (Fig. 3A, element 908; [column 6, line 9]), a first group of circuit components (Fig. 3A, element 920; [column 6, line 9]) among the plurality of circuit components formed on the first semiconductor substrate, and a first group of metal layers (Fig. 3A, element 46; [column 6, line 38]), wherein, the first group of circuit components are distributed to at least one circuit block (Fig. 3A, element 920, [column 6, line 9]), and traces (Fig. 3A, element 982; [column 7, line 22]) for each circuit block are formed in at least some metal layers of the first group of metal layers; a second circuit (Fig. 3A, element 700; [column 12, line 34]), including a second semiconductor substrate (Fig. 3A, element 708; [column 12, line 36]), a second group of circuit components (Fig. 3A, element 720; [column 12, line 36]) among the plurality of circuit components formed on the second semiconductor substrate, and a second group of metal layers (Fig. 3A, element 780, D0, D1; [column 12, line 39]), wherein, the second group of circuit components are distributed to at least one circuit block (Fig. 3A, element 720; [column 12, line 36]), and traces (Fig. 3A, element D0, D1; [column 13, line 24-26]) for each circuit block are formed in at least some metal layers of the second group of metal layers; wherein, the first circuit and the second circuit form a stacked structure and have electrical connections (Fig. 3A, element 900, 700; [column 16, line 40-43]) therebetween, and lower surfaces of the first semiconductor substrate (Fig. 3A, element 908; [column 6, line 9]) and the second semiconductor substrate (Fig. 3A, element 708; [column 12, line 36]) respectively serve as an upper surface and a lower surface of the stacked structure.
However, Said does not teach a display driver integrated circuit, and the display driver integrated circuit including: a Static Random Access Memory (SRAM), an Auto Place & Route (APR) area, a Gate Driver (GD), a Source Driver (SD), and an Interface (I/O).
Lee teaches a display driver integrated circuit, and the display driver integrated circuit including: a Static Random Access Memory (SRAM) (Fig. 4A, 4B, element “SRAM”; ¶: [0071]), a Gate Driver (GD) (Fig. 4A, 4B, element “Gate”; ¶: [0071]), a Source Driver (SD) (Fig. 4A, 4B, element “Source”; ¶: [0071]), and an Interface (I/O) (¶: [0076]). Neither Said nor Lee teach an Auto Place & Route (APR) area
Cheng teaches an Auto Place & Route (APR) area (element “FPGA”; ¶: [0173]).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include various circuits in order to control various components of the semiconductor device, such as driving data lines, as well as storing and improving the quality of data received (Lee, ¶: [0048-0049]).
Regarding claim 21, Said in view of Lee and further in view of Cheng teaches the semiconductor apparatus according to claim 20. Said further teaches one or more metal layers (Fig. 3A, element 46, 980, 780, D0, D1; [column 12, line 58-60], [column 13 line 23-26]), in the first group of metal layers and the second group of metal layers, between a first circuit block (Fig. 3A, element 920; [column 6, line 9]) in the first circuit and a second circuit block (Fig. 3A, element 720; [column 12, line 36]) in the second circuit serve as one or more shared metal layers, wherein, a first circuit component included in the first circuit block in the first circuit and a second circuit component included in the second circuit block in the second circuit are capable of supplying a signal and/or power to each other through the one or more shared metal layers (Fig. 3A, element 982 (bit line driver); [column 12, line 60-67]).
Allowable Subject Matter
Claims 6, 7, 10, and 12-17 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
-Claims 6 and 7 are objected to due to their dependence on claim 1
-Claim 10 is objected to due to its dependence on claim 9
-Claim 12 is objected to due to its dependence on claim 11
-Claims 13, 14, 16, and 17 are objected to due to their dependence on claim 12
-Claim 15 is objected to due to its dependence on claim 13
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112:
Regarding claim 6, Said in view of Kim teaches certain elements of the claimed invention including at least one circuit block and a projection region of the circuit block on a lower surface of a corresponding semiconductor substrate. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “for each circuit block, a projection region of the circuit block on a lower surface of a corresponding semiconductor substrate having a first side longer than a second side, wherein the first side is a side adjacent or parallel to a projection region of another circuit block in the same circuit on the lower surface of the corresponding semiconductor substrate, and the second side is another side of the projection region of the circuit block on the lower surface of the corresponding semiconductor substrate.” as recited in claim 6.
Regarding claim 7, Said in view of Kim teaches certain elements of the claimed invention including at least one circuit block and a projection region of the circuit block on a lower surface of a corresponding semiconductor substrate. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “the first circuit block and the second circuit block being arranged opposite to each other, or the first circuit block is arranged opposite to another circuit block in the second circuit which is not the second circuit block.” as recited in claim 7.
Regarding claim 10, Said in view of Kim teaches certain elements of the claimed invention including at least one circuit block, a projection region of the circuit block on a lower surface of a corresponding semiconductor substrate and a power supplying circuit. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “one or more power supplying circuit blocks on the lower surface of the first semiconductor substrate in the first circuit overlapping with a middle region of a projection region of the circuit block to be powered on the lower surface of the first semiconductor substrate.” as recited in claim 10.
Regarding claim 12, and thus, dependent claims 13 and 15, Said in view of Lee and further in view of Cheng teaches certain elements of the claimed invention including a Static Random Access Memory (SRAM), an Auto Place & Route (APR) area, a Gate Driver (GD), a Source Driver (SD), and an Interface (I/O). However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “the first group of circuit components include the Static Random Access Memory (SRAM) and the Auto Place & Route (APR) area and the second group of circuit components include the Gate Driver (GD), the Source Driver (SD), and the Interface (I/O)” as recited in claim 12 and “a second SD circuit block, and when the first circuit and the second circuit form the stacked structure, the first SD circuit block and the second SD circuit block are arranged opposite to each other” as recited in claim 13.
Regarding claim 14, The prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “the second group of circuit components further comprising another SRAM distributed to another SRAM circuit block in the second circuit, wherein when the first circuit and the second circuit form the stacked structure, the APR circuit block in the first circuit and the other SRAM circuit block in the second circuit are arranged opposite to each other.” as recited in claim 14.
Regarding claim 17, The prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “a plurality of voltage regulators, wherein the plurality of voltage regulators are arranged in the plurality of power supplying circuit blocks of the second circuit, and the plurality of power supplying circuit blocks are arranged opposite to the SRAM circuit block and the APR circuit block in the first circuit.” as recited in claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments, see (“Remarks": Pg 8, III. PATENTABILITY ARGUMENTS, B.), filed 12/01/2025, with respect to claim 7 have been fully considered and are persuasive.
The applicant argues that “the rejection of claim 7 under 35 U.S.C. § 112 for purportedly being indefinite should be withdrawn because it defines that the circuit components have identical circuit attributes or perform the same circuit functions”. MPEP § 2173 discussed indefiniteness of a claim. Specifically, MPEP § 2173.01 states that a claim may not be rejected solely because of the type of language used to define the subject matter for which patent protection is sought. Furthermore, MPEP § 2173.02 states that a decision on whether a claim is indefinite under 35 U.S.C. 112(b) requires a determination of whether those skilled in the art would understand what is claimed when the claim is read in light of the specification which. Thus rejection of claim 7 has been withdrawn. However, it should be noted that MPEP § 2173.01 further discusses broadest reasonable interpretation. Specifically, “under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification”. Since neither “having identical circuit attributes or performing the same circuit functions” (see “Remarks”, Pg. 8, III. PATENTABILITY ARGUMENTS, B.), nor a clear definition of what the applicant means by “same type of circuit component” is mentioned in the specification, the phrase “same type of circuit component” will be examined under broadest reasonable interpretation.
Applicant’s arguments, see (“Remarks": Pg 9, III. PATENTABILITY ARGUMENTS, C.), filed 12/01/2025, with respect to the rejections of claims 1-2 and 8 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made under 35 U.S.C. § 102 in view of the previously applied reference Said (U.S. 11,171,097 B2).
Regarding claim 1 (which currently includes the limitations of the former claim 8), Said teaches a semiconductor apparatus, configured to perform a predetermined function based on a plurality of circuit components, the semiconductor apparatus comprising: a first circuit (Fig. 3A, element 900; [column 6, line 6]), including a first semiconductor substrate (Fig. 3A, element 908; [column 6, line 9]), a first group of circuit components (Fig. 3A, element 920; [column 6, line 9]) among the plurality of circuit components formed on the first semiconductor substrate, and a first group of metal layers (Fig. 3A, element 46; [column 6, line 38]), wherein, the first group of circuit components are distributed to at least one circuit block (Fig. 3A, element 920, [column 6, line 9]), and traces (Fig. 3A, element 982; [column 7, line 22]) for each circuit block are formed in at least some metal layers of the first group of metal layers; a second circuit (Fig. 3A, element 700; [column 12, line 34]), including a second semiconductor substrate (Fig. 3A, element 708; [column 12, line 36]), a second group of circuit components (Fig. 3A, element 720; [column 12, line 36]) among the plurality of circuit components formed on the second semiconductor substrate, and a second group of metal layers (Fig. 3A, element 780, D0, D1; [column 12, line 39]), wherein, the second group of circuit components are distributed to at least one circuit block (Fig. 3A, element 720; [column 12, line 36]), and traces (Fig. 3A, element D0, D1; [column 13, line 24-26]) for each circuit block are formed in at least some metal layers of the second group of metal layers; wherein, the first circuit and the second circuit form a stacked structure and have electrical connections (Fig. 3A, element 900, 700; [column 16, line 40-43]) therebetween, and lower surfaces of the first semiconductor substrate (Fig. 3A, element 908; [column 6, line 9]) and the second semiconductor substrate (Fig. 3A, element 708; [column 12, line 36]) respectively serve as an upper surface and a lower surface of the stacked structure, wherein one or more metal layers included in one of the first circuit and the second circuit serve as a shared metal layer for supplying a signal/power to a predetermined circuit component included in the other one of the first circuit and the second circuit (Fig. 3A, element 700, 982 (bit line driver); [column 12, line 60-67]).
Regarding claim 2, Said teaches the first semiconductor substrate and the second semiconductor substrate being fabricated based on Wafer-on-Wafer (WoW) technology (Fig. 3A, element 908, 708; [column 16, line 40-43]).
Applicant's arguments filed 12/01/2025 regarding claims 18-21 have been fully considered but they are not persuasive.
As claim 1 and claim 9 have been rejected in this action, claim 18 and claim 19, incorporating the features of claims 1 and 9, have also been rejected.
As claim 1 and claim
Conclusion
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/I.H./Examiner, Art Unit 2899 /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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