Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the communication filed on 12/8/2025.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot due to the new grounds of rejection presented below further in view of Balasubramanian.
All objections and rejections not set forth below have been withdrawn.
Claims 1-20 have been examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Spencer et al. (US Patent Application Publication Number 2019/0013086), and further in view of Driscoll (US Patent Application Publication Number 2020/0322126), and further in view of Balasubramanian (US Patent Application Publication Number 2006/0174156).
Regarding claim 1, Spencer disclosed an apparatus, comprising: a number of memory devices (Spencer Figs. 2-4 and Paragraphs 0018-0028 for example) configured to store: a memory transfer block (MTB) in cypher text form, the MTB including a number of user data blocks (UDBs) that are associated with a write command (Spencer Figs. 2-4 and Paragraphs 0018-0028 for example);
a memory controller coupled to one or more of the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0018-0028 for example) and configured to: perform a first error detection operation on the MTB using first error detection information generated based on cypher text of the MTB (Spencer Figs. 2-4 and Paragraphs 0018-0028 for example); and perform a second error detection operation on an UDB of the MTB using second error detection information generated based on plain text of the UDB (Spencer Figs. 2-4 and Paragraphs 0018-0028 for example).
Spencer did not explicitly teach the memory storing authentication data generated based on plain text of the MTB, or perform an authentication operation on the MTB using the authentication data.
Driscoll taught, in an analogous system, that in addition to performing error detection coding on plaintext prior to encryption (and error detection processing on the plaintext after decryption), authentication and integrity coding can be performed on the plaintext as well (before encryption and after decryption) and the authentication data included with the encrypted data (Driscoll Fig. 4B and Paragraphs 0039-0040 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Further, Spencer and Driscoll did not explicitly teach that the MTB included UDBs that are associated with at least two different write commands. Spencer did teach that the system could be employed in a RAID environment (Spencer Paragraph 0013).
Balasubramanian taught, in a RAID environment, the use of a cache to collect small data fragments sent as write requests and coalescing the fragments to create larger data blocks to be sent to the controller for writing (Balasubramanian Paragraphs 0008-0010 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Balasubramanian in the storage system of Spencer and Driscoll by caching data fragments from small write requests and combining the data fragments into a map unit as taught by Spencer. This would have been obvious because the person having ordinary skill in the art would have been motivated to provide efficient bandwidth utilization of the storage network.
Regarding claim 2, Spencer, Driscoll, and Balasubramanian taught that the memory controller is configured to: write, to one of the number of memory devices, the second error detection information previously generated based on the plain text of the UDB (Spencer Figs. 2-4 and Paragraphs 0018-0028 for example); and cause the one of the number of memory devices to transfer the second error detection information to the memory controller to perform the second error detection operation (Spencer Figs. 2-4 and Paragraphs 0018-0028 for example).
Regarding claim 3, Spencer, Driscoll, and Balasubramanian taught that the memory controller is configured to generate, prior to the second error detection operation and to perform the second error detection operation, the second error detection information subsequent to the authentication (Spencer Figs. 2-4 and Paragraphs 0018-0028 for example and Driscoll Fig. 4B and Paragraphs 0039-0040 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Regarding claim 4, Spencer, Driscoll, and Balasubramanian taught that the memory controller comprises an authenticity and integrity check decoder configured to perform the authentication operation on the MTB (Driscoll Fig. 4B and Paragraphs 0039-0040 for example); and the memory controller further comprises a security decoder configured to decrypt the MTB to convert the cypher text of the MTB to the plain text (Driscoll Fig. 4B and Paragraphs 0039-0040 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Regarding claim 5, Spencer, Driscoll, and Balasubramanian taught that the memory controller is configured to: decrypt the MTB prior to performing the authentication operation on the MTB (Driscoll Fig. 4B and Paragraphs 0039-0040 for example); and perform the authentication operation based at least in part on the plain text of the MTB (Driscoll Fig. 4B and Paragraphs 0039-0040 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Regarding claim 6, Spencer, Driscoll, and Balasubramanian taught that the MTB corresponds to a cache line size (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 7, Spencer, Driscoll, and Balasubramanian taught that the memory controller further comprises a cache configured to store the MTB subsequent to the first error detection operation and the authentication operation being performed on the MTB (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 8, Spencer, Driscoll, and Balasubramanian taught that the memory controller is further configured to cause the cache to transfer the UDB to an error detection decoder configured to perform the second error detection operation to transfer the UDB to a host subsequent to the second error detection operation (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 9, Spencer disclosed an apparatus, comprising: a number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and a memory controller coupled to the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example), the memory controller configured to: generate, in response to receipt of a first user data block (UDB), first error detection information based on plain text of the UDB to perform a first error detection operation on the UDB (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); an memory transfer block (MTB), wherein the MTB corresponds to a cache line size and includes a number of UDBs including the first UDB (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); generate, to perform a second error detection operation on the UDB, second error detection information based on cypher text of the MTB to perform a second error detection operation on the MTB (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and write the MTB, and the second error detection information to the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Spencer did not explicitly disclose generating authentication data based on plain text of an MTB to perform an authentication operation on the MTB, or writing the authentication data to the number of memory devices.
Driscoll taught, in an analogous system, that in addition to performing error detection coding on plaintext prior to encryption (and error detection processing on the plaintext after decryption), authentication and integrity coding can be performed on the plaintext as well (before encryption and after decryption) and the authentication data included with the encrypted data (Driscoll Fig. 4B and Paragraphs 0039-0040 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Further, Spencer and Driscoll did not explicitly teach that the MTB included UDBs that are associated with at least two different write commands. Spencer did teach that the system could be employed in a RAID environment (Spencer Paragraph 0013).
Balasubramanian taught, in a RAID environment, the use of a cache to collect small data fragments sent as write requests and coalescing the fragments to create larger data blocks to be sent to the controller for writing (Balasubramanian Paragraphs 0008-0010 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Balasubramanian in the storage system of Spencer and Driscoll by caching data fragments from small write requests and combining the data fragments into a map unit as taught by Spencer. This would have been obvious because the person having ordinary skill in the art would have been motivated to provide efficient bandwidth utilization of the storage network.
Regarding claim 10, Spencer, Driscoll, and Balasubramanian taught that the memory controller is configured to, in response to receipt of a read command to access the first UDB stored in one of the number of memory devices: cause the number of memory devices to transfer the MTB including the first UDB, the authentication data, and the second error detection information to the memory controller (Spencer Figs. 2-4 and Paragraphs 0014-0028 and Driscoll Fig. 4B and Paragraphs 0039-004 for example); and perform the second error detection operation on the MTB and the authentication operation on the MTB respectively using the second error detection information and the authentication data transferred from the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 and Driscoll Fig. 4B and Paragraphs 0039-004 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Regarding claim 11, Spencer, Driscoll, and Balasubramanian taught that the memory controller is further configured to: write the first error detection information to the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and cause the number of memory devices to transfer the first error detection information to the memory controller to perform the first error detection operation on the UDB using the first error detection information transferred from the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 12, Spencer, Driscoll, and Balasubramanian taught that the memory controller further comprises a cache, wherein the memory controller is configured to write the first UDB to the cache subsequent to the first error detection information being generated (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 13, Spencer, Driscoll, and Balasubramanian taught that the memory controller is configured to cause the cache to transfer the MTB to an authenticity and integrity check encoder that is configured to generate the authentication data (Spencer Figs. 2-4 and Paragraphs 0014-0028 and Driscoll Fig. 4B and Paragraphs 0039-004 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Regarding claim 14, Spencer, Driscoll, and Balasubramanian taught that the memory controller further comprises: a first error detection encoder coupled to a first side of the cache and configured to generate the first error detection information (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and a first error detection decoder coupled to a second side of the cache and configured to perform an error detection operation using the first error detection information (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 15, Spencer, Driscoll, and Balasubramanian taught that the memory controller further comprises: a security encoder configured to encrypt the MTB to convert the plain text of the MTB to the cypher text (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and an authenticity and integrity check encoder configured to generate the authentication data (Spencer Figs. 2-4 and Paragraphs 0014-0028 and Driscoll Fig. 4B and Paragraphs 0039-004 for example); wherein the memory controller is configured to operate the security encoder and the authenticity/integrity check encoder in parallel such that the security encoder and the authenticity/integrity check encoder operate based on a same input corresponding to the plain text of the MTB (Spencer Figs. 2-4 and Paragraphs 0014-0028 and Driscoll Fig. 4B and Paragraphs 0039-004 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Regarding claim 16, Spencer, Driscoll, and Balasubramanian taught that the memory controller is configured to: write the first UDB to a first memory device of the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and write the first error detection information to the first memory device (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 17, Spencer disclosed a method, comprising: receiving, at a memory controller, a write command to write a first user data block (UDB) to a first memory device of a number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); generating first error detection information based on the first UDB to perform a first error detection operation on the first UDB (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); a memory transfer block (MTB), wherein the MTB corresponds to a cache line size and includes a number of UDBs including the first UDB (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); generating second error detection information based on the MTB (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and writing the second error detection information to the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Spencer did not explicitly teach generating authentication data based on the MTB in parallel with cryptographically encrypting the MTB, or writing the authentication data to the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Driscoll taught, in an analogous system, that in addition to performing error detection coding on plaintext prior to encryption (and error detection processing on the plaintext after decryption), authentication and integrity coding can be performed on the plaintext as well (before encryption and after decryption) and the authentication data included with the encrypted data (Driscoll Fig. 4B and Paragraphs 0039-0040 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Driscoll in the error detection system of Spencer by performing authentication and integrity coding prior to encrypting the plaintext and after decrypting ciphertext. This would have been obvious because the person having ordinary skill in the art would have been motivated to enable the system to confirm the cryptographic authenticity and integrity of the data being read from memory.
Further, Spencer and Driscoll did not explicitly teach that the MTB included UDBs that are associated with at least two different write commands. Spencer did teach that the system could be employed in a RAID environment (Spencer Paragraph 0013).
Balasubramanian taught, in a RAID environment, the use of a cache to collect small data fragments sent as write requests and coalescing the fragments to create larger data blocks to be sent to the controller for writing (Balasubramanian Paragraphs 0008-0010 for example).
It would have been obvious to the person having ordinary skill in the art to have employed the teachings of Balasubramanian in the storage system of Spencer and Driscoll by caching data fragments from small write requests and combining the data fragments into a map unit as taught by Spencer. This would have been obvious because the person having ordinary skill in the art would have been motivated to provide efficient bandwidth utilization of the storage network.
Regarding claim 18, Spencer, Driscoll, and Balasubramanian taught that the memory controller further comprises a cache and the method further comprises: writing the first UDB to the cache subsequent to generating the first error detection information (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and performing the first error detection operation subsequent to transferring the first UDB from the cache and prior to writing the first UDB to the first memory device (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 19, Spencer, Driscoll, and Balasubramanian taught performing the first error detection operation on the first UDB without writing the first error detection information to one of the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Regarding claim 20, Spencer, Driscoll, and Balasubramanian taught writing the first error detection information to one of the number of memory devices (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example); and subsequently transferring the first error detection information from the one of the number of memory devices to perform the first error detection operation on the first UDB using the first error detection information (Spencer Figs. 2-4 and Paragraphs 0014-0028 for example).
Conclusion
Claims 1-20 have been rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MATTHEW T HENNING/ Primary Examiner, Art Unit 2491