DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
Applicant’s arguments filed 07/29/2026 with respect to claims 1-4, 6-7, 9-14, 17, 19 and 24-29 have been fully considered but are moot in view of newly cited reference based on amendment.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 1-4, 6, 10, 12-14, 19 and 24-29 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dykema et al. (US pub. # 2023/0229624), hereinafter, “Dykema”.
2. As per claims 1 and 19, Dykema discloses a system comprising: an input/output die (IOD) (TCC 116 combined with fabrics 124 of fig. 1B, as discloses in paragraph 0087) that couples a plurality of devices [IO devices 460 combined with associated, respective attached components, of connected RPs, as discloses in paragraph 0148; see paragraph 0055, which discloses “a connection route between RPs can include one or more interconnection fabrics, or paths through interconnection fabrics, coupling a pair of RPs (and/or, a set of RPs more than 2). Interconnection fabrics included in a communications route between particular RPs can include, for example, particular ALNs, TLNs, or sub-arrays of an ALN or TLN; particular switches and/or ports of switches, of an ALN or TLN; and/or other particular other networks, such as Ethernets and InfiniBand networks. A connection route between RPs can include interconnection interfaces, such as I/O buses, data/memory buses, I/O links, network interfaces, and so forth, that can connect RPs directly to each other, can RPs to an interconnection fabric, and/or can connect interconnection fabrics intervening between RPs” and paragraph 0141, which discloses “Computer 410 can be a host processor, runtime processor, and/or RP of an RDS”]; a programmable fabric (interconnection fabrics, as discloses in paragraph 0054, 0055) included in the IOD (see paragraph 0054), the programmable fabric having interconnects that are reconfigurable for connecting the plurality of devices according to multiple network topologies of the programmable fabric [see paragraph 0041, which discloses “using the example of an RDS having RPs as dataflow processors, the RDS can configure multiple dataflow workers in a worker logical topology (e.g., a logical ring, tree, mesh, etc.) to perform computations of dataflow applications concurrently and can allocate particular RPs of the RDS to execute the dataflow workers (e.g., execute programs and/or operations of the workers). An RDS can allocate RPs to execute the dataflow workers among multiple RPs of the same and/or differing nodes. An RDS can physically interconnect RPs, in a physical interconnection topology corresponding to a worker logical topology, to enable dataflow workers to communicate (e.g., transfer application data and/or computational results within a pipeline or among parallel processing units) amongst each other while executing an application. As used herein, the term “physical interconnection topology” refers to an interconnection topology of dataflow processors, comprising physical interface connections among dataflow processors, physical interconnect fabrics interconnecting dataflow processors, and/or physical interconnection interfaces interconnecting dataflow processors and interconnection fabrics” or paragraph 0045, or 0129]; and a programmable core included in the IOD (see fig. 4 and paragraph 0141), the programmable core configured to implement at least one reconfigurable policy (a connection cost, as discloses in paragraph 0074) for scheduling memory access operations by the plurality of devices to a physical memory [see paragraph 0057, which discloses “a connections-optimized RP configuration can correspond, for example, to a highest performance communications route (hereinafter, for brevity, “route”) coupling RPs executing dataflow workers within a worker logical topology (e.g., a DPW ring). To determine a connections-optimized RP configuration, a TCC can determine – retrieve, such as from a hardware description of an RDS, or a database, or, alternatively, can compute – “connection costs”. In implementations connections costs can be based on communication metrics, which can comprise, for example, a shortest route (e.g., number of hops, or overall latency), a lowest data transfer latency, a highest data transfer bandwidth, utilization of shared interconnects (e.g., shared interconnects to an interconnection fabric), and/or utilization of interconnection fabrics, associated with communications routes among the RPs” or paragraph 0068, which discloses “to illustrate further, an RDS can allocate some or all of RPs 102 of node 100 to execute dataflow workers configured in a worker logical topology. Using, again, the example of AllReduce, a preferred logical topology of dataflow workers to execute the application can be a DPW ring. In a case in which only RPs of node 100 are allocated, TCC 110 can configure the allocated RPs to form a complete, intranodal ring of RPs, within node 100, corresponding to a dataflow workers configured in the DPW ring. TCC 110 can compute intranodal connection costs associated with routes between any pair of RPs of node 100 within node 100 and/or through fabric 106. The intranodal connection costs can comprise, or correspond to, for example, topological and/or performance characteristics of interconnects 108 that can couple the RPs to fabric 106 and/or to a route through fabric 106 between a pair of RPs”].
3. As per claim 2, Dykema discloses “The system of claim 1” [See rejection to claim 1 above], wherein the plurality of devices includes one or more chiplets coupled via the IOD to implement a disaggregated hardware resource accessible by a host processor via the IOD (see paragraph 00148).
4. As per claims 3 and 15, Dykema discloses wherein the IOD is configured to perform a data operation on data transferred along a data path defined by the interconnects (see paragraph 0156).
5. As per claim 4, Dykema discloses wherein the data operation includes encryption or compression of the data prior to transferring the data out of the IOD (see paragraph 0026 teaching CGRA, which uses compression, for example, dictionary-based compression or multicasting and bit-map encoding).
6. As per claim 6, Dykema discloses wherein the programmable core is configured to control access to the physical memory by the plurality of devices according to a reconfigurable quality-of-service policy of the at least one reconfigurable policy or a reconfigurable arbitration policy (see paragraph 0111) of the at least one reconfigurable policy, wherein the physical memory is external to the IOD (see fig. 1B).
7. As per claim 10, Dykema discloses wherein the IOD is configured to: receive a signal from a first device of the plurality of devices; and perform of an operation in response to receipt of the signal (see paragraph 0139).
8. As per claim 12, Dykema discloses wherein the IOD is configured to compose one or more of the plurality of devices into a configuration that implements a virtual hardware resource for executing a workload (see paragraph 0105).
9. As per claim 13, Dykema discloses wherein the IOD is configured to provide a root-of-trust for composition of the plurality of devices to implement the virtual hardware resource (see paragraph 0134).
10. As per claim 14, Dykema discloses a method comprising: connecting, via reconfigurable interconnects of a programmable fabric (interconnection fabrics, as discloses in paragraph 0054, 0055) included in an input/output die (IOD) (TCC 116 combined with fabrics 124 of fig. 1B, as discloses in paragraph 0087), a first combination (a first pair, segment, set, as disclose in paragraphs 0132 or 0139) of a plurality of devices [IO devices 460 combined with associated, respective attached components, of connected RPs, as discloses in paragraph 0148; see paragraph 0055, which discloses “a connection route between RPs can include one or more interconnection fabrics, or paths through interconnection fabrics, coupling a pair of RPs (and/or, a set of RPs more than 2). Interconnection fabrics included in a communications route between particular RPs can include, for example, particular ALNs, TLNs, or sub-arrays of an ALN or TLN; particular switches and/or ports of switches, of an ALN or TLN; and/or other particular other networks, such as Ethernets and InfiniBand networks. A connection route between RPs can include interconnection interfaces, such as I/O buses, data/memory buses, I/O links, network interfaces, and so forth, that can connect RPs directly to each other, can RPs to an interconnection fabric, and/or can connect interconnection fabrics intervening between RPs” and paragraph 0141, which discloses “Computer 410 can be a host processor, runtime processor, and/or RP of an RDS”] according to a first topology (complete RP interconnection topology, as discloses in paragraph 0139) of the programmable fabric (see paragraph 0139, which discloses “similar to RPs within a node having a feedback path between RPs, segments of an internodal RP topology can have feedback paths from a successor segment to a predecessor segment, among the totality of intranodal segments of the complete RP interconnection topology required in operation 302. Such a feedback path among segments can form, for example, another ring topology among a set of segments within the totality of segments of the complete RP interconnection topology. Operation 320 can include the TCC determining lowest cost communications routes to form feedback paths between particular segments of a larger RP interconnection topology, and the TCC can do so based on the node connections costs as described for operations 314 and 318”); reconfiguring the reconfigurable interconnects to connect a second combination of the plurality of devices according to a second topology (another ring topology, as discloses in paragraph 0139) of the programmable fabric (see paragraphs 0132 and 0139); and adjusting (see paragraph 0116, which discloses sorting routes, costs) at least one reconfigurable policy (a connection cost, as discloses in paragraph 0074) for scheduling memory access operations by the plurality of devices to a physical memory (memory 430, as discloses in paragraph 0153) based on the second topology, the at least one reconfigurable policy implemented by a programmable core included in the IOD [see paragraph 0057, which discloses “a connections-optimized RP configuration can correspond, for example, to a highest performance communications route (hereinafter, for brevity, “route”) coupling RPs executing dataflow workers within a worker logical topology (e.g., a DPW ring). To determine a connections-optimized RP configuration, a TCC can determine – retrieve, such as from a hardware description of an RDS, or a database, or, alternatively, can compute – “connection costs”. In implementations connections costs can be based on communication metrics, which can comprise, for example, a shortest route (e.g., number of hops, or overall latency), a lowest data transfer latency, a highest data transfer bandwidth, utilization of shared interconnects (e.g., shared interconnects to an interconnection fabric), and/or utilization of interconnection fabrics, associated with communications routes among the RPs” or paragraph 0068, which discloses “to illustrate further, an RDS can allocate some or all of RPs 102 of node 100 to execute dataflow workers configured in a worker logical topology. Using, again, the example of AllReduce, a preferred logical topology of dataflow workers to execute the application can be a DPW ring. In a case in which only RPs of node 100 are allocated, TCC 110 can configure the allocated RPs to form a complete, intranodal ring of RPs, within node 100, corresponding to a dataflow workers configured in the DPW ring. TCC 110 can compute intranodal connection costs associated with routes between any pair of RPs of node 100 within node 100 and/or through fabric 106. The intranodal connection costs can comprise, or correspond to, for example, topological and/or performance characteristics of interconnects 108 that can couple the RPs to fabric 106 and/or to a route through fabric 106 between a pair of RPs”].
11. As per claim 24, Dykema discloses wherein the multiple network topologies connect different combinations of the plurality of devices (see paragraph 0139).
12. As per claim 25, Dykema discloses wherein the programmable core is configured to update a memory bandwidth assigned to a particular device of the plurality of devices (see paragraphs 0097 and 0116).
13. As per claim 26, Dykema discloses wherein the at least one reconfigurable policy is dynamically adjusted during execution of a workload based on a phase (note, claim language doesn’t disclose what is a ‘phase’) of the workload being executed (see paragraphs 0097 and 0116).
14. As per claim 27, Dykema discloses wherein the at least one reconfigurable policy is
configured to schedule the memory access operations based one or more of workload phases, workload characteristics, a hardware resource configuration implemented by the programmable fabric, observed or expected memory access patterns, or quality-of-service considerations (see paragraphs 0097 and 0111).
15. As per claim 28, Dykema discloses wherein the programmable core is configured to arbitrate, in accordance with the at least one reconfigurable policy, memory access requests from the plurality of devices to bias memory access toward a particular device of the plurality of devices based on characteristics of workloads executed by the plurality of devices (see paragraph 0116, which discloses sorting routes, costs).
16. As per claim 29, Dykema discloses wherein adjusting the at least one reconfigurable policy includes changing the at least one reconfigurable policy from a first reconfigurable policy to a second reconfigurable policy based on one or more of the reconfiguration from the first topology to the second topology or a characteristic of a workload executed by the plurality of devices. (see paragraphs 0097 and 0111).
Claim Rejections - 35 USC § 103
17. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
18. Claims 7, 9, 11 and 17 are rejected under 35 U.S.C. 103(a) as being unpatentable over Dykema et al. (US pub. # 2023/0229624), hereinafter, “Dykema”, in view of Hammarlund et al. (US pub. # 2023/0058989), hereinafter, “Hammarlund”.
19. As per claim 7, Dykema discloses “The system of claim 1” [See rejection to claim 1 above] but fails to expressly discloses wherein the programmable core is configured to prefetch data from the physical memory according to a reconfigurable prefetching policy of the at least one reconfigurable policy.
Hammarlund discloses wherein the programmable core is configured to prefetch data from the physical memory according to a reconfigurable prefetching policy of the at least one reconfigurable policy (see paragraph 0151).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Hammarlund’s teaching of an integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers configured to support scaling of a system using a unified memory architecture, into Dykema’s teaching of a computer-implemented method comprises a topological communications configurator (TCC) of a computing system determining a connections-optimized configuration of processors among compute nodes of the system, for the ability/benefit of integrate a variety of system hardware components into a single silicon die that formerly implemented as discrete silicon components.
20. As per claim 9, Dykema discloses “The system of claim 1” [See rejection to claim 1 above] but fails to expressly discloses wherein the programmable core is configured to manage address translation service (ATS) requests from the plurality of devices according to a reconfigurable ATS policy of the at least one reconfigurable policy.
Hammarlund discloses wherein the programmable core is configured to manage address translation service (ATS) requests from the plurality of devices according to a reconfigurable ATS policy of the at least one reconfigurable policy (see paragraph 0215).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Hammarlund’s teaching of an integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture, into Dykema’s teaching of a computer-implemented method comprises a topological communications configurator (TCC) of a computing system determining a connections-optimized configuration of processors among compute nodes of the system, for the ability/benefit of integrate a variety of system hardware components into a single silicon die that formerly implemented as discrete silicon components.
21. As per claims 11 and 17, Dykema discloses “The system of claim 10” [See rejection to claim 10 above], but fails to expressly discloses wherein the first device of the plurality of devices is a first accelerator and a second device of the plurality of devices is a second accelerator, wherein the operation includes enqueuing a task in a task queue of the second accelerator in response to the receipt of the signal from the first accelerator.
Hammarlund discloses wherein the first device of the plurality of devices (peripherals D144A and D144B of figs. 45 and 46) is a first accelerator and a second device of the plurality of devices is a second accelerator [see paragraph 0092, which discloses “for example, an SOC may include one or more general purpose processor cores, one or more graphics processing units, and one or more other peripheral devices (such as application-specific accelerators, I/O interfaces, or other types of devices) distinct from the processor cores and graphics processing units. The SOC may further include one or more memory controller circuits configured to interface with system memory, as well as an interconnect fabric configured to provide communication between the memory controller circuit(s), the processor core(s), the graphics processing unit(s), and the peripheral device(s)”], wherein the operation includes enqueuing a task in a task queue of the second accelerator in response to the receipt of the signal from the first accelerator (see paragraph 0108, which discloses “thus, there may be one or more levels of cache between the processor cores, graphics processing units, peripheral devices, and the system memory. The one or more memory controller circuits 22A-22m may include respective memory caches interposed between the interconnect fabric and the system memory, wherein the respective memory caches are one of the one or more levels of cache”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Hammarlund’s teaching of an integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture, into Dykema’s teaching of a computer-implemented method comprises a topological communications configurator (TCC) of a computing system determining a connections-optimized configuration of processors among compute nodes of the system, for the ability/benefit of integrate a variety of system hardware components into a single silicon die that formerly implemented as discrete silicon components.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-4, 6-7, 9-14, 17, 19 and 24-29 have received a final action on the merits.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
