DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
Applicant's arguments filed on 03/30/2026 with respect to claims 1-4, 6-14, 17, 19, 22 and 24-27 have been fully considered and found to be persuasive and prosecution is therefore reopened.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 1-4, 6, 8, 10, 12-14, 19, 22 and 24-27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Srivastava et al. (US pub. # 2024/0264965), hereinafter, “Srivastava”.
2. As per claims 1 and 19, Srivastava discloses a system (PCIe interface 200 of fig. 2) comprising: an input/output die (IOD) (root complex 204 and processor 202 combined; see paragraph 0038, which discloses “the root complex 204 is implemented in the same IC device that includes the processor 202. A root complex 204 may support multiple PCIe ports”) that couples a plurality of devices (endpoint devices 210 and 212A-212N) (see paragraph 0038); a programmable fabric (root complex 204) included in the IOD (see paragraph 0038), the programmable fabric having interconnects (links 222 combined with PCIe ports) that are reconfigurable for connecting the plurality of devices according to multiple network topologies (with respect to ‘topologies’, see paragraph 0040, which teaches PCIe bus protocols, point-to-point, root, full-duplex) of the programmable fabric (see paragraph 0041, which discloses “each of the links 222 in the bus of FIG. 2 may be reconfigured during operation of the apparatus 122 to accommodate changes in bandwidth consumption by the endpoints 210, 212A-N, the root complex 204, the processor 202, and/or the memory subsystem 208….. According to aspects of this disclosure, the lanes may be reconfigured to change the direction of wires within the lanes, and thus change the bandwidth available in the transmit and receive directions on each of the links 222. The lane configuration may be changed during operation of the bus interface based on changing uses of the bus”); and a programmable core (processor 202) included in the IOD, the programmable core configured to implement at least one reconfigurable policy (bandwidth) for controlling access to a physical memory (memory subsystem 208) by the plurality of devices [see paragraph 0041, which discloses “each of the links 222 in the bus of FIG. 2 may be reconfigured during operation of the apparatus 122 to accommodate changes in bandwidth consumption by the endpoints 210, 212A-N, the root complex 204, the processor 202, and/or the memory subsystem 208” and paragraph 0060, which discloses “as described in the example above, reconfiguring the bus for data transfer to a storage device may be useful when a large data file is queued for reading or writing to the storage device to decrease the amount of time the link is out of low-power state to perform the transfer. As another example, a network interface, such as a wireless modem, may have changing bandwidth requirements, such as when a large file is transmitted to a cloud server (which involves a large transmit operation from memory to the modem) or when a video is downloaded from the Internet (which involves a large receive operation from the modem to the storage device)”].
3. As per claim 2, Srivastava discloses “The system of claim 1” [See rejection to claim 1 above], wherein the plurality of devices includes one or more chiplets coupled via the IOD to implement a disaggregated hardware resource accessible by a host processor via the IOD (see paragraph 0039).
4. As per claims 3 and 15, Srivastava discloses wherein the IOD is configured to perform a data operation on data transferred along a data path defined by the interconnects (see paragraph 0060).
5. As per claim 4, Srivastava discloses wherein the data operation includes encryption or compression of the data prior to transferring the data out of the IOD (see paragraph 0010).
6. As per claim 6, Srivastava discloses wherein the programmable core is configured to control access to the physical memory by the plurality of devices according to a reconfigurable quality-of-service policy or a reconfigurable arbitration policy (see paragraph 0045), wherein the physical memory (memory subsystem 208) is external to the IOD (see fig. 2).
7. As per claim 8, Srivastava discloses wherein the programmable core is configured to schedule memory requests from the plurality of devices according to a reconfigurable scheduling policy (see paragraph 0057).
8. As per claim 10, Srivastava discloses wherein the IOD is configured to: receive a signal from a first device of the plurality of devices; and perform of an operation in response to receipt of the signal (see fig. 4B).
9. As per claim 12, Srivastava discloses wherein the IOD is configured to compose one or more of the plurality of devices into a configuration that implements a virtual hardware resource for executing a workload (see paragraph 0063).
10. As per claim 13, Srivastava discloses wherein the IOD is configured to provide a root-of-trust for composition of the plurality of devices to implement the virtual hardware resource (see paragraph 0033).
11. As per claim 14, Srivastava discloses a method comprising: connecting, via reconfigurable interconnects (links 222 combined with PCIe ports of root complex 204; see fig. 2) of a programmable fabric (root complex 204) included in an input/output die (IOD) (root complex 204 and processor 202 combined; see paragraph 0038, which discloses “the root complex 204 is implemented in the same IC device that includes the processor 202. A root complex 204 may support multiple PCIe ports”), a plurality of devices (endpoint devices 210 and 212A-212N) (see paragraph 0038) according to a topology of the programmable fabric (see paragraph 0041, which discloses “each of the links 222 in the bus of FIG. 2 may be reconfigured during operation of the apparatus 122 to accommodate changes in bandwidth consumption by the endpoints 210, 212A-N, the root complex 204, the processor 202, and/or the memory subsystem 208….. According to aspects of this disclosure, the lanes may be reconfigured to change the direction of wires within the lanes, and thus change the bandwidth available in the transmit and receive directions on each of the links 222. The lane configuration may be changed during operation of the bus interface based on changing uses of the bus”); and adjusting at least one reconfigurable policy (bandwidth) for controlling access to a physical memory by the plurality of devices, the at least one reconfigurable policy implemented by a programmable core included in the IOD [see paragraph 0041, which discloses “each of the links 222 in the bus of FIG. 2 may be reconfigured during operation of the apparatus 122 to accommodate changes in bandwidth consumption by the endpoints 210, 212A-N, the root complex 204, the processor 202, and/or the memory subsystem 208” and paragraph 0060, which discloses “as described in the example above, reconfiguring the bus for data transfer to a storage device may be useful when a large data file is queued for reading or writing to the storage device to decrease the amount of time the link is out of low-power state to perform the transfer. As another example, a network interface, such as a wireless modem, may have changing bandwidth requirements, such as when a large file is transmitted to a cloud server (which involves a large transmit operation from memory to the modem) or when a video is downloaded from the Internet (which involves a large receive operation from the modem to the storage device)”].
12. As per claim 22, Srivastava discloses further comprising: reconfiguring the reconfigurable interconnects to connect the plurality of devices according to a different topology (with respect to a ‘different topology’, see paragraph 0040, which teaches PCIe bus protocols, point-to-point, root, full-duplex) of the programmable fabric (see paragraph 0041).
13. As per claim 24, Srivastava discloses wherein the multiple network topologies include different data paths connecting different combinations of the plurality of devices (see paragraph 0040).
14. As per claim 25, Srivastava discloses wherein the programmable core is configured to update a memory bandwidth assigned to a particular device of the plurality of devices (see paragraph 0060).
15. As per claim 26, Srivastava discloses wherein the at least one reconfigurable policy is dynamically adjusted during execution of a workload based on a phase (note, claim language doesn’t disclose what is a ‘phase’) of the workload being executed (see paragraph 0060).
16. As per claim 27, Srivastava discloses wherein the programmable core is configured to reconfigure the at least one reconfigurable policy by updating how the plurality of devices access the physical memory based one or more of workload phases, workload characteristics, a hardware resource configuration implemented by the programmable fabric, observed or expected memory access patterns, or quality-of-service considerations (see paragraphs 0045 and 0060).
Claim Rejections - 35 USC § 103
17. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
18. Claims 7, 9, 11 and 17 are rejected under 35 U.S.C. 103(a) as being unpatentable over Srivastava et al. (US pub. # 2024/0264965), hereinafter, “Srivastava”, in view of Hammarlund et al. (US pub. # 2023/0058989), hereinafter, “Hammarlund”.
19. As per claim 7, Srivastava discloses “The system of claim 1” [See rejection to claim 1 above], but fails to expressly discloses wherein the programmable core is configured to prefetch data from the physical memory according to a reconfigurable prefetching policy.
Hammarlund discloses wherein the programmable core is configured to prefetch data from the physical memory according to a reconfigurable prefetching policy (see paragraph 0151).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Hammarlund’s teaching of an integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers configured to support scaling of a system using a unified memory architecture, into Srivastava’s teaching of a method for interconnecting components of an electronic device through a bus interface that supports dynamic link configuration for changing bandwidth requirements on a bus, for the ability/benefit of integrate a variety of system hardware components into a single silicon die that formerly implemented as discrete silicon components.
20. As per claim 9, Srivastava discloses “The system of claim 1” [See rejection to claim 1 above], but fails to expressly discloses wherein the programmable core is configured to manage address translation service (ATS) requests from the plurality of devices according to a reconfigurable ATS policy.
Hammarlund discloses wherein the programmable core is configured to manage address translation service (ATS) requests from the plurality of devices according to a reconfigurable ATS policy (see paragraph 0215).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Hammarlund’s teaching of an integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture, into Srivastava’s teaching of a method for interconnecting components of an electronic device through a bus interface that supports dynamic link configuration for changing bandwidth requirements on a bus, for the ability/benefit of integrate a variety of system hardware components into a single silicon die that formerly implemented as discrete silicon components.
21. As per claims 11 and 17, Srivastava discloses “The system of claim 10” [See rejection to claim 10 above], but fails to expressly discloses wherein the first device of the plurality of devices is a first accelerator and a second device of the plurality of devices is a second accelerator, wherein the operation includes enqueuing a task in a task queue of the second accelerator in response to the receipt of the signal from the first accelerator.
Hammarlund discloses wherein the first device of the plurality of devices (peripherals D144A and D144B of figs. 45 and 46) is a first accelerator and a second device of the plurality of devices is a second accelerator [see paragraph 0092, which discloses “for example, an SOC may include one or more general purpose processor cores, one or more graphics processing units, and one or more other peripheral devices (such as application-specific accelerators, I/O interfaces, or other types of devices) distinct from the processor cores and graphics processing units. The SOC may further include one or more memory controller circuits configured to interface with system memory, as well as an interconnect fabric configured to provide communication between the memory controller circuit(s), the processor core(s), the graphics processing unit(s), and the peripheral device(s)”], wherein the operation includes enqueuing a task in a task queue of the second accelerator in response to the receipt of the signal from the first accelerator (see paragraph 0108, which discloses “thus, there may be one or more levels of cache between the processor cores, graphics processing units, peripheral devices, and the system memory. The one or more memory controller circuits 22A-22m may include respective memory caches interposed between the interconnect fabric and the system memory, wherein the respective memory caches are one of the one or more levels of cache”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Hammarlund’s teaching of an integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture, into Srivastava’s teaching of a method for interconnecting components of an electronic device through a bus interface that supports dynamic link configuration for changing bandwidth requirements on a bus, for the ability/benefit of integrate a variety of system hardware components into a single silicon die that formerly implemented as discrete silicon components.
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-4, 6-14, 17, 19, 22 and 24-27 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov.
Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217- 91 97 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights