DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 05/16/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim(s) 18-20 is/are objected to because of the following informalities:
Claim 18 recites “and invalidating a cache line …” in lines 5-6. It should read “[[and]] invalidating a cache line …”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 1-17 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “to the other device” in line 3. This renders the claim unclear as there is insufficient antecedent basis for this limitation in the claim. Previous limitations recite a plurality for other devices. Previous limitation do not recite “an other device”. {for examinations purpose limitation will read as the “at least one” other device}
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites “N server devices”, “(N-1) receive light pipes”, “N-1 other server devices”. This renders the claim unclear as N is undefined. This same rejection applies to Claims 8-9, 12, 15-17.
All dependents are also rejected as having the same deficiencies as the claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0133873 Al (Williams) in view of US 2021/0374050 Al (Dropps).
Regarding Claim 1:
Williams teaches A host device of a multidevice system, comprising:
a network interface to an “at least one” other device on the ([0018] system 100 includes multiple processing units 102 that are coupled for communication to a system interconnect 104 for conveying address, data and control information between attached devices. These attached devices include not only processing units 102, but also a memory controller 106 providing an interface to a shared system memory 108.)
a decoder to receive a packet when the host device is a consumer, ([0051] At block 350, L1 STQ 127 issues an L_release request to L2 STQ 166 of L2 cache 130 via store bus 164. The L_release request includes, for example, an indication of the request type, the target address, and an identifier of the issuing thread. At block 352, L1 STQ 127 then awaits receipt from L2 cache 130 of an acknowledgement (ACK) of the L_release request, as discussed below with reference to block 478 of FIG. 4C.)
wherein the network interface is to send an acknowledgement (ACK) or negative acknowledgement (NACK) in response to the packet; ([0061] After the L_release request is processed by the RC machines 142, L2 STQ 166 sends an acknowledgement (ACK) to L1 STQ 127 to confirm termination of the protection window, as discussed above with reference to block 352 of FIG. 3B (block 478).)
and hardware to invalidate a cache line of a local copy of a shared memory in response to receipt of the packet ([0044] If the instruction executed at block 302 was a LARX instruction, LD unit 128 performs the processing depicted at block 306 and following blocks. [0045] At block 306, LD unit 128 determines whether or not the load target address of the LARX instruction resides in LI cache 126. If so, LD unit 128 invalidates the cache line containing the load target address in LI cache 126 (block 308).)
and write an updated copy of the cache line into the local copy of the shared memory as the updated copy of the cache line is processed from the ([0046]-[0048] In response to receipt of the requested cache line, LD unit 128 transfers the data word(s) associated with the load target address into a core register 123 and allocates the requested cache line in L1 cache 126 (block 328).) The load target address is received, then mapped to the cache.
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches, in the same field of endeavor, on methods to reduce latency and bandwidth consumption in systems by grouping multiple cache line request messages, Abstract.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 2:
Williams (as modified by Dropps) teaches the invention of claim 1 as described.
Williams teaches wherein the ([0018] Fig 1, system 100 includes multiple processing units 102 (including at least processing units 102a-102b) for processing data and instructions. Processing units 102 are coupled for communication to a system interconnect 104 for conveying address, data and control information between attached devices. Network Interfaces for transmit/receive: [0021] load-reserve and store-conditional requests may be transmitted from a processor core 120 to the shared memory system to initiate data accesses. [0051][0061] Fig 3C & Fig 4B, send/receive ACK.)
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 3:
Williams (as modified by Dropps) teaches the invention of claim 1 as described.
Williams teaches wherein the host device is to register as a consumer of the other devices, and the other devices are to register as consumers of the host device. ([0018] Fig 1, system 100 includes multiple processing units 102 (including at least processing units 102a-102b) for processing data and instructions. Processing units 102 are coupled for communication to a system interconnect 104 for conveying address, data and control information between attached devices. Network Interfaces for transmit/receive: [0021] load-reserve and store-conditional requests may be transmitted from a processor core 120 to the shared memory system to initiate data accesses. [0051][0061] Fig 3C & Fig 4B, send/receive ACK.) Devices are connected as consumers (receivers) of each other.
Regarding Claim 4:
Williams (as modified by Dropps) teaches the invention of claim 1 as described.
Williams teaches wherein the hardware comprises: an address decoder to snoop packets for address information, and trigger invalidation of the cache line in response to the address information. ([0025] L2 cache 130 further includes a number of snoop state machines (SN machine) 144a-144n for servicing memory access and other requests … any SN machine 144 or RC machine 142 can signal the invalidation of a cache line to processor core 120. [0074] Referring now to the request servicing subprocess, … in order to dispatch a SN machine 144, a SN machine 144 must be available (i.e., in the idle state) and no RC machine 146 or SN machine 144 can be busy servicing a request having a target cache line address matching that specified by the snooped request.)
Regarding Claim 5:
Williams (as modified by Dropps) teaches the invention of claim 1 as described.
Williams teaches wherein the hardware comprises: a cache controller for the local copy of the shared memory, the cache controller to invalidate the cache line in response to receipt of the packet, and to write the updated copy of the cache line into the local copy of the shared memory. ([0068] RC machine 142 obtains authority to modify the target cache line and, if necessary, a copy of the target cache line from another cache hierarchy or memory controller 106 by issuing one or more requests on system interconnect 104 (block 612). At block 614, the RC machine 142 again checks whether or not the issuing hardware thread has a valid reservation for the store target address of the STCX request. [0069] Block 620 illustrates RC machine 142 updating the target cache line in L2 storage array and directory 140 with the store data of the STCX request. RC machine 142 additionally returns a pass indication to processor core 120 via pass/fail bus 17 4 to report successful update of the L2 cache 130 (block 622).)
Regarding Claim 6:
Williams (as modified by Dropps) teaches the invention of claim 1 as described.
Williams teaches wherein the packet comprises a first packet of a multiple cache line message indicating multiple cache lines to update, and wherein the hardware is to invalidate the multiple cache lines in response to the first packet, and write updated copies of the multiple cache lines as the multiple cache lines are processed from the ([0024] FIG. 1, L2 cache 130 contains a storage array and directory 140 that store cache lines of instructions and data in association with their respective memory addresses and coherence states. [0069] Block 620 illustrates RC machine 142 updating the target cache line in L2 storage array and directory 140 with the store data of the STCX request. RC machine 142 additionally returns a pass indication to processor core 120 via pass/fail bus 17 4 to report successful update of the L2 cache 130 (block 622).)
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 7:
Williams teaches A network system, comprising: an ([0018] system 100 includes multiple processing units 102 that are coupled for communication to a system interconnect 104 for conveying address, data and control information between attached devices. These attached devices include not only processing units 102, but also a memory controller 106 providing an interface to a shared system memory 108.)
the single transmit light pipe to send a packet to N-1 other server devices as a producer in response to locking a cache line of data in the local copy of the shared memory, ([0051] At block 350, L1 STQ 127 issues an L_release request to L2 STQ 166 of L2 cache 130 via store bus 164. The L_release request includes, for example, an indication of the request type, the target address, and an identifier of the issuing thread. At block 352, L1 STQ 127 then awaits receipt from L2 cache 130 of an acknowledgement (ACK) of the L_release request, as discussed below with reference to block 478 of FIG. 4C.)
and the (N-1) receive light pipes to receive messages from the N-1 other server devices as a consumer of shared messages from the N-1 other server devices. ([0018] Fig 1, system 100 includes multiple processing units 102 (including at least processing units 102a-102b) for processing data and instructions. Processing units 102 are coupled for communication to a system interconnect 104 for conveying address, data and control information between attached devices. Network Interfaces for transmit/receive: [0021] load-reserve and store-conditional requests may be transmitted from a processor core 120 to the shared memory system to initiate data accesses. [0051][0061] Fig 3C & Fig 4B, send/receive ACK.) Devices are connected as consumers (receivers) of each other.
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 8:
Williams (as modified by Dropps) teaches the invention of claim 7 as described.
Williams teaches wherein the network interface to the ([0018] Fig 1, system 100 includes multiple processing units 102 (including at least processing units 102a-102b) for processing data and instructions. Processing units 102 are coupled for communication to a system interconnect 104 for conveying address, data and control information between attached devices. Network Interfaces for transmit/receive: [0021] load-reserve and store-conditional requests may be transmitted from a processor core 120 to the shared memory system to initiate data accesses. [0051][0061] Fig 3C & Fig 4B, send/receive ACK.)
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 9:
Williams (as modified by Dropps) teaches the invention of claim 7 as described.
Williams teaches wherein the N server devices are to register with each other as consumers of shared messages from the N-1other server devices. ([0018] Fig 1, system 100 includes multiple processing units 102 (including at least processing units 102a-102b) for processing data and instructions. Processing units 102 are coupled for communication to a system interconnect 104 for conveying address, data and control information between attached devices. Network Interfaces for transmit/receive: [0021] load-reserve and store-conditional requests may be transmitted from a processor core 120 to the shared memory system to initiate data accesses. [0051][0061] Fig 3C & Fig 4B, send/receive ACK.) Devices are connected as consumers (receivers) of each other.
Regarding Claim 10:
Williams (as modified by Dropps) teaches the invention of claim 7 as described.
Williams teaches wherein the packet comprises a first packet of a multiple cache line message indicating multiple cache lines to update, and wherein the consumers are to invalidate the multiple cache lines in response to the first packet, and write updated copies of the multiple cache lines as the multiple cache lines are processed from the ([0024] FIG. 1, L2 cache 130 contains a storage array and directory 140 that store cache lines of instructions and data in association with their respective memory addresses and coherence states. [0069] Block 620 illustrates RC machine 142 updating the target cache line in L2 storage array and directory 140 with the store data of the STCX request. RC machine 142 additionally returns a pass indication to processor core 120 via pass/fail bus 17 4 to report successful update of the L2 cache 130 (block 622).)
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 11:
Williams (as modified by Dropps) teaches the invention of claim 7 as described.
Williams teaches wherein the network interface comprises: a decoder to receive a packet on one of the receive light pipes, wherein the network interface is to send an acknowledgement (ACK) or negative acknowledgement (NACK) in response to the packet on the transmit light pipe. ([0061] After the L_release request is processed by the RC machines 142, L2 STQ 166 sends an acknowledgement (ACK) to L1 STQ 127 to confirm termination of the protection window, as discussed above with reference to block 352 of FIG. 3B (block 478).)
Regarding Claim 12:
Williams (as modified by Dropps) teaches the invention of claim 11 as described.
Williams teaches wherein the N server devices comprise: hardware to invalidate a cache line of the local copy of the shared memory in response to receipt of the packet ([0044] If the instruction executed at block 302 was a LARX instruction, LD unit 128 performs the processing depicted at block 306 and following blocks. [0045] At block 306, LD unit 128 determines whether or not the load target address of the LARX instruction resides in LI cache 126. If so, LD unit 128 invalidates the cache line containing the load target address in LI cache 126 (block 308).)
and write an updated copy of the cache line into the local copy of the shared memory as the updated copy of the cache line is processed from the ([0046]-[0048] In response to receipt of the requested cache line, LD unit 128 transfers the data word(s) associated with the load target address into a core register 123 and allocates the requested cache line in L1 cache 126 (block 328).) The load target address is received, then mapped to the cache.
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 13:
Williams (as modified by Dropps) teaches the invention of claim 12 as described.
Williams teaches wherein the hardware comprises: an address decoder to snoop packets for address information, and trigger invalidation of the cache line in response to the address information. ([0025] L2 cache 130 further includes a number of snoop state machines (SN machine) 144a-144n for servicing memory access and other requests received from other processing units 102 via system interconnect 104 and snoop bus 170. SN machines 144 and RC machines 142 are each connected to a back-invalidation bus 172 by which any SN machine 144 or RC machine 142 can signal the invalidation of a cache line to processor core 120.)
Regarding Claim 14:
Williams (as modified by Dropps) teaches the invention of claim 12 as described.
Williams teaches wherein the hardware comprises: a cache controller for the local copy of the shared memory, the cache controller to invalidate the cache line in response to receipt of the packet, ([0044] If the instruction executed at block 302 was a LARX instruction, LD unit 128 performs the processing depicted at block 306 and following blocks. [0045] At block 306, LD unit 128 determines whether or not the load target address of the LARX instruction resides in LI cache 126. If so, LD unit 128 invalidates the cache line containing the load target address in LI cache 126 (block 308).)
and to write the updated copy of the cache line into the local copy of the shared memory. ([0046]-[0048] In response to receipt of the requested cache line, LD unit 128 transfers the data word(s) associated with the load target address into a core register 123 and allocates the requested cache line in L1 cache 126 (block 328).) The load target address is received, then mapped to the cache.
Regarding Claim 17:
Williams (as modified by Dropps) teaches the invention of claim 7 as described.
Williams teaches wherein, in response to any of the N server devices obtaining a data lock on a cache line of the shared memory, the other server devices will stall during execution at the cache line with the data lock until the cache line is updated and the data lock is released. ([0035]-[0040] With reference now to FIG. 2B, there is illustrated a second exemplary instruction sequence 210 that employs load-reserve and store-conditional instructions to coordinate execution of a critical section of a multithreaded program. As indicated, instruction sequence 210 includes, in program order, a polling instruction sequence 212, lock acquisition sequence 214, critical section 216, and lock release sequence 218.)
Regarding Claim 18:
Williams teaches A method for memory sharing, comprising:
receiving a packet over an (ie. release) to a shared memory by one of multiple other nodes that share the shared memory; ([0051] At block 350, L1 STQ 127 issues an L_release request to L2 STQ 166 of L2 cache 130 via store bus 164. The L_release request includes, for example, an indication of the request type, the target address, and an identifier of the issuing thread. At block 352, L1 STQ 127 then awaits receipt from L2 cache 130 of an acknowledgement (ACK) of the L_release request, as discussed below with reference to block 478 of FIG. 4C.)
sending an acknowledgement (ACK) or negative acknowledgement (NACK) in response to the packet; ([0061] After the L_release request is processed by the RC machines 142, L2 STQ 166 sends an acknowledgement (ACK) to L1 STQ 127 to confirm termination of the protection window, as discussed above with reference to block 352 of FIG. 3B (block 478).)
and invalidating a cache line of a local copy of the shared memory in response to receipt of the packet; ([0044] If the instruction executed at block 302 was a LARX instruction, LD unit 128 performs the processing depicted at block 306 and following blocks. [0045] At block 306, LD unit 128 determines whether or not the load target address of the LARX instruction resides in LI cache 126. If so, LD unit 128 invalidates the cache line containing the load target address in LI cache 126 (block 308).)
and writing an updated copy of the cache line into the local copy of the shared memory as the updated copy of the cache line is processed from the ([0046]-[0048] In response to receipt of the requested cache line, LD unit 128 transfers the data word(s) associated with the load target address into a core register 123 and allocates the requested cache line in L1 cache 126 (block 328).) The load target address is received, then mapped to the cache.
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 19:
Williams (as modified by Dropps) teaches the invention of claim 18 as described.
Williams teaches wherein the ([0018] Fig 1, system 100 includes multiple processing units 102 (including at least processing units 102a-102b) for processing data and instructions. Processing units 102 are coupled for communication to a system interconnect 104 for conveying address, data and control information between attached devices. Network Interfaces for transmit/receive: [0021] load-reserve and store-conditional requests may be transmitted from a processor core 120 to the shared memory system to initiate data accesses. [0051][0061] Fig 3C & Fig 4B, send/receive ACK.)
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Regarding Claim 20:
Williams (as modified by Dropps) teaches the invention of claim 18 as described.
Williams teaches wherein the packet comprises a first packet of a multiple cache line message, and wherein invalidating the cache line comprises invalidating multiple cache lines in response to the first packet, ([0044] If the instruction executed at block 302 was a LARX instruction, LD unit 128 performs the processing depicted at block 306 and following blocks. [0045] At block 306, LD unit 128 determines whether or not the load target address of the LARX instruction resides in LI cache 126. If so, LD unit 128 invalidates the cache line containing the load target address in LI cache 126 (block 308).)
and writing updated copies of the multiple cache lines as the multiple cache lines are processed from the ([0046]-[0048] In response to receipt of the requested cache line, LD unit 128 transfers the data word(s) associated with the load target address into a core register 123 and allocates the requested cache line in L1 cache 126 (block 328).) The load target address is received, then mapped to the cache.
Williams teaches on semiconductors, processor and bus connections ([0018], [0076][0077]). However, Williams is silent that the connections between these elements are optical.
Dropps teaches on utilizing optical communication links/connections. ([0091] transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave and infrared data communications.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams per Dropps to include utilizing optical communication links/connections. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with various architectures and connections.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0133873 Al (Williams) in view of US 2021/0374050 Al (Dropps) further in view of US 8095617 B2 (Johnsen).
Regarding Claim 15:
Williams (as modified by Dropps) teaches the invention of claim 7 as described.
Williams teaches on multiple processing units ([0019]) and RC machines ([0025]). However, Williams (as modified by Dropps) is silent on wherein the N server devices comprise blade servers.
Johnsen teaches, in the same field of endeavor, on managing operations in a first compute node of a multi-computer system, Abstract.
Johnsen teaches wherein the N server devices comprise blade servers. (Col 3-4, ln 49-53, 10-12, Compute Node--refers to a computer system having one or more processors (or CPUs) and memories. A Compute Node may have a single processor (which may be single core or multi-core) or may have a plurality of processors. One example of a Compute Node is a blade server. The cluster comprises one or more racks 106 each comprising 4 blade server chassis' which each comprise a plurality of blade servers (compute nodes) 102.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams (as modified by Dropps) by modifying Williams per Johnsen to include wherein the N server devices comprise blade servers. This would have been advantageous as discussed above, as it would allow the modified system to provide flexible implementations in systems with varied network elements/devices.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0133873 Al (Williams) in view of US 2021/0374050 Al (Dropps) further in view of US 2023/0058989 Al (Hammarlund).
Regarding Claim 16:
Williams (as modified by Dropps) teaches the invention of claim 7 as described.
Williams teaches on host bridges and memory controllers ([0018]). However, Williams (as modified by Dropps) is silent on wherein one of the N server devices is designated as a primary node and the other server devices are secondary nodes, wherein the primary node first initializes its local copy of the shared memory, and the secondary nodes subsequently initialize their local copies of the shared memory based on messages from the primary node.
Hammarlund teaches, in the same field of endeavor, An integrated circuit (IC) including a plurality of processors and controllers configured to support scaling of the system using a unified memory architecture, Abstract.
Hammarlund teaches wherein one of the N server devices is designated as a primary node and the other server devices are secondary nodes, wherein the primary node first initializes its local copy of the shared memory, and the secondary nodes subsequently initialize their local copies of the shared memory based on messages from the primary node. ([0306] The primary shared (P) state, or "clean shared primary" state, may be the state in a coherent agent C14A-C14n that has a shared copy of the cache block but also has the responsibility to forward the cache block to another coherent agent based on a snoop forward request. The secondary shared (S) state, or "clean shared secondary" state, may be a state in a coherent agent C14A-C14n that has a shared copy of the cache block but is not responsible for providing the cache block if another coherent agent Cl4A-Cl4n has the cache block in primary shared state.)
It would have been have obvious to a person having ordinary skill in the art before the effective filing date, to modify Williams (as modified by Dropps) by modifying Williams per Hammarlund to include wherein one of the N server devices is designated as a primary node and the other server devices are secondary nodes, wherein the primary node first initializes its local copy of the shared memory, and the secondary nodes subsequently initialize their local copies of the shared memory based on messages from the primary node. This would have been advantageous as discussed above, as it would allow the modified system to provide fine-tuned control for the distribution of the cache copies.
Conclusion & Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RACHEL J HACKENBERG whose telephone number is (571)272-5417. The examiner can normally be reached 9am-5pm M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Glenton B Burgess can be reached at (571)272-3949. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RACHEL J HACKENBERG/Primary Examiner, Art Unit 2454
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