DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar (US 20220197819), in view of Gower (US 20110004709), further in view of Ziai (US 12204794).
Regarding Claim 1, Kumar teaches
An integrated circuit comprising: a first logic block that issues first read operations; first and second memory controller circuits; (Kumar [0011] In a pooled memory architecture, memory controllers may provide access to a multitude of remote dual inline memory modules (DIMMs) that connected through a particular interconnect. [0012] Memory pools can be unequally utilized as memory pool A can be overused relative to memory pools B-D. Latency can represent a time from when a request to read or write data is sent to a time when the data is received at a memory accessible by the requester or a time when the data is written to a target memory. [0029] Pooled memory controller 210 can be implemented as one or more of: programmable general-purpose or special-purpose microprocessors, field programmable gate arrays (FPGAs), digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.)
a load balancing multiplexer circuit that redirects a first one of the first read operations from the first memory controller circuit to the second memory controller circuit in response to receiving a first indication that the second memory controller circuit comprises first available memory bandwidth; (Kumar [0014] an orchestrator can perform load balancing of usage of multiple memory pools. [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices in a single memory pool to support requested network and memory bandwidth or network and memory bandwidth in excess of requested bandwidth. The orchestrator can balance memory access latency and network bandwidth by allocating memory capacity via interleaving across multiple pools. [0026] Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative) stored in various queues to attempt to satisfy an SLA associated with a process. There may be multiple instances of load balancers (e.g., one per queue). Pooled MC 210 can be separate from a local MC to local memory 230 or integrated with local MC to local memory 230.)
Kumar ([0057]) teaches switch and service mesh, Kumar does not teach multiplexer
However, Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Kumar-Gower does not teach
and a bank spreading circuit that causes each of the first read operations that is provided to a first memory circuit through the load balancing multiplexer circuit to access a different bank in the first memory circuit.
However, Ziai teaches and a bank spreading circuit that causes each of the first read operations that is provided to a first memory circuit to access a different bank in the first memory circuit. (Ziai Col. 5, lines 3-8: the memory device can reorder or otherwise group read operations and write operations to provide that such operations can be directed to multiple memory banks in a manner that optimizes the number of operations performed by each memory bank, without the computing device having to be involved in any such optimization. Col. 9, lines14-16: the ordering/transaction optimization circuit 113d can process those read/write commands 114)
Kumar, Gower and Ziai are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower and Ziai to modify the Kumar-Gower’s dynamic load balancing of the memory system with Ziai’s teaching. The motivation for doing so would be that (Ziai Col. 5, lines 7-8) optimizes the number of operations performed by each memory bank.
Regarding Claim 2, Kumar, Gower and Ziai teach
wherein the load balancing multiplexer circuit sends a second one of the first read operations to the first memory controller circuit in response to receiving a second indication that the first memory controller circuit comprises second available memory bandwidth. (Kumar [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices in a single memory pool to support requested network and memory bandwidth. The orchestrator can balance memory access latency and network bandwidth by allocating memory capacity via interleaving across multiple pools.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Regarding Claim 3, Kumar, Gower and Ziai teach
a second logic block that issues second read operations, wherein the load balancing multiplexer circuit sends the second read operations to the first memory controller circuit in response to receiving a second indication that the first memory controller circuit comprises second available memory bandwidth. (Kumar [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices in a single memory pool to support requested network and memory bandwidth. The orchestrator can balance memory access latency and network bandwidth by allocating memory capacity via interleaving across multiple pools.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Regarding Claim 4, Kumar, Gower and Ziai teach
wherein the first memory controller circuit transmits a second one of the first read operations to a second memory circuit, and wherein the second memory controller circuit transmits the first one of the first read operations to the first memory circuit. (Kumar [0011] In a pooled memory architecture, memory controllers may provide access to a multitude of remote dual inline memory modules (DIMMs) that connected through a particular interconnect. [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices [0026] Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative) stored in various queues to attempt to satisfy an SLA associated with a process.)
Regarding Claim 5, Kumar, Gower and Ziai teach
wherein the load balancing multiplexer circuit sends a write operation to the first memory controller circuit to store data in a second memory circuit and to the second memory controller circuit to store the data in the first memory circuit. (Kumar [0011] With memory pooling technologies, a server can utilize memory from multiple pools to memory address capacity requirements. [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices [0026] Pooled memory controller 210 can utilize queues 218 to buffer data before the data is sent to a memory pool. Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative) stored in various queues to attempt to satisfy an SLA associated with a process.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Regarding Claim 6, Kumar, Gower and Ziai teach
wherein the first memory controller circuit is coupled to the second memory circuit, and wherein the second memory controller circuit is coupled to the first memory circuit. (Kumar [0011] In a pooled memory architecture, memory controllers may provide access to a multitude of remote dual inline memory modules (DIMMs) that connected through a particular interconnect. [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices)
Regarding Claim 8, Kumar, Gower and Ziai teach
Kumar teaches the load balancing circuit (Kumar [0026] Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative) stored in various queues to attempt to satisfy an SLA associated with a process. There may be multiple instances of load balancers)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Kumar-Gower does not teach but Ziai teaches wherein the bank spreading circuit causes the first one of the first read operations to be provided to the different bank in the first memory circuit via the load balancing multiplexer circuit than a second one of the first read operations immediately preceding the first one of the first read operations. (Ziai Col. 5, lines 3-8: the memory device can reorder or otherwise group read operations and write operations to provide that such operations can be directed to multiple memory banks in a manner that optimizes the number of operations performed by each memory bank, without the computing device having to be involved in any such optimization.)
Kumar, Gower and Ziai are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower and Ziai to modify the Kumar-Gower’s dynamic load balancing of the memory system with Ziai’s teaching. The motivation for doing so would be that (Ziai Col. 5, lines 7-8) optimizes the number of operations performed by each memory bank.
Regarding Claim 9, Kumar, Gower and Ziai teach
a pooling circuit that causes a set of read requests to be provided to a memory device as a first group and a set of write requests to be provided to the memory device as a second group. (Kumar [0011] With memory pooling technologies, a server can utilize memory from multiple pools to memory address capacity requirements.)
Regarding Claim 10, Kumar teaches
A method for accessing first and second memory circuits, the method comprising: (Kumar [0011] In a pooled memory architecture, memory controllers may provide access to a multitude of remote dual inline memory modules (DIMMs) that connected through a particular interconnect.)
providing a first read operation through a load balancing multiplexer circuit to a first memory controller circuit for transmission to the first memory circuit; (Kumar [0026] Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative) stored in various queues to attempt to satisfy an SLA associated with a process. There may be multiple instances of load balancers (e.g., one per queue). Pooled MC 210 can be separate from a local MC to local memory 230 or integrated with local MC to local memory 230.)
and providing a second read operation through the load balancing multiplexer circuit to a second memory controller circuit for transmission to the second memory circuit based on a first indication that the second memory controller circuit comprises first available memory bandwidth. (Kumar [0014] an orchestrator can perform load balancing of usage of multiple memory pools. [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices in a single memory pool to support requested network and memory bandwidth or network and memory bandwidth in excess of requested bandwidth. The orchestrator can balance memory access latency and network bandwidth by allocating memory capacity via interleaving across multiple pools.)
read operations that is provided from a logic block to the first memory circuit (Kumar [0026] Pooled memory controller 210 can utilize queues 218 to buffer data before the data is sent to a memory pool. Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative) [0029] Pooled memory controller 210 can be implemented as one or more of: programmable general-purpose or special-purpose microprocessors) (i.e. microprocessor is a logic block issues read/write operation to memory circuit)
Kumar ([0057]) teaches switch and service mesh, Kumar does not teach multiplexer
However, Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Kumar-Gower does not teach
and causing each of third read operations that is provided from a logic block to the first memory circuit to access a different bank of addresses in the first memory circuit using a bank spreading circuit.
However, Ziai teaches and causing each of third read operations to access a different bank of addresses in the first memory circuit using a bank spreading circuit. (Ziai Col. 5, lines 3-8: the memory device can reorder or otherwise group read operations and write operations to provide that such operations can be directed to multiple memory banks in a manner that optimizes the number of operations performed by each memory bank, without the computing device having to be involved in any such optimization. Col. 9, lines14-16: the ordering/transaction optimization circuit 113d can process those read/write commands 114)
Kumar, Gower and Ziai are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower and Ziai to modify the Kumar-Gower’s dynamic load balancing of the memory system with Ziai’s teaching. The motivation for doing so would be that (Ziai Col. 5, lines 7-8) optimizes the number of operations performed by each memory bank.
Regarding Claim 13, Kumar, Gower and Ziai teach
Kumar teaches the first and the second read operations received from the load balancing multiplexer circuit; (Kumar [0014] an orchestrator can perform load balancing of usage of multiple memory pools.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Kumar-Gower does not teach but Ziai teaches performing memory interface optimizations; and providing the memory interface optimizations (Ziai Col. 5, lines 3-8: the memory device can reorder or otherwise group read operations and write operations to provide that such operations can be directed to multiple memory banks in a manner that optimizes the number of operations performed by each memory bank, without the computing device having to be involved in any such optimization.)
Kumar, Gower and Ziai are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower and Ziai to modify the Kumar-Gower’s dynamic load balancing of the memory system with Ziai’s teaching. The motivation for doing so would be that (Ziai Col. 5, lines 7-8) optimizes the number of operations performed by each memory bank.
Regarding Claim 15, Kumar, Gower and Ziai teach
Kumar-Gower does not teach but Ziai teaches causing a set of write requests to be provided to the first memory circuit as a group using a pooling circuit. (Ziai Col. 5, lines 3-8: the memory device can reorder or otherwise group read operations and write operations to provide that such operations can be directed to multiple memory banks in a manner that optimizes the number of operations performed by each memory bank, without the computing device having to be involved in any such optimization.)
Kumar, Gower and Ziai are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower and Ziai to modify the Kumar-Gower’s dynamic load balancing of the memory system with Ziai’s teaching. The motivation for doing so would be that (Ziai Col. 5, lines 7-8) optimizes the number of operations performed by each memory bank.
Claim(s) 7, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar (US 20220197819), in view of Gower (US 20110004709), further in view of Ziai (US 12204794), further in view of Diamant (US 10613977).
Regarding Claim 7, Kumar, Gower and Ziai teach
Kumar teaches the load balancing multiplexer circuit (Kumar [0014] an orchestrator can perform load balancing of usage of multiple memory pools.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Kumar-Gower-Ziai does not teach a bank cycling circuit that duplicates a write operation to generate duplicate write operations, sends each of the duplicate write operations to a different bank of addresses within a memory device
However, Diamant teaches a bank cycling circuit that duplicates a write operation to generate duplicate write operations, sends each of the duplicate write operations to a different bank of addresses within a memory device (Diamant Col. 34, lines 14-16:
a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses)
Kumar, Gower, Ziai and Diamant are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower, Ziai and Diamant to modify the Kumar-Gower-Ziai‘s dynamic load balancing of the memory system with Diamant’s teaching. The motivation for doing so would be that (Diamant Col. 34, lines 14-16) a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses.)
Regarding Claim 14, Kumar, Gower and Ziai teach
Kumar teaches within the first memory circuit or the second memory circuit through the load balancing multiplexer circuit (Kumar [0014] an orchestrator can perform load balancing of usage of multiple memory pools.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Kumar-Gower-Ziai does not teach duplicating a write operation to generate duplicate write operations using a bank cycling circuit; and sending each of the duplicate write operations to a different bank of addresses
However, Diamant teaches duplicating a write operation to generate duplicate write operations using a bank cycling circuit; and sending each of the duplicate write operations to a different bank of addresses (Diamant Col. 34, lines 14-16: a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses)
Kumar, Gower, Ziai and Diamant are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower, Ziai and Diamant to modify the Kumar-Gower-Ziai‘s dynamic load balancing of the memory system with Diamant’s teaching. The motivation for doing so would be that (Diamant Col. 34, lines 14-16) a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses.)
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar (US 20220197819), in view of Gower (US 20110004709), further in view of Diamant (US 10613977).
Regarding Claim 16, Kumar teaches
A circuit system comprising: first and second memory devices; first and second memory controller circuits; (Kumar [0011] In a pooled memory architecture, memory controllers may provide access to a multitude of remote dual inline memory modules (DIMMs) that connected through a particular interconnect.)
and a load balancing multiplexer circuit that sends a first copy of a first write operation to the first memory controller circuit to store a first copy of first data in the first memory device, (Kumar [0026] Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative) stored in various queues to attempt to satisfy an SLA associated with a process. There may be multiple instances of load balancers (e.g., one per queue). Pooled MC 210 can be separate from a local MC to local memory 230 or integrated with local MC to local memory 230.)
wherein the load balancing multiplexer circuit sends a duplicate copy of the first write operation to the second memory controller circuit to store a duplicate copy of the first data in the second memory device. (Kumar [0014] an orchestrator can perform load balancing of usage of multiple memory pools. [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices in a single memory pool to support requested network and memory bandwidth or network and memory bandwidth in excess of requested bandwidth. The orchestrator can balance memory access latency and network bandwidth by allocating memory capacity via interleaving across multiple pools.)
Kumar ([0057]) teaches switch and service mesh, Kumar does not teach multiplexer
However, Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Kumar-Gower does not teach a duplicate copy of the first write operation to store a duplicate copy of the first data
However, Diamant teaches a duplicate copy of (Diamant Col. 34, lines 14-16: a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses. Col. 5, lines 37-38: Staggered distribution of the transaction data can enable the data to be duplicated across banks in a memory)
Kumar, Gower and Diamant are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower and Diamant to modify the Kumar-Gower‘s dynamic load balancing of the memory system with Diamant’s teaching. The motivation for doing so would be that (Diamant Col. 34, lines 14-16) a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses.)
Regarding Claim 17, Kumar, Gower and Diamant teach
Kumar teaches wherein the first and the second memory controller circuits and the load balancing multiplexer circuit are in a first integrated circuit, wherein the first memory device is a second integrated circuit, and wherein the second memory device is a third integrated circuit. (Kumar [0031] Computing platform 310 can execute one or more processes 312 that utilize pooled memory controller 322 to access one or more memory pools 340-A to 340-C. Memory regions in one or more memory pools 340-A to 340-C can be allocated for access by one or more processes 312.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Regarding Claim 18, Kumar, Gower and Diamant teach
Kumar teaches wherein the load balancing multiplexer circuit provides a read operation to the second memory controller circuit for transmission to the second memory device based on an indication that the second memory controller circuit has available memory bandwidth. (Kumar [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices in a single memory pool to support requested network and memory bandwidth. The orchestrator can balance memory access latency and network bandwidth by allocating memory capacity via interleaving across multiple pools.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Regarding Claim 19, Kumar, Gower and Diamant teach
Kumar teaches wherein the load balancing multiplexer circuit sends a first copy of a second write operation to the first memory controller circuit to store a first copy of second data in the first memory device, (Kumar [0014] an orchestrator can perform load balancing of usage of multiple memory pools. [0026] Pooled memory controller 210 can utilize queues 218 to buffer data before the data is sent to a memory pool. Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative))
and wherein the load balancing multiplexer circuit sends a duplicate copy of the second write operation to the second memory controller circuit to store a duplicate copy of the second data in the second memory device. (Kumar [0014] an orchestrator can perform load balancing of usage of multiple memory pools. [0026] Pooled memory controller 210 can utilize queues 218 to buffer data before the data is sent to a memory pool. Interleaving and LB 220 can select memory access requests (e.g., read, write, administrative))
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Kumar-Gower does not teach but Diamant teaches a duplicate copy of the second write operation to store a duplicate copy of the second data (Diamant Col. 34, lines 14-16: a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses. Col. 5, lines 37-38: Staggered distribution of the transaction data can enable the data to be duplicated across banks in a memory)
Kumar, Gower and Diamant are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar, Gower and Diamant to modify the Kumar-Gower‘s dynamic load balancing of the memory system with Diamant’s teaching. The motivation for doing so would be that (Diamant Col. 34, lines 14-16) a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses.)
Regarding Claim 20, Kumar, Gower and Diamant teach
Kumar teaches wherein the load balancing multiplexer circuit provides a read operation to one of the first or the second memory controller circuits to access the first data from a respective one of the first or the second memory devices based on available memory bandwidth of the one of the first or the second memory controller circuits. (Kumar [0015] The orchestrator can request allocation of memory that is potentially interleaved among multiple memory pools or multiple memory devices in a single memory pool to support requested network and memory bandwidth. The orchestrator can balance memory access latency and network bandwidth by allocating memory capacity via interleaving across multiple pools.)
Kumar does not teach but Gower teaches multiplexer (Gower [0013] the memory hub controller may send a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.)
Kumar and Gower are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kumar and Gower to modify the Kumar ‘s dynamic load balancing of the memory system with Gower’s teaching of multiplexer. The motivation for doing so would be (Gower [0003]) enhancing the memory bandwidth available through a memory module of a memory system.
Response to Arguments
Applicant's arguments filed 01/05/2026 have been fully considered but they are not persuasive.
Applicant argues that the cited references do not disclose amended limitations. The Office disagrees.
First, for claim 1, applicant argues that Ziai in combination with Gower and Kumar do
not disclose "a first logic block that issues first read operations;" ... "and a bank spreading circuit that causes each of the first read operations that is provided to a first memory circuit through the load balancing multiplexer circuit to access a different bank in the first memory circuit" and that Ziai does not disclose or suggest that a bank spreading circuit causes each of the read operations issued by a logic block and provided to a memory circuit to access a different bank in the memory circuit. The Office submits that Kumar teaches load balancing circuit for memory devices to handle read/write operations and Kumar’s microprocessor is a logic block issues read/write operation and Ziai’s teaching of memory read/write operations can be directed to multiple memory banks is bank spreading (Ziai Col. 5, lines 3-8: the memory device can reorder or otherwise group read operations and write operations to provide that such operations can be directed to multiple memory banks in a manner that optimizes the number of operations performed by each memory bank, without the computing device having to be involved in any such optimization. Col. 9, lines14-16: the ordering/transaction optimization circuit 113d can process those read/write commands 114).
Next, for claim 10, applicant argues similar to claim 1.
Next, for claim 16, applicant argues that Kumar does not disclose or render obvious sending a first copy of a write operation to a first memory controller circuit to store a first copy of data in a first memory device and sending a duplicate copy of the write operation to a second memory controller circuit to store a duplicate copy of the data in a second memory device. The Office submits that Diamant teaches duplicating write operation and write data (Diamant Col. 34, lines 14-16: a write transaction can be duplicated into different sets of memory banks, and/or with different offset addresses. Col. 5, lines 37-38: Staggered distribution of the transaction data can enable the data to be duplicated across banks in a memory)
Applicant’s argument for dependent claims 2-9, 11-15 and 17-20 are based on their respective base independent claim 1, 10 and 16, which are addressed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WEI MA/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135