Prosecution Insights
Last updated: October 02, 2026
Application No. 18/215,752

HARDWARE ATTESTATION IN A MULTI-NETWORK INTERFACE DEVICE SYSTEM

Non-Final OA §102§112
Filed
Jun 28, 2023
Examiner
LWIN, MAUNG T
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
554 granted / 623 resolved
+28.9% vs TC avg
Strong +22% interview lift
Without
With
+21.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
17 currently pending
Career history
632
Total Applications
across all art units

Statute-Specific Performance

§101
12.4%
-27.6% vs TC avg
§103
31.5%
-8.5% vs TC avg
§102
13.6%
-26.4% vs TC avg
§112
35.5%
-4.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 623 resolved cases

Office Action

§102 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the application filed on 06/28/2023 and the preliminary amendment filed on 10/12/2023. Claims 1-20 are currently pending in this application. Claims 2, 9, 10 and 16 have been amended. Information Disclosure Statement The information disclosure statements (IDSs) submitted on 08/03/2023, 10/25/2024 and 01/03/2025 were filed. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner except for the documents, for which the copies of the documents are illegible. Examiner’s Note Applicants are suggested to include information from figure 3C with related text into the claims to provide a better condition for an allowance. Claim Objections Claims 2 and 10-14 are objected to because of the following informalities: Claim 2 recites “… to communicate with a attestation authority …”, which appears to be “… to communicate with an attestation authority …”; Claims 10-14 recite “The non-transitory computer-readable medium of claim 9 (or 10) …”; however, the claim 9 includes “At least one …”. Appropriate correction is required. Drawings The drawings are objected to because the text of figure 3B is illegible. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (B) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. Applicants are suggested review all claims for clarification (e.g., compatibility, capability issues) and some of the issues (not all because there are too many) are indicated below. Claim 1 recites: “An apparatus comprising: a network interface device comprising: a network interface, memory … and circuitry to: register the network interface device and …”, however, it is not clear whether the network interface device is registering itself or not – it is not clear to define a boundary of the limitations/components; “… based on selection as an attestation device by a management controller from among multiple candidate network interface devices, receive attestation information and perform attestation of one or more devices”, however, it is not clear: whether selection is performed by the network interface device or by the management controller (note: the management controller does not have any relationship with the claimed network interface device so that the process of the management controller does not have any patentable weight for the claimed apparatus); whether the management controller is located in the multiple candidate network interface devices or not; what are the multiple network interface devices candidate for; whether the multiple candidate network interface devices have any relationship with the claimed network interface device; whether all components (e.g., the interwork interface, memory, one or more processors and circuitry) of the network interface device perform the claimed functions (e.g., receiving and attestation) or not (or how the combination of them can process these functions); whether the one or more devices have any relationship with the network interface device to perform attestation process – or omitting necessary component/step which causes the limitations unclear. Claim 9 recites: “At least one non-transitory computer-readable medium … if executed by one or more processors, cause the one or more processor to: configure a management controller to select an attestation device … wherein the selected network interface device is to receive … and perform … one or more devices connected to a server”, however, it is not clear: whether claimed a plurality of non-transitory computer-readable medium, using a plurality of processors, perform configuration of the management controller or not – it is not clear to define a boundary of the limitations; whether the management controller has any structural relationship (e.g., connected, linked, etc.) with the plurality of (at least one) non-transitory computer-readable medium or not – omitting necessary component/step which causes the limitations unclear; how selecting the attestation device becomes the selected network interface device; whether the included functions (e.g., to receive and perform) are actually processing or not (e.g., the intended use or the reason for selection); whether the one or more devices have any relationship with the claimed non-transitory computer-readable medium to perform attestation process – or omitting necessary component/step which causes the limitations unclear. Claim 15 recites “A method comprising: configuring a controller to select an attestation device from among multiple candidate network interface devices wherein the selected network interface device is to receive … and perform … one or more devices connected to a server”, however, it is not clear: whether the configuration method is performed by the human (using a pen and paper or in mind) or not (note: if so or not including a machine, such as a computer, a hardware processor, etc. may have a 101 or an abstract idea issue); how selecting the attestation device becomes the selected network interface device; whether the included functions (e.g., to receive and perform) are actually processing or not (e.g., the intended use or the reason for selection); whether the one or more devices have any structural relationship with the controller or network interface device to perform attestation process – or omitting necessary component/step which causes the limitations unclear. Claims 2-8, 10-14 and 16-20 depend from the claim 1, 9 or 15, and are analyzed and rejected accordingly. Claims 2 and 3 recite “… to communicate with a attestation authority to determine if the circuitry is trusted” and “… the attestation authority comprises an attestation server”, however, it is not clear (1) how the circuitry can be determined if it is trusted – or omitting necessary component/step which causes the limitations unclear; (2) whether the attestation server has any structural relationship with the claimed apparatus or not – it is not clear to define a boundary of the limitation/terms. Claim 8 recites “… wherein the one or more devices comprise … a network interface device …”, however, it is not clear whether “a network interface device” is the same as “a network interface device” included in the claim 1 or not. Claims 10 and 16 recite “… to determine if the selected network interface device is trusted as a second attestation authority”, however, it is not clear how to determine (or compare) the selected network interface device with the second attestation authority. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sahita et al. (US 2021/0141658 A1). Note: for compact prosecution, teaching of Oliver et al. of US 2022/0141255 A1 is provided for the rejections. As per claim 1, Sahita teaches an apparatus (see figs. 1, 4) comprising: a network interface device comprising: a network interface, memory, one or more processors, and circuitry to: register the network interface device and based on selection as an attestation device by a management controller from among multiple candidate network interface devices, receive attestation information and perform attestation of one or more devices [figs. 1, 2; par. 0015, lines 1-15; par. 0020, lines 1-18; par. 0022, lines 1-8; par. 0025, lines 1-7 of Sahita teaches a network interface device (e.g., the network interface device/accelerator 104) comprising: a network interface, memory, one or more processors, and circuitry to: register the network interface device (e.g., initialized including authentication and initialization of firmware on the device) and based on selection as an attestation device (e.g., direct-assign the device) by a management controller from among multiple candidate network interface devices (e.g., other devices of fig. 1), receive attestation information (e.g., the attestation information or the measurement) and perform attestation of one or more devices]. As per claim 2, Sahita teaches the apparatus of claim 1. Sahita further teaches wherein the management controller is to communicate with a attestation authority to determine if the circuitry is trusted [figs. 1, 2; par. 0026, lines 1-8; claim 5 of page 6 of Sahita teaches wherein the management controller is to communicate with a attestation authority (e.g., the remote cloud tenant) to determine if the circuitry is trusted (e.g., to verify the virtual composed device is a trusted device)]. As per claim 3, Sahita teaches the apparatus of claim 2. Sahita further teaches wherein the attestation authority comprises an attestation server [figs. 1, 2; par. 0026, lines 1-8; claim 5 of page 6 of Sahita teaches wherein the attestation authority comprises an attestation server (e.g., the remote cloud tenant)]. For compact prosecution, see the teaching of Oliver et al. of US 2022/0141255 A1 for an attestation server with motivation of the modification in fig. 6, abstract; paras. 0002, 0003. As per claim 4, Sahita teaches the apparatus of claim 1. Sahita further teaches wherein the circuitry is to execute Linux mcheck() to perform verify one or more cores [figs. 1, 2, 4; par. 0016, lines 13-17; par. 0020, lines 1-18 of Sahita teaches wherein the circuitry is to execute Linux mcheck() to perform verify one or more cores (e.g., implementing a secure arbitration mode of the processor/CPU)]. For compact prosecution, see the teaching of Oliver et al. of US 2022/0141255 A1 for executing Linux performing integrity measurement of the core root of trust with motivation of the modification in paras. 0002, 0003, 0058 and 0068. As per claim 5, Sahita teaches the apparatus of claim 1. Sahita further teaches wherein communications between the management controller and the circuitry are secured based on Peripheral Component Interconnect express (PCle) or Compute Express Link (CXL) [fig. 1; par. 0019, lines 1-13 of Sahita teaches communications between the management controller and the circuitry are secured based on Peripheral Component Interconnect express (PCle) or Compute Express Link (CXL) (e.g., the secure data path using PCIe or CXL)]. As per claim 6, Sahita teaches the apparatus of claim 1. Sahita further teaches wherein the attestation information is associated with the one or more devices connected to a server and comprises device identifiers and firmware identifiers [par. 0017, lines 1-13; par. 0018, lines 1-3; par. 0026, lines 1-8 of Sahita teaches the attestation information is associated with the one or more devices (e.g., the composed device, etc.) connected to a server (e.g., the remote cloud tenant) and comprises device identifiers and firmware identifiers (e.g., the composed ID of the device including measurement of the firmware)]. As per claim 7, Sahita teaches the apparatus of claim 1. Sahita further teaches wherein the attestation information is provided by one or more local attestor cores associated with a central processing unit (CPU) complex or the network interface device [figs. 1, 4; par. 0017, lines 1-13; par. 0018, lines 1-3; par. 0029, lines 1-4 of Sahita teaches wherein the attestation information (e.g., the composed ID including attestation information) is provided by one or more local attestor cores associated with a central processing unit (CPU) complex (see fig. 1) or the network interface device (e.g., the network interface device/accelerator 104)]. As per claim 8, Sahita teaches the apparatus of claim 1. Sahita further teaches wherein the one or more devices comprise one or more of: a processor, a graphics processing unit (GPU), an accelerator, a network interface device, a memory device, or a storage device [fig. 1; par. 0015, lines 1-6 of Sahita teaches wherein the one or more devices comprise one or more of: a processor, a graphics processing unit (GPU), an accelerator, a network interface device, a memory device, or a storage device]. Claims 9-14 are medium claims that correspond to the (part of) apparatus claims 1-3 and 5-7, and are analyzed and rejected accordingly. Claims 15-20 are method claims that correspond to the (part of) apparatus claims 1-3 and 5-7, and are analyzed and rejected accordingly. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAUNG T LWIN whose telephone number is (571)270-7845. The examiner can normally be reached on Monday - Friday 10:00 am - 6:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Farid Homayounmehr can be reached on 571-272-3739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MAUNG T LWIN/Primary Examiner, Art Unit 2495
Read full office action

Prosecution Timeline

Jun 28, 2023
Application Filed
Aug 19, 2023
Response after Non-Final Action
Aug 12, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+21.8%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 623 resolved cases by this examiner. Grant probability derived from career allowance rate.

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