Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This action is in response to Applicant's filing on 29 June 2023. Claims 1-20 are presently pending and under consideration.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6th July 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities: the limitation “time” is omitted when compared to corresponding dependent claims 12 and 19. The claim should recite “wherein time to read a cache line is 96 Unit Intervals”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5, 6, 8-11, 13, 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Boles (US 2023/0367712 A1, hereinafter Boles) in view of Miller et al (US 2026/0064597 A1, hereinafter Miller).
Regarding claims 1, 9, and 16, taking claim 9 as exemplary, Boles discloses a system comprising: a memory controller (See Boles, Fig. 1, controller 115 and [0025] “The memory sub-system controller 115 can include a processing device, which includes one or more processors (e.g., processor 117), configured to execute instructions stored in a local memory 119”); and
a memory module, the memory module comprising: Input/Output interface logic to couple to the memory controller (See Boles, Fig. 1, disclosing memory device 125 interfaced with memory controller 115 and [0016] “A memory sub-system 110 can be a storage device, a memory module, or a combination of a storage device and memory module. Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMMs)”); and
a memory device, the memory device (See Boles, Fig. 1 disclosing memory device 125 and [0015] “The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 125). The volatile memory devices (e.g., memory device 125) can be, but are not limited to, random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM)”) comprising:
a memory array segmented into two equal size portions, each portion having a plurality of banks and segmented into two equal size sub-portions (See Boles, [0028], “sixteen memory banks grouped into four bank groups”, or in other words, two bank groups each having eight banks).
Boles does not disclose a cache line in the memory array accessed by accessing a first half of the cache line in parallel in all of the sub-portions and accessing a second half of the cache line in parallel in all of the sub-portions of the memory array after a gap time.
However, Miller discloses a cache line in the memory array accessed by accessing a first half of the cache line in parallel in all of the sub-portions and accessing a second half of the cache line in parallel in all of the sub-portions of the memory array after a gap time (See Miller [0014], disclosing “cache entries are split across multiple DRAM storage banks such that each cache-line read or write is effected by a time-staggered set of read or write operations within respective storage banks spanned by the target cache entry” and “each entry-spanned bank pair is constituted by one bank within an even-numbered bank group (the “even bank”) and another bank within an odd-numbered bank group (“the odd bank”), effectively pairing the bank groups themselves so that every incoming cache request triggers staggered memory access operations—for example, staggered by a minimum time between row activations in different bank groups—in both the odd bank/odd bank group and even bank/even bank group”).
Boles and Miller are analogous art directed to improved DRAM access techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the DRAM memory system of Boles with the staggered cache-line halves memory access operations of Miller as performance can be increased by allowing a host device to perceive a complete cache line is transferred in continuous data burst over the data links extending between the host device (See Miller [0014])
Regarding claims 2, 10, and 17, taking claim 10 as exemplary, Boles in view of Miller disclosed the system of claim 9 as above. Boles further discloses wherein the plurality of banks are configured as four bank groups with four banks per bank group (See Boles, [0010] A DRAM device includes multiple memory banks grouped in bank groups, e.g., sixteen memory banks grouped into four bank groups and [0028], “FIG. 1 illustrates sixteen memory banks grouped into four bank groups”).
Regarding claim 3, 11, and 18, taking claim 11 as exemplary, Boles in view of Miller disclosed the system of claim 9 as above. Miller further discloses wherein the cache line in the memory array is read by reading a first half of the cache line in parallel from all of the sub-portions and reading a second half of the cache line in parallel from all of the sub-portions of the memory array after a read gap time (See Miller [0014] “each cache entry is split (or striped or distributed) across paired banks disposed within respective (different) bank groups, with each constituent bank of the pair storing a respective half of the cache line together with a respective portion of tag-match/cache-line replacement information. In one implementation, for example, each entry-spanned bank pair is constituted by one bank within an even-numbered bank group (the “even bank”) and another bank within an odd-numbered bank group (“the odd bank”), effectively pairing the bank groups themselves so that every incoming cache request triggers staggered memory access operations—for example, staggered by a minimum time between row activations in different bank groups—in both the odd bank/odd bank group and even bank/even bank group”).
Regarding claims 6, 13, and 20, taking claim 13 as exemplary, Boles in view of Miller disclosed the system of claim 9 as above. Miller further discloses wherein the cache line in the memory array is written by writing a first half of the cache line in parallel in all of the sub-portions and reading a second half of the cache line in parallel in all of the sub-portions of the memory array after a write gap time (See Miller, [0014] “each cache entry is split (or striped or distributed) across paired banks disposed within respective (different) bank groups, with each constituent bank of the pair storing a respective half of the cache line together with a respective portion of tag-match/cache-line replacement information. In one implementation, for example, each entry-spanned bank pair is constituted by one bank within an even-numbered bank group (the “even bank”) and another bank within an odd-numbered bank group (“the odd bank”), effectively pairing the bank groups themselves so that every incoming cache request triggers staggered memory access operations—for example, staggered by a minimum time between row activations in different bank groups—in both the odd bank/odd bank group and even bank/even bank group”).
Regarding claim 5, Boles in view of Miller disclosed the memory device of claim 1 as above. Boles further discloses wherein the cache line in the memory array is read in response to a read command received by the Input/Output interface logic from the memory controller (See Boles [0019] “The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and read data from the memory sub-system 110” and [0024] “A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 125 to perform operations such as reading data, writing data, or erasing data at the memory devices 125 and other such operations”).
Regarding claim 8, Boles in view of Miller disclosed the memory device of claim 1 as above. Boles further discloses wherein the cache line in the memory array is written in response to a write command received by the Input/Output interface logic from the memory controller (See Boles, [0019] “The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and read data from the memory sub-system 110” [0024] “A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 125 to perform operations such as reading data, writing data, or erasing data at the memory devices 125 and other such operations”).
Regarding claim 15, Boles in view of Miller disclosed the system of claim 9 as above. Boles further discloses the system further comprising one or more of: at least one processor communicatively coupled to the memory controller; a display communicatively coupled to at least one processor; or a power supply to provide power to the system (See Boles, [0017] The computing system 100 can be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device).
Allowable Subject Matter
Claims 4, 7, 12, 14, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record:
Boles discloses a DRAM device including multiple memory banks grouped in bank groups, and in particular, sixteen memory banks grouped into four bank groups.
Miller discloses cache-line read or write is effected by a time-staggered set of read or write operations within respective storage banks spanned by the target cache entry.
Kim et al (US 2019/0267060 A1) discloses a DRAM four bank-group access mode may require a time interval corresponding to a tCCD_L when the same bank group is consecutively accessed and a tCCD_S time interval when different bank groups are consecutively accessed.
Agarwal et al (US 2019/0042500 A1) discloses different targeted ranks of memory chips that are multiplexed over a same burst window can be accessed at different time with respect to one another. For example, the rank of memory chips from the first group is accessed at a first clock phase and the rank of memory chirp from the second group is accessed at a second clock phase lagging the first.
However, the prior art alone or in combination fails to teach or fairly suggest the combination of a DRAM cache line read operation time is 96 Unit Intervals (UI) and the read gap time is 32 UI for a DRAM I/O speed greater than 9.6 Gbps up to 12.8 Gbps, as in dependent claims 4, 12, and 19.
The prior art alone or in combination also fails to teach or fairly suggest the combination of a DRAM cache line write operation time is 128 Unit Intervals (UI) and the write gap time is 64 UI for a DRAM I/O speed greater than 9.6 Gbps up to 12.8 Gbps, as in dependent claims 7 and 14.
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
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/E.H.K/Examiner, Art Unit 2137
/RYAN BERTRAM/Primary Examiner, Art Unit 2137
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