DETAILED ACTION
Claims 1-20 are pending.
Claims 21-27 are cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 02/13/2026, have been fully considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Conti et al.,
US Patent Application Publication No. 2007/0226795 (hereinafter Conti).
Regarding claims 1-20, Conti discloses all the claimed limitations, as outlined below:
Claims 1 and 8. An apparatus comprising: a register; a memory; and register control circuitry configured to: determine whether the memory includes reconfiguration data corresponding to a trigger event experienced by state machine circuitry, the reconfiguration data associated with the register; and based on determining that the memory includes the reconfiguration data corresponding to the trigger event, reconfigure the register with a value included in the reconfiguration data (Fig 19 and 20, PARA 0313-0316 and 0326 - - utilizing DMA registers after an event is detected and storing the configuration data).
Claims 2 and 9. The apparatus of claim 1, wherein the register control circuitry is configured to determine whether the state machine circuitry experienced the trigger event based on whether an interrupt from the state machine circuitry includes a trigger event code (Fig 19 and 20, PARA 0313-0316 and 0326 - - utilizing DMA registers after an event is detected and storing the configuration data).
Claims 3 and 10. The apparatus of claim 1, wherein the trigger event corresponds to a first trigger event code, the reconfiguration data includes trigger event data including a second trigger event code, and the register control circuitry is configured to, based on the state machine circuitry experiencing the trigger event: compare the first trigger event code to the second trigger event code; and based on the first trigger event code matching the second trigger event code, the reconfiguration data corresponding to the first trigger event (Fig 19 and 20, PARA 0313-0316 and 0326 - - utilizing DMA registers after an event is detected and storing the configuration data).
Claims 4 and 12. The apparatus of claim 1, wherein the reconfiguration data is to identify an address of the register and the value with which to reconfigure the register (Fig 19 and 20, PARA 0313-0316 and 0326 - - utilizing DMA registers after an event is detected and storing the configuration data).
Claim 5. The apparatus of claim 4, wherein the reconfiguration data includes trigger event data, the trigger event data to identify one or more trigger events after which to reconfigure the register (Fig 19 and 20, PARA 0313-0316 and 0326 - - utilizing DMA registers after an event is detected and storing the configuration data).
Claims 6 and 13. The apparatus of claim 1, including the state machine circuitry, the state machine circuitry configured to generate an interrupt after experiencing the trigger event (Fig 19 and 20, PARA 0313-0316 and 0326 - - utilizing DMA registers after an event is detected and storing the configuration data).
Claims 7 and 14. The apparatus of claim 1, including: communication protocol circuitry; and arbitration circuitry configured to resolve a conflict between a first configuration change request from the register control circuitry and a second configuration change request from the communication protocol circuitry (Fig 19 and 20, PARA 0313-0316 and 0326 - - utilizing DMA registers after an event is detected and storing the configuration data).
11. The apparatus of claim 8, wherein the memory is first memory, and the reconfigurable circuitry includes at least one of a first register, second memory, a first variable component including a second register, or a second variable component including switching circuitry (Fig 19 and 20, PARA 0313-0316 and 0326 - - utilizing DMA registers after an event is detected and storing the configuration data).
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hindle et al., US Patent No. 10,997,100 relates to - - communication interface between host system and state machine.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS R ORTIZ RODRIGUEZ whose telephone number is (571)272-3766. The examiner can normally be reached on Mon-Fri 10:00 am- 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mohammad Ali can be reached on 571-272-4105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CARLOS R ORTIZ RODRIGUEZ/ Primary Examiner, Art Unit 2119
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